From: Chen Lin <[email protected]>
Default reset value of secure banked register SMMU_sACR.cache_lock is 1.
If it is not been set to 0 by secure software(eg: atf), the non-secure
linux cannot clear ARM_MMU500_ACTLR_CPRE bit. In this situation,
the prefetcher errata is not applied successfully, warn once.
Signed-off-by: Chen Lin <[email protected]>
---
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c b/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c
index 658f3cc83278..2d2252b3e518 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c
@@ -136,6 +136,9 @@ int arm_mmu500_reset(struct arm_smmu_device *smmu)
reg = arm_smmu_cb_read(smmu, i, ARM_SMMU_CB_ACTLR);
reg &= ~ARM_MMU500_ACTLR_CPRE;
arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_ACTLR, reg);
+ reg = arm_smmu_cb_read(smmu, i, ARM_SMMU_CB_ACTLR);
+ if (reg & ARM_MMU500_ACTLR_CPRE)
+ dev_warn_once(smmu->dev, "Failed to alpply prefetcher errata patch, check SMMU_sACR.cache_lock\n");
}
return 0;
--
2.25.1
On Sat, Oct 22, 2022 at 10:45:59AM +0800, Chen Lin wrote:
> From: Chen Lin <[email protected]>
>
> Default reset value of secure banked register SMMU_sACR.cache_lock is 1.
> If it is not been set to 0 by secure software(eg: atf), the non-secure
> linux cannot clear ARM_MMU500_ACTLR_CPRE bit. In this situation,
> the prefetcher errata is not applied successfully, warn once.
>
> Signed-off-by: Chen Lin <[email protected]>
> ---
> drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 3 +++
> 1 file changed, 3 insertions(+)
As has been stated many times before, please fix your email systems and
stop using personal accounts, if you wish for us to think that you
really are developing from a zte.com.cn account.
thanks,
greg k-h