Hello again everyone!
This series enabled the VTM nodes for all of Texas Instruments K3 SoCs
Most of this series updates the k3_j72xx_bandgap driver to conditionally
map an eFuse region used by the j721e to work around an issue in its VTM
implementation and allows us to save the SPARE_FUSE region on other SoCs
We can then update the device tree bindings for the driver and finally
define the VTM nodes for each device
Thanks for reviewing!
~Bryan
****
v1 -> v2 changes[0]:
- when removing 'fuse_base' from the 'k3_j72xx_bandgap' structure, I
forgot to pass 'fuse_base' to get_efuse_values()
- removed the descriptions to the generic 'power-domains' property
- incorporated Krzysztof's suggestions to the binding description
- refactored binding to use allOf: if: {min,max}Items over what I was
doing :) Thanks Krzysztof
[0] https://lore.kernel.org/lkml/[email protected]/
Bryan Brattlof (11):
thermal: k3_j72xx_bandgap: simplify k3_thermal_get_temp() function
thermal: k3_j72xx_bandgap: use bool for i2128 erratum flag
thermal: k3_j72xx_bandgap: remove fuse_base from structure
thermal: k3_j72xx_bandgap: map fuse_base only for erratum workaround
dt-bindings: thermal: k3-j72xx: elaborate on binding description
dt-bindings: thermal: k3-j72xx: conditionally require efuse reg range
arm64: dts: ti: k3-am64-main: add VTM node
arm64: dts: ti: k3-am62-wakeup: add VTM node
arm64: dts: ti: k3-j721e-mcu-wakeup: add VTM node
arm64: dts: ti: k3-j721s2-mcu-wakeup: add VTM node
arm64: dts: ti: k3-j7200-mcu-wakeup: add VTM node
.../bindings/thermal/ti,j72xx-thermal.yaml | 35 +++++-
arch/arm64/boot/dts/ti/k3-am62-thermal.dtsi | 33 ++++++
arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi | 8 ++
arch/arm64/boot/dts/ti/k3-am62.dtsi | 7 +-
arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 8 ++
arch/arm64/boot/dts/ti/k3-am64-thermal.dtsi | 33 ++++++
arch/arm64/boot/dts/ti/k3-am64.dtsi | 4 +
.../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 8 ++
arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi | 47 ++++++++
arch/arm64/boot/dts/ti/k3-j7200.dtsi | 3 +
.../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 9 ++
arch/arm64/boot/dts/ti/k3-j721e-thermal.dtsi | 75 +++++++++++++
arch/arm64/boot/dts/ti/k3-j721e.dtsi | 3 +
.../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 8 ++
arch/arm64/boot/dts/ti/k3-j721s2-thermal.dtsi | 103 ++++++++++++++++++
arch/arm64/boot/dts/ti/k3-j721s2.dtsi | 3 +
drivers/thermal/k3_j72xx_bandgap.c | 67 ++++++------
17 files changed, 420 insertions(+), 34 deletions(-)
create mode 100644 arch/arm64/boot/dts/ti/k3-am62-thermal.dtsi
create mode 100644 arch/arm64/boot/dts/ti/k3-am64-thermal.dtsi
create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi
create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-thermal.dtsi
create mode 100644 arch/arm64/boot/dts/ti/k3-j721s2-thermal.dtsi
--
2.38.1
The j721s2 supports a single Voltage and Thermal Management (VTM) device
located in the wakeup domain with seven associated temperature monitors
located in various hot spots on the die.
Signed-off-by: Bryan Brattlof <[email protected]>
---
.../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 8 ++
arch/arm64/boot/dts/ti/k3-j721s2-thermal.dtsi | 103 ++++++++++++++++++
arch/arm64/boot/dts/ti/k3-j721s2.dtsi | 3 +
3 files changed, 114 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-j721s2-thermal.dtsi
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
index 4d1bfabd1313a..8287fd32c42f3 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
@@ -299,4 +299,12 @@ cpts@3d000 {
ti,cpts-periodic-outputs = <2>;
};
};
+
+ vtm0: temperature-sensor@42040000 {
+ compatible = "ti,j7200-vtm";
+ reg = <0x0 0x42040000 0x0 0x350>,
+ <0x0 0x42050000 0x0 0x350>;
+ power-domains = <&k3_pds 154 TI_SCI_PD_SHARED>;
+ #thermal-sensor-cells = <1>;
+ };
};
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-thermal.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-thermal.dtsi
new file mode 100644
index 0000000000000..c51009536756e
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-thermal.dtsi
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/thermal/thermal.h>
+
+thermal_zones: thermal-zones {
+ wkup0_thermal: wkup0-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&vtm0 0>;
+
+ trips {
+ wkup0_crit: wkup0-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ wkup1_thermal: wkup1-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&vtm0 1>;
+
+ trips {
+ wkup1_crit: wkup1-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ main0_thermal: main0-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&vtm0 2>;
+
+ trips {
+ main0_crit: main0-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ main1_thermal: main1-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&vtm0 3>;
+
+ trips {
+ main1_crit: main1-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ main2_thermal: main2-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&vtm0 4>;
+
+ trips {
+ main2_crit: main2-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ main3_thermal: main3-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&vtm0 5>;
+
+ trips {
+ main3_crit: main3-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ main4_thermal: main4-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&vtm0 6>;
+
+ trips {
+ main4_crit: main4-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi
index 7b930a85a29d6..33ea52e28b24f 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi
@@ -161,6 +161,9 @@ cbass_mcu_wakeup: bus@28380000 {
};
};
+
+ #include "k3-j721s2-thermal.dtsi"
+
};
/* Now include peripherals from each bus segment */
--
2.38.1
The am64x supports a single VTM module which is located in the main
domain with two associated temperature monitors located at different hot
spots on the die.
Signed-off-by: Bryan Brattlof <[email protected]>
---
arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 8 +++++
arch/arm64/boot/dts/ti/k3-am64-thermal.dtsi | 33 +++++++++++++++++++++
arch/arm64/boot/dts/ti/k3-am64.dtsi | 4 +++
3 files changed, 45 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-am64-thermal.dtsi
diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index d6aa23681bbe5..a31a139127e35 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -1356,4 +1356,12 @@ elm0: ecc@25010000 {
clocks = <&k3_clks 54 0>;
clock-names = "fck";
};
+
+ vtm0: temperature-sensor@b00000 {
+ compatible = "ti,j7200-vtm";
+ reg = <0x00 0xb00000 0x00 0x400>,
+ <0x00 0xb01000 0x00 0x400>;
+ power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>;
+ #thermal-sensor-cells = <1>;
+ };
};
diff --git a/arch/arm64/boot/dts/ti/k3-am64-thermal.dtsi b/arch/arm64/boot/dts/ti/k3-am64-thermal.dtsi
new file mode 100644
index 0000000000000..1819a6948b19d
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am64-thermal.dtsi
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/thermal/thermal.h>
+
+thermal_zones: thermal-zones {
+ main0_thermal: main0-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&vtm0 0>;
+
+ trips {
+ main0_crit: main0-crit {
+ temperature = <105000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ main1_thermal: main1-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&vtm0 1>;
+
+ trips {
+ main1_crit: main1-crit {
+ temperature = <105000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/ti/k3-am64.dtsi b/arch/arm64/boot/dts/ti/k3-am64.dtsi
index c858725133af4..a0170605d7b4e 100644
--- a/arch/arm64/boot/dts/ti/k3-am64.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64.dtsi
@@ -69,6 +69,7 @@ cbass_main: bus@f4000 {
<0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
<0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
+ <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
<0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */
<0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
<0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */
@@ -105,6 +106,9 @@ cbass_mcu: bus@4000000 {
ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */
};
};
+
+ #include "k3-am64-thermal.dtsi"
+
};
/* Now include the peripherals for each bus segments */
--
2.38.1
Only some of TI's J721E SoCs will need a eFuse register range mapped to
determine if they're affected by TI's i2128 erratum. All other SoC will
not need this eFuse range to function properly
Update the bindings for the k3_j72xx_bandgap thermal driver so other
devices will only need two register ranges
Signed-off-by: Bryan Brattlof <[email protected]>
---
.../bindings/thermal/ti,j72xx-thermal.yaml | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/Documentation/devicetree/bindings/thermal/ti,j72xx-thermal.yaml b/Documentation/devicetree/bindings/thermal/ti,j72xx-thermal.yaml
index 3bb870a26872f..0509c9cec224d 100644
--- a/Documentation/devicetree/bindings/thermal/ti,j72xx-thermal.yaml
+++ b/Documentation/devicetree/bindings/thermal/ti,j72xx-thermal.yaml
@@ -37,6 +37,7 @@ properties:
devices to function properly. This eFuse region provides
the information needed for these SoCs to report
temperatures accurately.
+ minItems: 2
power-domains:
maxItems: 1
@@ -44,6 +45,21 @@ properties:
"#thermal-sensor-cells":
const: 1
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: ti,j721e-vtm
+ then:
+ properties:
+ reg:
+ minItems: 3
+ else:
+ properties:
+ reg:
+ maxItems: 2
+
required:
- compatible
- reg
--
2.38.1
The j7200 supports a single Voltage and Thermal Management (VTM) device
located in the wakeup domain with three associated temperature monitors
located in various hot spots on the die.
Signed-off-by: Bryan Brattlof <[email protected]>
---
.../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 8 ++++
arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi | 47 +++++++++++++++++++
arch/arm64/boot/dts/ti/k3-j7200.dtsi | 3 ++
3 files changed, 58 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
index e5be78a58682d..651d17dd20663 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
@@ -395,4 +395,12 @@ rng: rng@40910000 {
status = "disabled"; /* Used by OP-TEE */
};
};
+
+ vtm0: temperature-sensor@42040000 {
+ compatible = "ti,j7200-vtm";
+ reg = <0x00 0x42040000 0x00 0x350>,
+ <0x00 0x42050000 0x00 0x350>;
+ power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
+ #thermal-sensor-cells = <1>;
+ };
};
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi
new file mode 100644
index 0000000000000..0bf52c93c3f9a
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/thermal/thermal.h>
+
+thermal_zones: thermal-zones {
+ mcu_thermal: mcu-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&vtm0 0>;
+
+ trips {
+ wkup_crit: wkup-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ mpu_thermal: mpu-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&vtm0 1>;
+
+ trips {
+ mpu_crit: mpu-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ main_thermal: main-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&vtm0 2>;
+
+ trips {
+ c7x_crit: c7x-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
index b6da0454cc5bd..9368a6e3d4a62 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
@@ -168,6 +168,9 @@ cbass_mcu_wakeup: bus@28380000 {
<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3 */
};
};
+
+ #include "k3-j7200-thermal.dtsi"
+
};
/* Now include the peripherals for each bus segments */
--
2.38.1
Some of TI's J721E's require a software trimming method to report
temperatures accurately. Currently we are using a few different data
types to indicate when this device should apply the erratum.
Change the 'workaround_needed' variable's data type to a bool to align
with how we are using this variable currently.
Signed-off-by: Bryan Brattlof <[email protected]>
---
drivers/thermal/k3_j72xx_bandgap.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/thermal/k3_j72xx_bandgap.c b/drivers/thermal/k3_j72xx_bandgap.c
index a9f99a190cb61..b9d20026771a5 100644
--- a/drivers/thermal/k3_j72xx_bandgap.c
+++ b/drivers/thermal/k3_j72xx_bandgap.c
@@ -340,7 +340,7 @@ static void print_look_up_table(struct device *dev, int *ref_table)
}
struct k3_j72xx_bandgap_data {
- unsigned int has_errata_i2128;
+ const bool has_errata_i2128;
};
static int k3_j72xx_bandgap_probe(struct platform_device *pdev)
@@ -351,7 +351,7 @@ static int k3_j72xx_bandgap_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct k3_j72xx_bandgap *bgp;
struct k3_thermal_data *data;
- int workaround_needed = 0;
+ bool workaround_needed = false;
const struct k3_j72xx_bandgap_data *driver_data;
struct thermal_zone_device *ti_thermal;
int *ref_table;
@@ -522,11 +522,11 @@ static int k3_j72xx_bandgap_remove(struct platform_device *pdev)
}
static const struct k3_j72xx_bandgap_data k3_j72xx_bandgap_j721e_data = {
- .has_errata_i2128 = 1,
+ .has_errata_i2128 = true,
};
static const struct k3_j72xx_bandgap_data k3_j72xx_bandgap_j7200_data = {
- .has_errata_i2128 = 0,
+ .has_errata_i2128 = false,
};
static const struct of_device_id of_k3_j72xx_bandgap_match[] = {
--
2.38.1
On 25/10/2022 15:15, Bryan Brattlof wrote:
> Only some of TI's J721E SoCs will need a eFuse register range mapped to
> determine if they're affected by TI's i2128 erratum. All other SoC will
> not need this eFuse range to function properly
>
> Update the bindings for the k3_j72xx_bandgap thermal driver so other
> devices will only need two register ranges
>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof