2022-10-13 18:44:21

by Vidya Sagar

Subject: [PATCH V5 2/3] PCI: qcom-ep: Refactor EP initialization completion

Move the post initialization code to .ep_init_late() call back and call
only dw_pcie_ep_init_notify() which internally takes care of calling
dw_pcie_ep_init_complete().

Signed-off-by: Vidya Sagar <[email protected]>
---
V5:
* None

V4:
* New patch in this series

drivers/pci/controller/dwc/pcie-qcom-ep.c | 27 ++++++++++++++---------
1 file changed, 16 insertions(+), 11 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
index e33eb3871309..c418b20042aa 100644
--- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
+++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
@@ -361,22 +361,12 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci)
PARF_INT_ALL_LINK_UP;
writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_MASK);

- ret = dw_pcie_ep_init_complete(&pcie_ep->pci.ep);
+ ret = dw_pcie_ep_init_notify(&pcie_ep->pci.ep);
if (ret) {
dev_err(dev, "Failed to complete initialization: %d\n", ret);
goto err_disable_resources;
}

- /*
- * The physical address of the MMIO region which is exposed as the BAR
- * should be written to MHI BASE registers.
- */
- writel_relaxed(pcie_ep->mmio_res->start,
- pcie_ep->parf + PARF_MHI_BASE_ADDR_LOWER);
- writel_relaxed(0, pcie_ep->parf + PARF_MHI_BASE_ADDR_UPPER);
-
- dw_pcie_ep_init_notify(&pcie_ep->pci.ep);
-
/* Enable LTSSM */
val = readl_relaxed(pcie_ep->parf + PARF_LTSSM);
val |= BIT(8);
@@ -643,8 +633,23 @@ static void qcom_pcie_ep_init(struct dw_pcie_ep *ep)
dw_pcie_ep_reset_bar(pci, bar);
}

+static void qcom_pcie_ep_init_late(struct dw_pcie_ep *ep)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
+
+ /*
+ * The physical address of the MMIO region which is exposed as the BAR
+ * should be written to MHI BASE registers.
+ */
+ writel_relaxed(pcie_ep->mmio_res->start,
+ pcie_ep->parf + PARF_MHI_BASE_ADDR_LOWER);
+ writel_relaxed(0, pcie_ep->parf + PARF_MHI_BASE_ADDR_UPPER);
+}
+
static const struct dw_pcie_ep_ops pci_ep_ops = {
.ep_init = qcom_pcie_ep_init,
+ .ep_init_late = qcom_pcie_ep_init_late,
.raise_irq = qcom_pcie_ep_raise_irq,
.get_features = qcom_pcie_epc_get_features,
};
--
2.17.1

2022-10-26 05:54:41

by Manivannan Sadhasivam

Subject: Re: [PATCH V5 2/3] PCI: qcom-ep: Refactor EP initialization completion

On Thu, Oct 13, 2022 at 11:27:11PM +0530, Vidya Sagar wrote:
> Move the post initialization code to .ep_init_late() call back and call
> only dw_pcie_ep_init_notify() which internally takes care of calling
> dw_pcie_ep_init_complete().
>
> Signed-off-by: Vidya Sagar <[email protected]>
> ---
> V5:
> * None
>
> V4:
> * New patch in this series
>
> drivers/pci/controller/dwc/pcie-qcom-ep.c | 27 ++++++++++++++---------
> 1 file changed, 16 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
> index e33eb3871309..c418b20042aa 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
> @@ -361,22 +361,12 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci)
> PARF_INT_ALL_LINK_UP;
> writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_MASK);
>
> - ret = dw_pcie_ep_init_complete(&pcie_ep->pci.ep);
> + ret = dw_pcie_ep_init_notify(&pcie_ep->pci.ep);
> if (ret) {
> dev_err(dev, "Failed to complete initialization: %d\n", ret);
> goto err_disable_resources;
> }
>
> - /*
> - * The physical address of the MMIO region which is exposed as the BAR
> - * should be written to MHI BASE registers.
> - */
> - writel_relaxed(pcie_ep->mmio_res->start,
> - pcie_ep->parf + PARF_MHI_BASE_ADDR_LOWER);
> - writel_relaxed(0, pcie_ep->parf + PARF_MHI_BASE_ADDR_UPPER);

Writes to the MHI base addresses are required before starting LTSSM and not
necessarily before core_init notifier. So you could just leave this code here
and get rid of .ep_init_late() callback.

And you should also rebase the series on top of v6.1-rcX as I've added few more
code in this function.

Thanks,
Mani

> -
> - dw_pcie_ep_init_notify(&pcie_ep->pci.ep);
> -
> /* Enable LTSSM */
> val = readl_relaxed(pcie_ep->parf + PARF_LTSSM);
> val |= BIT(8);
> @@ -643,8 +633,23 @@ static void qcom_pcie_ep_init(struct dw_pcie_ep *ep)
> dw_pcie_ep_reset_bar(pci, bar);
> }
>
> +static void qcom_pcie_ep_init_late(struct dw_pcie_ep *ep)
> +{
> + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> + struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
> +
> + /*
> + * The physical address of the MMIO region which is exposed as the BAR
> + * should be written to MHI BASE registers.
> + */
> + writel_relaxed(pcie_ep->mmio_res->start,
> + pcie_ep->parf + PARF_MHI_BASE_ADDR_LOWER);
> + writel_relaxed(0, pcie_ep->parf + PARF_MHI_BASE_ADDR_UPPER);
> +}
> +
> static const struct dw_pcie_ep_ops pci_ep_ops = {
> .ep_init = qcom_pcie_ep_init,
> + .ep_init_late = qcom_pcie_ep_init_late,
> .raise_irq = qcom_pcie_ep_raise_irq,
> .get_features = qcom_pcie_epc_get_features,
> };
> --
> 2.17.1
>

--
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