From: Runyang Chen <[email protected]>
Based on tag: next-20220919, linux-next/master
Refer to the discussion in the link:
https://patchwork.kernel.org/project/linux-mediatek/patch/[email protected]/
The other wdt compatible strings are unchanged.So, won't apply the
series above
v3:
Rebase on 6.0-rc5 and add reviewed-by and acked-by tag.
v2:
Revert wdt compatible for MT8188.
v1:
1. Add mt8188-resets.h to define definition of reset bits.
2. Add wdt compatible for MT8188.*
Runyang Chen (3):
dt-bindings: watchdog: Add compatible for MediaTek MT8188
dt-bindings: reset: mt8188: add toprgu reset-controller header file
watchdog: mediatek: mt8188: add wdt support
.../devicetree/bindings/watchdog/mtk-wdt.txt | 1 +
drivers/watchdog/mtk_wdt.c | 6 ++++
include/dt-bindings/reset/mt8188-resets.h | 36 +++++++++++++++++++
3 files changed, 43 insertions(+)
create mode 100644 include/dt-bindings/reset/mt8188-resets.h
base-commit: 4c9ca5b1597e3222177ba2a94658f78fa5ef4f58
--
2.18.0
From: Runyang Chen <[email protected]>
Add toprgu reset-controller header file for MT8188
Signed-off-by: Runyang Chen <[email protected]>
Acked-by: Rob Herring <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
---
include/dt-bindings/reset/mt8188-resets.h | 36 +++++++++++++++++++++++
1 file changed, 36 insertions(+)
create mode 100644 include/dt-bindings/reset/mt8188-resets.h
diff --git a/include/dt-bindings/reset/mt8188-resets.h b/include/dt-bindings/reset/mt8188-resets.h
new file mode 100644
index 000000000000..377cdfda82a9
--- /dev/null
+++ b/include/dt-bindings/reset/mt8188-resets.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)*/
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ * Author: Runyang Chen <[email protected]>
+ */
+
+#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8188
+#define _DT_BINDINGS_RESET_CONTROLLER_MT8188
+
+#define MT8188_TOPRGU_CONN_MCU_SW_RST 0
+#define MT8188_TOPRGU_INFRA_GRST_SW_RST 1
+#define MT8188_TOPRGU_IPU0_SW_RST 2
+#define MT8188_TOPRGU_IPU1_SW_RST 3
+#define MT8188_TOPRGU_IPU2_SW_RST 4
+#define MT8188_TOPRGU_AUD_ASRC_SW_RST 5
+#define MT8188_TOPRGU_INFRA_SW_RST 6
+#define MT8188_TOPRGU_MMSYS_SW_RST 7
+#define MT8188_TOPRGU_MFG_SW_RST 8
+#define MT8188_TOPRGU_VENC_SW_RST 9
+#define MT8188_TOPRGU_VDEC_SW_RST 10
+#define MT8188_TOPRGU_CAM_VCORE_SW_RST 11
+#define MT8188_TOPRGU_SCP_SW_RST 12
+#define MT8188_TOPRGU_APMIXEDSYS_SW_RST 13
+#define MT8188_TOPRGU_AUDIO_SW_RST 14
+#define MT8188_TOPRGU_CAMSYS_SW_RST 15
+#define MT8188_TOPRGU_MJC_SW_RST 16
+#define MT8188_TOPRGU_PERI_SW_RST 17
+#define MT8188_TOPRGU_PERI_AO_SW_RST 18
+#define MT8188_TOPRGU_PCIE_SW_RST 19
+#define MT8188_TOPRGU_ADSPSYS_SW_RST 21
+#define MT8188_TOPRGU_DPTX_SW_RST 22
+#define MT8188_TOPRGU_SPMI_MST_SW_RST 23
+
+#define MT8188_TOPRGU_SW_RST_NUM 24
+
+#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8188 */
--
2.18.0
On Wed, Oct 26, 2022 at 02:33:26PM +0800, Runyang Chen wrote:
> From: Runyang Chen <[email protected]>
>
> Add toprgu reset-controller header file for MT8188
>
> Signed-off-by: Runyang Chen <[email protected]>
> Acked-by: Rob Herring <[email protected]>
> Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Guenter Roeck <[email protected]>
> ---
> include/dt-bindings/reset/mt8188-resets.h | 36 +++++++++++++++++++++++
> 1 file changed, 36 insertions(+)
> create mode 100644 include/dt-bindings/reset/mt8188-resets.h
>
> diff --git a/include/dt-bindings/reset/mt8188-resets.h b/include/dt-bindings/reset/mt8188-resets.h
> new file mode 100644
> index 000000000000..377cdfda82a9
> --- /dev/null
> +++ b/include/dt-bindings/reset/mt8188-resets.h
> @@ -0,0 +1,36 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)*/
> +/*
> + * Copyright (c) 2022 MediaTek Inc.
> + * Author: Runyang Chen <[email protected]>
> + */
> +
> +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8188
> +#define _DT_BINDINGS_RESET_CONTROLLER_MT8188
> +
> +#define MT8188_TOPRGU_CONN_MCU_SW_RST 0
> +#define MT8188_TOPRGU_INFRA_GRST_SW_RST 1
> +#define MT8188_TOPRGU_IPU0_SW_RST 2
> +#define MT8188_TOPRGU_IPU1_SW_RST 3
> +#define MT8188_TOPRGU_IPU2_SW_RST 4
> +#define MT8188_TOPRGU_AUD_ASRC_SW_RST 5
> +#define MT8188_TOPRGU_INFRA_SW_RST 6
> +#define MT8188_TOPRGU_MMSYS_SW_RST 7
> +#define MT8188_TOPRGU_MFG_SW_RST 8
> +#define MT8188_TOPRGU_VENC_SW_RST 9
> +#define MT8188_TOPRGU_VDEC_SW_RST 10
> +#define MT8188_TOPRGU_CAM_VCORE_SW_RST 11
> +#define MT8188_TOPRGU_SCP_SW_RST 12
> +#define MT8188_TOPRGU_APMIXEDSYS_SW_RST 13
> +#define MT8188_TOPRGU_AUDIO_SW_RST 14
> +#define MT8188_TOPRGU_CAMSYS_SW_RST 15
> +#define MT8188_TOPRGU_MJC_SW_RST 16
> +#define MT8188_TOPRGU_PERI_SW_RST 17
> +#define MT8188_TOPRGU_PERI_AO_SW_RST 18
> +#define MT8188_TOPRGU_PCIE_SW_RST 19
> +#define MT8188_TOPRGU_ADSPSYS_SW_RST 21
> +#define MT8188_TOPRGU_DPTX_SW_RST 22
> +#define MT8188_TOPRGU_SPMI_MST_SW_RST 23
> +
> +#define MT8188_TOPRGU_SW_RST_NUM 24
> +
> +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8188 */