SM6125 comes with SDCC (SDHCI controller) v5, so the second range of
registers is cqhci, not core.
Fixes: cff4bbaf2a2d ("arm64: dts: qcom: Add support for SM6125")
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
Not tested on hardware, but no practical impact is expected, because
supports-cqe is not defined.
---
arch/arm64/boot/dts/qcom/sm6125.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
index af49a748e511..24ee7c0c1195 100644
--- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
@@ -458,7 +458,7 @@ rpm_msg_ram: sram@45f0000 {
sdhc_1: mmc@4744000 {
compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
reg = <0x04744000 0x1000>, <0x04745000 0x1000>;
- reg-names = "hc", "core";
+ reg-names = "hc", "cqhci";
interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
--
2.34.1
On 2022-10-26 12:36:46, Krzysztof Kozlowski wrote:
> SM6125 comes with SDCC (SDHCI controller) v5, so the second range of
> registers is cqhci, not core.
>
> Fixes: cff4bbaf2a2d ("arm64: dts: qcom: Add support for SM6125")
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
>
> ---
>
> Not tested on hardware, but no practical impact is expected, because
> supports-cqe is not defined.
Thanks for this! According to my downstream sources this reg is called
cmdq_mem, that's not core indeed.
Reviewed-by: Marijn Suijten <[email protected]>
Tested-by: Marijn Suijten <[email protected]> # Sony Xperia 10 II
And also according to my downstream sources, this SoC should support it.
When adding supports-cqe _together with your patch_:
[ 0.391950] sdhci_msm 4744000.mmc: mmc0: CQE init: success
I'll send a followup to that effect. Thanks again for bringing this to
my attention!
- Marijn
> ---
> arch/arm64/boot/dts/qcom/sm6125.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
> index af49a748e511..24ee7c0c1195 100644
> --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
> @@ -458,7 +458,7 @@ rpm_msg_ram: sram@45f0000 {
> sdhc_1: mmc@4744000 {
> compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
> reg = <0x04744000 0x1000>, <0x04745000 0x1000>;
> - reg-names = "hc", "core";
> + reg-names = "hc", "cqhci";
>
> interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
> --
> 2.34.1
>
On Wed, 26 Oct 2022 12:36:46 -0400, Krzysztof Kozlowski wrote:
> SM6125 comes with SDCC (SDHCI controller) v5, so the second range of
> registers is cqhci, not core.
>
>
Applied, thanks!
[1/1] arm64: dts: qcom: sm6125: fix SDHCI CQE reg names
commit: 3de1172624b3c4ca65730bc34333ab493510b3e1
Best regards,
--
Bjorn Andersson <[email protected]>