SM8350 does not have the EDP_GTC clock, so let's disable it
for this SoC.
Signed-off-by: Robert Foss <[email protected]>
---
drivers/clk/qcom/dispcc-sm8250.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c
index 709076f0f9d7..180ac2726f7e 100644
--- a/drivers/clk/qcom/dispcc-sm8250.c
+++ b/drivers/clk/qcom/dispcc-sm8250.c
@@ -1330,6 +1330,9 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev)
disp_cc_pll1_config.test_ctl_hi1_val = 0x01800000;
disp_cc_pll1_init.ops = &clk_alpha_pll_lucid_5lpe_ops;
disp_cc_pll1.vco_table = lucid_5lpe_vco;
+
+ disp_cc_sm8250_clocks[DISP_CC_MDSS_EDP_GTC_CLK] = NULL;
+ disp_cc_sm8250_clocks[DISP_CC_MDSS_EDP_GTC_CLK_SRC] = NULL;
}
clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
--
2.34.1
All SoC supported by this driver supports the RETAIN_FF_ENABLE flag,
so it should be enabled here.
This feature enables registers to maintain their state after
dis/re-enabling the GDSC.
Signed-off-by: Robert Foss <[email protected]>
---
drivers/clk/qcom/dispcc-sm8250.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c
index 180ac2726f7e..a7606580cf22 100644
--- a/drivers/clk/qcom/dispcc-sm8250.c
+++ b/drivers/clk/qcom/dispcc-sm8250.c
@@ -1137,7 +1137,7 @@ static struct gdsc mdss_gdsc = {
.name = "mdss_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
- .flags = HW_CTRL,
+ .flags = HW_CTRL | RETAIN_FF_ENABLE,
};
static struct clk_regmap *disp_cc_sm8250_clocks[] = {
--
2.34.1