Unlike the old design that the register setting of the TACH should based
on the configure of the PWM. In ast26xx, the dependency between pwm and
tach controller is eliminated and becomes a separate hardware block. One
is used to provide pwm output and another is used to monitor the frequency
of the input. Therefore, this patch serials implements them by writing the
two driver "pwm-aspeed-ast2600.c" and "tach-aspeed-ast2600.c". The former
is following the pwm subsystem which can apply the existed driver to
controller the fan(pwm-fan.c), beeper(pwm-beeper.c) and so on. The latter
is following the sysfs interface of hwmon to creat the node for fan
monitor.
Billy Tsai (3):
dt-bindings: Add bindings for aspeed pwm-tach.
pwm: Add Aspeed ast2600 PWM support
hwmon: Add Aspeed ast2600 TACH support
.../bindings/hwmon/aspeed,ast2600-tach.yaml | 48 ++
.../bindings/mfd/aspeed,ast2600-pwm-tach.yaml | 76 ++
.../bindings/pwm/aspeed,ast2600-pwm.yaml | 64 ++
drivers/hwmon/Kconfig | 9 +
drivers/hwmon/Makefile | 1 +
drivers/hwmon/tach-aspeed-ast2600.c | 692 ++++++++++++++++++
drivers/pwm/Kconfig | 10 +
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-aspeed-ast2600.c | 325 ++++++++
9 files changed, 1226 insertions(+)
create mode 100644 Documentation/devicetree/bindings/hwmon/aspeed,ast2600-tach.yaml
create mode 100644 Documentation/devicetree/bindings/mfd/aspeed,ast2600-pwm-tach.yaml
create mode 100644 Documentation/devicetree/bindings/pwm/aspeed,ast2600-pwm.yaml
create mode 100644 drivers/hwmon/tach-aspeed-ast2600.c
create mode 100644 drivers/pwm/pwm-aspeed-ast2600.c
--
2.25.1
This patch add the support of Tachometer which can use to monitor the
frequency of the input. The tach supports up to 16 channels and it's part
function of multi-function device "pwm-tach controller".
Signed-off-by: Billy Tsai <[email protected]>
---
drivers/hwmon/Kconfig | 9 +
drivers/hwmon/Makefile | 1 +
drivers/hwmon/tach-aspeed-ast2600.c | 692 ++++++++++++++++++++++++++++
3 files changed, 702 insertions(+)
create mode 100644 drivers/hwmon/tach-aspeed-ast2600.c
diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index fa2356398744..a84c15b73aa6 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -397,6 +397,15 @@ config SENSORS_ASPEED
This driver can also be built as a module. If so, the module
will be called aspeed_pwm_tacho.
+config SENSORS_TACH_ASPEED_AST2600
+ tristate "ASPEED ast2600 Tachometer support"
+ select REGMAP
+ help
+ This driver provides support for Aspeed ast2600 Tachometer.
+
+ To compile this driver as a module, choose M here: the module
+ will be called tach-aspeed-ast2600.
+
config SENSORS_ATXP1
tristate "Attansic ATXP1 VID controller"
depends on I2C
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index d2497b2644e6..7e2d708e93b8 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -51,6 +51,7 @@ obj-$(CONFIG_SENSORS_ARM_SCMI) += scmi-hwmon.o
obj-$(CONFIG_SENSORS_ARM_SCPI) += scpi-hwmon.o
obj-$(CONFIG_SENSORS_AS370) += as370-hwmon.o
obj-$(CONFIG_SENSORS_ASC7621) += asc7621.o
+obj-$(CONFIG_SENSORS_TACH_ASPEED_AST2600) += tach-aspeed-ast2600.o
obj-$(CONFIG_SENSORS_ASPEED) += aspeed-pwm-tacho.o
obj-$(CONFIG_SENSORS_ATXP1) += atxp1.o
obj-$(CONFIG_SENSORS_AXI_FAN_CONTROL) += axi-fan-control.o
diff --git a/drivers/hwmon/tach-aspeed-ast2600.c b/drivers/hwmon/tach-aspeed-ast2600.c
new file mode 100644
index 000000000000..c5250ea8a16d
--- /dev/null
+++ b/drivers/hwmon/tach-aspeed-ast2600.c
@@ -0,0 +1,692 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) ASPEED Technology Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/hwmon.h>
+#include <linux/hwmon-sysfs.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/mfd/syscon.h>
+#include <linux/sysfs.h>
+#include <linux/reset.h>
+#include <linux/regmap.h>
+#include <linux/bitfield.h>
+
+/* The channel number of Aspeed tach controller */
+#define TACH_ASPEED_NR_TACHS 16
+/* TACH Control Register */
+#define TACH_ASPEED_CTRL(ch) (((ch) * 0x10) + 0x08)
+#define TACH_ASPEED_IER BIT(31)
+#define TACH_ASPEED_INVERS_LIMIT BIT(30)
+#define TACH_ASPEED_LOOPBACK BIT(29)
+#define TACH_ASPEED_ENABLE BIT(28)
+#define TACH_ASPEED_DEBOUNCE_MASK GENMASK(27, 26)
+#define TACH_ASPEED_DEBOUNCE_BIT (26)
+#define TACH_ASPEED_IO_EDGE_MASK GENMASK(25, 24)
+#define TACH_ASPEED_IO_EDGE_BIT (24)
+#define TACH_ASPEED_CLK_DIV_T_MASK GENMASK(23, 20)
+#define TACH_ASPEED_CLK_DIV_BIT (20)
+#define TACH_ASPEED_THRESHOLD_MASK GENMASK(19, 0)
+/* [27:26] */
+#define DEBOUNCE_3_CLK 0x00
+#define DEBOUNCE_2_CLK 0x01
+#define DEBOUNCE_1_CLK 0x02
+#define DEBOUNCE_0_CLK 0x03
+/* [25:24] */
+#define F2F_EDGES 0x00
+#define R2R_EDGES 0x01
+#define BOTH_EDGES 0x02
+/* [23:20] */
+/* divisor = 4 to the nth power, n = register value */
+#define DEFAULT_TACH_DIV 1024
+#define DIV_TO_REG(divisor) (ilog2(divisor) >> 1)
+
+/* TACH Status Register */
+#define TACH_ASPEED_STS(ch) (((ch) * 0x10) + 0x0C)
+
+/*PWM_TACH_STS */
+#define TACH_ASPEED_ISR BIT(31)
+#define TACH_ASPEED_PWM_OUT BIT(25)
+#define TACH_ASPEED_PWM_OEN BIT(24)
+#define TACH_ASPEED_DEB_INPUT BIT(23)
+#define TACH_ASPEED_RAW_INPUT BIT(22)
+#define TACH_ASPEED_VALUE_UPDATE BIT(21)
+#define TACH_ASPEED_FULL_MEASUREMENT BIT(20)
+#define TACH_ASPEED_VALUE_MASK GENMASK(19, 0)
+/**********************************************************
+ * Software setting
+ *********************************************************/
+#define DEFAULT_FAN_MIN_RPM 1000
+#define DEFAULT_FAN_PULSE_PR 2
+/*
+ * Add this value to avoid CPU consuming a lot of resources in waiting rpm
+ * updating. Assume the max rpm of fan is 60000, the fastest period of updating
+ * tach value will be equal to (1000000 * 2 * 60) / (2 * max_rpm) = 1000us.
+ */
+#define DEFAULT_FAN_MAX_RPM 60000
+
+struct aspeed_tach_channel_params {
+ int limited_inverse;
+ u16 threshold;
+ u8 tach_edge;
+ u8 tach_debounce;
+ u8 pulse_pr;
+ u32 min_rpm;
+ u32 max_rpm;
+ u32 divisor;
+ u32 sample_period; /* unit is us */
+ u32 polling_period; /* unit is us */
+};
+
+struct aspeed_tach_data {
+ struct device *dev;
+ struct regmap *regmap;
+ struct clk *clk;
+ struct reset_control *reset;
+ bool tach_present[TACH_ASPEED_NR_TACHS];
+ struct aspeed_tach_channel_params *tach_channel;
+ /* for hwmon */
+ const struct attribute_group *groups[2];
+};
+
+static void aspeed_update_tach_sample_period(struct aspeed_tach_data *priv,
+ u8 fan_tach_ch)
+{
+ u32 tach_period_us;
+ u8 pulse_pr = priv->tach_channel[fan_tach_ch].pulse_pr;
+ u32 min_rpm = priv->tach_channel[fan_tach_ch].min_rpm;
+
+ /*
+ * min(Tach input clock) = (PulsePR * minRPM) / 60
+ * max(Tach input period) = 60 / (PulsePR * minRPM)
+ * Tach sample period > 2 * max(Tach input period) = (2*60) / (PulsePR * minRPM)
+ */
+ tach_period_us = (USEC_PER_SEC * 2 * 60) / (pulse_pr * min_rpm);
+ /* Add the margin (about 1.5) of tach sample period to avoid sample miss */
+ tach_period_us = (tach_period_us * 1500) >> 10;
+ dev_dbg(priv->dev, "tach%d sample period = %dus", fan_tach_ch, tach_period_us);
+ priv->tach_channel[fan_tach_ch].sample_period = tach_period_us;
+}
+
+static void aspeed_update_tach_polling_period(struct aspeed_tach_data *priv,
+ u8 fan_tach_ch)
+{
+ u32 tach_period_us;
+ u8 pulse_pr = priv->tach_channel[fan_tach_ch].pulse_pr;
+ u32 max_rpm = priv->tach_channel[fan_tach_ch].max_rpm;
+
+ tach_period_us = (USEC_PER_SEC * 2 * 60) / (pulse_pr * max_rpm);
+ dev_dbg(priv->dev, "tach%d polling period = %dus", fan_tach_ch, tach_period_us);
+ priv->tach_channel[fan_tach_ch].polling_period = tach_period_us;
+}
+
+static void aspeed_tach_ch_enable(struct aspeed_tach_data *priv, u8 tach_ch,
+ bool enable)
+{
+ if (enable)
+ regmap_set_bits(priv->regmap, TACH_ASPEED_CTRL(tach_ch),
+ TACH_ASPEED_ENABLE);
+ else
+ regmap_clear_bits(priv->regmap, TACH_ASPEED_CTRL(tach_ch),
+ TACH_ASPEED_ENABLE);
+}
+
+static int aspeed_get_fan_tach_ch_rpm(struct aspeed_tach_data *priv,
+ u8 fan_tach_ch)
+{
+ u32 raw_data, tach_div, val;
+ unsigned long clk_source;
+ u64 rpm;
+ int ret;
+
+ /* Restart the Tach channel to guarantee the value is fresh */
+ aspeed_tach_ch_enable(priv, fan_tach_ch, false);
+ aspeed_tach_ch_enable(priv, fan_tach_ch, true);
+ ret = regmap_read_poll_timeout(
+ priv->regmap, TACH_ASPEED_STS(fan_tach_ch), val,
+ (val & TACH_ASPEED_FULL_MEASUREMENT) &&
+ (val & TACH_ASPEED_VALUE_UPDATE),
+ priv->tach_channel[fan_tach_ch].polling_period,
+ priv->tach_channel[fan_tach_ch].sample_period);
+
+ if (ret) {
+ /* return 0 if we didn't get an answer because of timeout*/
+ if (ret == -ETIMEDOUT)
+ return 0;
+ else
+ return ret;
+ }
+
+ raw_data = val & TACH_ASPEED_VALUE_MASK;
+ /*
+ * We need the mode to determine if the raw_data is double (from
+ * counting both edges).
+ */
+ if (priv->tach_channel[fan_tach_ch].tach_edge == BOTH_EDGES)
+ raw_data <<= 1;
+
+ tach_div = raw_data * (priv->tach_channel[fan_tach_ch].divisor) *
+ (priv->tach_channel[fan_tach_ch].pulse_pr);
+
+ clk_source = clk_get_rate(priv->clk);
+ dev_dbg(priv->dev, "clk %ld, raw_data %d , tach_div %d\n", clk_source,
+ raw_data, tach_div);
+
+ if (tach_div == 0)
+ return -EDOM;
+
+ rpm = (u64)clk_source * 60;
+ do_div(rpm, tach_div);
+
+ return rpm;
+}
+
+static ssize_t fan_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
+ int index = sensor_attr->index;
+ int rpm;
+ struct aspeed_tach_data *priv = dev_get_drvdata(dev);
+
+ rpm = aspeed_get_fan_tach_ch_rpm(priv, index);
+ if (rpm < 0)
+ return rpm;
+
+ return sprintf(buf, "%d\n", rpm);
+}
+
+static umode_t fan_dev_is_visible(struct kobject *kobj, struct attribute *a,
+ int index)
+{
+ struct device *dev = container_of(kobj, struct device, kobj);
+ struct aspeed_tach_data *priv = dev_get_drvdata(dev);
+
+ if (!priv->tach_present[index % TACH_ASPEED_NR_TACHS])
+ return 0;
+ return a->mode;
+}
+
+static SENSOR_DEVICE_ATTR_RO(fan1_input, fan, 0);
+static SENSOR_DEVICE_ATTR_RO(fan2_input, fan, 1);
+static SENSOR_DEVICE_ATTR_RO(fan3_input, fan, 2);
+static SENSOR_DEVICE_ATTR_RO(fan4_input, fan, 3);
+static SENSOR_DEVICE_ATTR_RO(fan5_input, fan, 4);
+static SENSOR_DEVICE_ATTR_RO(fan6_input, fan, 5);
+static SENSOR_DEVICE_ATTR_RO(fan7_input, fan, 6);
+static SENSOR_DEVICE_ATTR_RO(fan8_input, fan, 7);
+static SENSOR_DEVICE_ATTR_RO(fan9_input, fan, 8);
+static SENSOR_DEVICE_ATTR_RO(fan10_input, fan, 9);
+static SENSOR_DEVICE_ATTR_RO(fan11_input, fan, 10);
+static SENSOR_DEVICE_ATTR_RO(fan12_input, fan, 11);
+static SENSOR_DEVICE_ATTR_RO(fan13_input, fan, 12);
+static SENSOR_DEVICE_ATTR_RO(fan14_input, fan, 13);
+static SENSOR_DEVICE_ATTR_RO(fan15_input, fan, 14);
+static SENSOR_DEVICE_ATTR_RO(fan16_input, fan, 15);
+
+static ssize_t fan_max_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
+ int index = sensor_attr->index;
+ struct aspeed_tach_data *priv = dev_get_drvdata(dev);
+ u32 max_rpm = priv->tach_channel[index].max_rpm;
+
+ return sprintf(buf, "%d\n", max_rpm);
+}
+
+static ssize_t fan_max_store(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
+ int index = sensor_attr->index;
+ struct aspeed_tach_data *priv = dev_get_drvdata(dev);
+ long max_rpm;
+ int ret;
+
+ ret = kstrtoul(buf, 10, &max_rpm);
+ if (ret < 0)
+ return ret;
+
+ priv->tach_channel[index].max_rpm = max_rpm;
+ aspeed_update_tach_polling_period(priv, index);
+ return count;
+}
+
+static SENSOR_DEVICE_ATTR_RW(fan1_max, fan_max, 0);
+static SENSOR_DEVICE_ATTR_RW(fan2_max, fan_max, 1);
+static SENSOR_DEVICE_ATTR_RW(fan3_max, fan_max, 2);
+static SENSOR_DEVICE_ATTR_RW(fan4_max, fan_max, 3);
+static SENSOR_DEVICE_ATTR_RW(fan5_max, fan_max, 4);
+static SENSOR_DEVICE_ATTR_RW(fan6_max, fan_max, 5);
+static SENSOR_DEVICE_ATTR_RW(fan7_max, fan_max, 6);
+static SENSOR_DEVICE_ATTR_RW(fan8_max, fan_max, 7);
+static SENSOR_DEVICE_ATTR_RW(fan9_max, fan_max, 8);
+static SENSOR_DEVICE_ATTR_RW(fan10_max, fan_max, 9);
+static SENSOR_DEVICE_ATTR_RW(fan11_max, fan_max, 10);
+static SENSOR_DEVICE_ATTR_RW(fan12_max, fan_max, 11);
+static SENSOR_DEVICE_ATTR_RW(fan13_max, fan_max, 12);
+static SENSOR_DEVICE_ATTR_RW(fan14_max, fan_max, 13);
+static SENSOR_DEVICE_ATTR_RW(fan15_max, fan_max, 14);
+static SENSOR_DEVICE_ATTR_RW(fan16_max, fan_max, 15);
+
+static ssize_t fan_min_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
+ int index = sensor_attr->index;
+ struct aspeed_tach_data *priv = dev_get_drvdata(dev);
+ u32 min_rpm = priv->tach_channel[index].min_rpm;
+
+ return sprintf(buf, "%d\n", min_rpm);
+}
+
+static ssize_t fan_min_store(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
+ int index = sensor_attr->index;
+ struct aspeed_tach_data *priv = dev_get_drvdata(dev);
+ long min_rpm;
+ int ret;
+
+ ret = kstrtoul(buf, 10, &min_rpm);
+ if (ret < 0)
+ return ret;
+
+ priv->tach_channel[index].min_rpm = min_rpm;
+ aspeed_update_tach_sample_period(priv, index);
+ return count;
+}
+
+static SENSOR_DEVICE_ATTR_RW(fan1_min, fan_min, 0);
+static SENSOR_DEVICE_ATTR_RW(fan2_min, fan_min, 1);
+static SENSOR_DEVICE_ATTR_RW(fan3_min, fan_min, 2);
+static SENSOR_DEVICE_ATTR_RW(fan4_min, fan_min, 3);
+static SENSOR_DEVICE_ATTR_RW(fan5_min, fan_min, 4);
+static SENSOR_DEVICE_ATTR_RW(fan6_min, fan_min, 5);
+static SENSOR_DEVICE_ATTR_RW(fan7_min, fan_min, 6);
+static SENSOR_DEVICE_ATTR_RW(fan8_min, fan_min, 7);
+static SENSOR_DEVICE_ATTR_RW(fan9_min, fan_min, 8);
+static SENSOR_DEVICE_ATTR_RW(fan10_min, fan_min, 9);
+static SENSOR_DEVICE_ATTR_RW(fan11_min, fan_min, 10);
+static SENSOR_DEVICE_ATTR_RW(fan12_min, fan_min, 11);
+static SENSOR_DEVICE_ATTR_RW(fan13_min, fan_min, 12);
+static SENSOR_DEVICE_ATTR_RW(fan14_min, fan_min, 13);
+static SENSOR_DEVICE_ATTR_RW(fan15_min, fan_min, 14);
+static SENSOR_DEVICE_ATTR_RW(fan16_min, fan_min, 15);
+
+static ssize_t fan_pulse_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
+ int index = sensor_attr->index;
+ struct aspeed_tach_data *priv = dev_get_drvdata(dev);
+ u32 pulse_pr = priv->tach_channel[index].pulse_pr;
+
+ return sprintf(buf, "%d\n", pulse_pr);
+}
+
+static ssize_t fan_pulse_store(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
+ int index = sensor_attr->index;
+ struct aspeed_tach_data *priv = dev_get_drvdata(dev);
+ long pulse_pr;
+ int ret;
+
+ ret = kstrtoul(buf, 10, &pulse_pr);
+ if (ret < 0)
+ return ret;
+
+ priv->tach_channel[index].pulse_pr = pulse_pr;
+ aspeed_update_tach_sample_period(priv, index);
+ return count;
+}
+
+static SENSOR_DEVICE_ATTR_RW(fan1_pulse, fan_pulse, 0);
+static SENSOR_DEVICE_ATTR_RW(fan2_pulse, fan_pulse, 1);
+static SENSOR_DEVICE_ATTR_RW(fan3_pulse, fan_pulse, 2);
+static SENSOR_DEVICE_ATTR_RW(fan4_pulse, fan_pulse, 3);
+static SENSOR_DEVICE_ATTR_RW(fan5_pulse, fan_pulse, 4);
+static SENSOR_DEVICE_ATTR_RW(fan6_pulse, fan_pulse, 5);
+static SENSOR_DEVICE_ATTR_RW(fan7_pulse, fan_pulse, 6);
+static SENSOR_DEVICE_ATTR_RW(fan8_pulse, fan_pulse, 7);
+static SENSOR_DEVICE_ATTR_RW(fan9_pulse, fan_pulse, 8);
+static SENSOR_DEVICE_ATTR_RW(fan10_pulse, fan_pulse, 9);
+static SENSOR_DEVICE_ATTR_RW(fan11_pulse, fan_pulse, 10);
+static SENSOR_DEVICE_ATTR_RW(fan12_pulse, fan_pulse, 11);
+static SENSOR_DEVICE_ATTR_RW(fan13_pulse, fan_pulse, 12);
+static SENSOR_DEVICE_ATTR_RW(fan14_pulse, fan_pulse, 13);
+static SENSOR_DEVICE_ATTR_RW(fan15_pulse, fan_pulse, 14);
+static SENSOR_DEVICE_ATTR_RW(fan16_pulse, fan_pulse, 15);
+
+static ssize_t fan_div_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
+ int index = sensor_attr->index;
+ struct aspeed_tach_data *priv = dev_get_drvdata(dev);
+ u32 divisor, val = priv->tach_channel[index].divisor;
+
+ regmap_read(priv->regmap, TACH_ASPEED_CTRL(index), &val);
+ divisor = FIELD_GET(TACH_ASPEED_CLK_DIV_T_MASK, val);
+ divisor = 1 << (divisor << 1);
+
+ return sprintf(buf, "%d\n", divisor);
+}
+
+static ssize_t fan_div_store(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
+ int index = sensor_attr->index;
+ struct aspeed_tach_data *priv = dev_get_drvdata(dev);
+ long divisor;
+ int ret;
+
+ ret = kstrtoul(buf, 10, &divisor);
+ if (ret < 0)
+ return ret;
+
+ if ((is_power_of_2(divisor) && !(ilog2(divisor) % 2))) {
+ priv->tach_channel[index].divisor = divisor;
+ regmap_write_bits(priv->regmap, TACH_ASPEED_CTRL(index),
+ TACH_ASPEED_CLK_DIV_T_MASK,
+ DIV_TO_REG(priv->tach_channel[index].divisor)
+ << TACH_ASPEED_CLK_DIV_BIT);
+ } else {
+ dev_err(dev,
+ "fan_div value %ld not supported. Only support power of 4\n",
+ divisor);
+ return -EINVAL;
+ }
+
+ return count;
+}
+
+static SENSOR_DEVICE_ATTR_RW(fan1_div, fan_div, 0);
+static SENSOR_DEVICE_ATTR_RW(fan2_div, fan_div, 1);
+static SENSOR_DEVICE_ATTR_RW(fan3_div, fan_div, 2);
+static SENSOR_DEVICE_ATTR_RW(fan4_div, fan_div, 3);
+static SENSOR_DEVICE_ATTR_RW(fan5_div, fan_div, 4);
+static SENSOR_DEVICE_ATTR_RW(fan6_div, fan_div, 5);
+static SENSOR_DEVICE_ATTR_RW(fan7_div, fan_div, 6);
+static SENSOR_DEVICE_ATTR_RW(fan8_div, fan_div, 7);
+static SENSOR_DEVICE_ATTR_RW(fan9_div, fan_div, 8);
+static SENSOR_DEVICE_ATTR_RW(fan10_div, fan_div, 9);
+static SENSOR_DEVICE_ATTR_RW(fan11_div, fan_div, 10);
+static SENSOR_DEVICE_ATTR_RW(fan12_div, fan_div, 11);
+static SENSOR_DEVICE_ATTR_RW(fan13_div, fan_div, 12);
+static SENSOR_DEVICE_ATTR_RW(fan14_div, fan_div, 13);
+static SENSOR_DEVICE_ATTR_RW(fan15_div, fan_div, 14);
+static SENSOR_DEVICE_ATTR_RW(fan16_div, fan_div, 15);
+
+static struct attribute *fan_dev_attrs[] = {
+ &sensor_dev_attr_fan1_input.dev_attr.attr,
+ &sensor_dev_attr_fan2_input.dev_attr.attr,
+ &sensor_dev_attr_fan3_input.dev_attr.attr,
+ &sensor_dev_attr_fan4_input.dev_attr.attr,
+ &sensor_dev_attr_fan5_input.dev_attr.attr,
+ &sensor_dev_attr_fan6_input.dev_attr.attr,
+ &sensor_dev_attr_fan7_input.dev_attr.attr,
+ &sensor_dev_attr_fan8_input.dev_attr.attr,
+ &sensor_dev_attr_fan9_input.dev_attr.attr,
+ &sensor_dev_attr_fan10_input.dev_attr.attr,
+ &sensor_dev_attr_fan11_input.dev_attr.attr,
+ &sensor_dev_attr_fan12_input.dev_attr.attr,
+ &sensor_dev_attr_fan13_input.dev_attr.attr,
+ &sensor_dev_attr_fan14_input.dev_attr.attr,
+ &sensor_dev_attr_fan15_input.dev_attr.attr,
+ &sensor_dev_attr_fan16_input.dev_attr.attr,
+
+ &sensor_dev_attr_fan1_max.dev_attr.attr,
+ &sensor_dev_attr_fan2_max.dev_attr.attr,
+ &sensor_dev_attr_fan3_max.dev_attr.attr,
+ &sensor_dev_attr_fan4_max.dev_attr.attr,
+ &sensor_dev_attr_fan5_max.dev_attr.attr,
+ &sensor_dev_attr_fan6_max.dev_attr.attr,
+ &sensor_dev_attr_fan7_max.dev_attr.attr,
+ &sensor_dev_attr_fan8_max.dev_attr.attr,
+ &sensor_dev_attr_fan9_max.dev_attr.attr,
+ &sensor_dev_attr_fan10_max.dev_attr.attr,
+ &sensor_dev_attr_fan11_max.dev_attr.attr,
+ &sensor_dev_attr_fan12_max.dev_attr.attr,
+ &sensor_dev_attr_fan13_max.dev_attr.attr,
+ &sensor_dev_attr_fan14_max.dev_attr.attr,
+ &sensor_dev_attr_fan15_max.dev_attr.attr,
+ &sensor_dev_attr_fan16_max.dev_attr.attr,
+
+ &sensor_dev_attr_fan1_min.dev_attr.attr,
+ &sensor_dev_attr_fan2_min.dev_attr.attr,
+ &sensor_dev_attr_fan3_min.dev_attr.attr,
+ &sensor_dev_attr_fan4_min.dev_attr.attr,
+ &sensor_dev_attr_fan5_min.dev_attr.attr,
+ &sensor_dev_attr_fan6_min.dev_attr.attr,
+ &sensor_dev_attr_fan7_min.dev_attr.attr,
+ &sensor_dev_attr_fan8_min.dev_attr.attr,
+ &sensor_dev_attr_fan9_min.dev_attr.attr,
+ &sensor_dev_attr_fan10_min.dev_attr.attr,
+ &sensor_dev_attr_fan11_min.dev_attr.attr,
+ &sensor_dev_attr_fan12_min.dev_attr.attr,
+ &sensor_dev_attr_fan13_min.dev_attr.attr,
+ &sensor_dev_attr_fan14_min.dev_attr.attr,
+ &sensor_dev_attr_fan15_min.dev_attr.attr,
+ &sensor_dev_attr_fan16_min.dev_attr.attr,
+
+ &sensor_dev_attr_fan1_div.dev_attr.attr,
+ &sensor_dev_attr_fan2_div.dev_attr.attr,
+ &sensor_dev_attr_fan3_div.dev_attr.attr,
+ &sensor_dev_attr_fan4_div.dev_attr.attr,
+ &sensor_dev_attr_fan5_div.dev_attr.attr,
+ &sensor_dev_attr_fan6_div.dev_attr.attr,
+ &sensor_dev_attr_fan7_div.dev_attr.attr,
+ &sensor_dev_attr_fan8_div.dev_attr.attr,
+ &sensor_dev_attr_fan9_div.dev_attr.attr,
+ &sensor_dev_attr_fan10_div.dev_attr.attr,
+ &sensor_dev_attr_fan11_div.dev_attr.attr,
+ &sensor_dev_attr_fan12_div.dev_attr.attr,
+ &sensor_dev_attr_fan13_div.dev_attr.attr,
+ &sensor_dev_attr_fan14_div.dev_attr.attr,
+ &sensor_dev_attr_fan15_div.dev_attr.attr,
+ &sensor_dev_attr_fan16_div.dev_attr.attr,
+
+ &sensor_dev_attr_fan1_pulse.dev_attr.attr,
+ &sensor_dev_attr_fan2_pulse.dev_attr.attr,
+ &sensor_dev_attr_fan3_pulse.dev_attr.attr,
+ &sensor_dev_attr_fan4_pulse.dev_attr.attr,
+ &sensor_dev_attr_fan5_pulse.dev_attr.attr,
+ &sensor_dev_attr_fan6_pulse.dev_attr.attr,
+ &sensor_dev_attr_fan7_pulse.dev_attr.attr,
+ &sensor_dev_attr_fan8_pulse.dev_attr.attr,
+ &sensor_dev_attr_fan9_pulse.dev_attr.attr,
+ &sensor_dev_attr_fan10_pulse.dev_attr.attr,
+ &sensor_dev_attr_fan11_pulse.dev_attr.attr,
+ &sensor_dev_attr_fan12_pulse.dev_attr.attr,
+ &sensor_dev_attr_fan13_pulse.dev_attr.attr,
+ &sensor_dev_attr_fan14_pulse.dev_attr.attr,
+ &sensor_dev_attr_fan15_pulse.dev_attr.attr,
+ &sensor_dev_attr_fan16_pulse.dev_attr.attr,
+ NULL
+};
+
+static const struct attribute_group fan_dev_group = {
+ .attrs = fan_dev_attrs,
+ .is_visible = fan_dev_is_visible,
+};
+
+static void aspeed_create_fan_tach_channel(struct aspeed_tach_data *priv,
+ u32 tach_ch)
+{
+ priv->tach_present[tach_ch] = true;
+ priv->tach_channel[tach_ch].limited_inverse = 0;
+ regmap_write_bits(priv->regmap, TACH_ASPEED_CTRL(tach_ch),
+ TACH_ASPEED_INVERS_LIMIT,
+ priv->tach_channel[tach_ch].limited_inverse ?
+ TACH_ASPEED_INVERS_LIMIT :
+ 0);
+
+ priv->tach_channel[tach_ch].tach_debounce = DEBOUNCE_3_CLK;
+ regmap_write_bits(priv->regmap, TACH_ASPEED_CTRL(tach_ch),
+ TACH_ASPEED_DEBOUNCE_MASK,
+ priv->tach_channel[tach_ch].tach_debounce
+ << TACH_ASPEED_DEBOUNCE_BIT);
+
+ priv->tach_channel[tach_ch].tach_edge = F2F_EDGES;
+ regmap_write_bits(priv->regmap, TACH_ASPEED_CTRL(tach_ch),
+ TACH_ASPEED_IO_EDGE_MASK,
+ priv->tach_channel[tach_ch].tach_edge
+ << TACH_ASPEED_IO_EDGE_BIT);
+
+ priv->tach_channel[tach_ch].divisor = DEFAULT_TACH_DIV;
+ regmap_write_bits(priv->regmap, TACH_ASPEED_CTRL(tach_ch),
+ TACH_ASPEED_CLK_DIV_T_MASK,
+ DIV_TO_REG(priv->tach_channel[tach_ch].divisor)
+ << TACH_ASPEED_CLK_DIV_BIT);
+
+ priv->tach_channel[tach_ch].threshold = 0;
+ regmap_write_bits(priv->regmap, TACH_ASPEED_CTRL(tach_ch),
+ TACH_ASPEED_THRESHOLD_MASK,
+ priv->tach_channel[tach_ch].threshold);
+
+ priv->tach_channel[tach_ch].pulse_pr = DEFAULT_FAN_PULSE_PR;
+ priv->tach_channel[tach_ch].min_rpm = DEFAULT_FAN_MIN_RPM;
+ aspeed_update_tach_sample_period(priv, tach_ch);
+
+ priv->tach_channel[tach_ch].max_rpm = DEFAULT_FAN_MAX_RPM;
+ aspeed_update_tach_polling_period(priv, tach_ch);
+
+ aspeed_tach_ch_enable(priv, tach_ch, true);
+}
+
+static int aspeed_tach_create_fan(struct device *dev, struct device_node *child,
+ struct aspeed_tach_data *priv)
+{
+ u32 tach_channel;
+ int ret;
+
+ ret = of_property_read_u32(child, "reg", &tach_channel);
+ if (ret)
+ return ret;
+
+ aspeed_create_fan_tach_channel(priv, tach_channel);
+
+ return 0;
+}
+
+static int aspeed_tach_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np, *child;
+ struct aspeed_tach_data *priv;
+ struct device *hwmon;
+ struct platform_device *parent_dev;
+ int ret;
+
+ np = dev->parent->of_node;
+ if (!of_device_is_compatible(np, "aspeed,ast2600-pwm-tach"))
+ return dev_err_probe(dev, -ENODEV,
+ "Unsupported tach device binding\n");
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+ priv->dev = &pdev->dev;
+ priv->tach_channel =
+ devm_kzalloc(dev,
+ TACH_ASPEED_NR_TACHS * sizeof(*priv->tach_channel),
+ GFP_KERNEL);
+
+ priv->regmap = syscon_node_to_regmap(np);
+ if (IS_ERR(priv->regmap)) {
+ dev_err(priv->dev, "Couldn't get regmap\n");
+ return -ENODEV;
+ }
+ parent_dev = of_find_device_by_node(np);
+ priv->clk = devm_clk_get(&parent_dev->dev, 0);
+ if (IS_ERR(priv->clk))
+ return dev_err_probe(dev, PTR_ERR(priv->clk),
+ "Couldn't get clock\n");
+
+ priv->reset = devm_reset_control_get_shared(&parent_dev->dev, NULL);
+ if (IS_ERR(priv->reset))
+ return dev_err_probe(dev, PTR_ERR(priv->reset),
+ "Couldn't get reset control\n");
+
+ ret = clk_prepare_enable(priv->clk);
+ if (ret)
+ return dev_err_probe(dev, ret, "Couldn't enable clock\n");
+
+ ret = reset_control_deassert(priv->reset);
+ if (ret) {
+ dev_err_probe(dev, ret, "Couldn't deassert reset control\n");
+ goto err_disable_clk;
+ }
+ for_each_child_of_node(dev->of_node, child) {
+ ret = aspeed_tach_create_fan(dev, child, priv);
+ if (ret) {
+ of_node_put(child);
+ goto err_assert_reset;
+ }
+ }
+
+ priv->groups[0] = &fan_dev_group;
+ priv->groups[1] = NULL;
+ hwmon = devm_hwmon_device_register_with_groups(dev, "aspeed_tach", priv,
+ priv->groups);
+ ret = PTR_ERR_OR_ZERO(hwmon);
+ if (ret) {
+ dev_err_probe(dev, ret, "Failed to register hwmon device\n");
+ goto err_assert_reset;
+ }
+ platform_set_drvdata(pdev, priv);
+ return 0;
+err_assert_reset:
+ reset_control_assert(priv->reset);
+err_disable_clk:
+ clk_disable_unprepare(priv->clk);
+ return ret;
+}
+
+static int aspeed_tach_remove(struct platform_device *pdev)
+{
+ struct aspeed_tach_data *priv = platform_get_drvdata(pdev);
+
+ reset_control_assert(priv->reset);
+ clk_disable_unprepare(priv->clk);
+
+ return 0;
+}
+
+static const struct of_device_id of_stach_match_table[] = {
+ {
+ .compatible = "aspeed,ast2600-tach",
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, of_stach_match_table);
+
+static struct platform_driver aspeed_tach_driver = {
+ .probe = aspeed_tach_probe,
+ .remove = aspeed_tach_remove,
+ .driver = {
+ .name = "aspeed_tach",
+ .of_match_table = of_stach_match_table,
+ },
+};
+
+module_platform_driver(aspeed_tach_driver);
+
+MODULE_AUTHOR("Billy Tsai <[email protected]>");
+MODULE_DESCRIPTION("Aspeed ast2600 TACH device driver");
+MODULE_LICENSE("GPL v2");
+
--
2.25.1
This patch add the support of PWM controller which can be found at aspeed
ast2600 soc. The pwm supoorts up to 16 channels and it's part function
of multi-function device "pwm-tach controller".
Signed-off-by: Billy Tsai <[email protected]>
Reviewed-by: Uwe Kleine-König <[email protected]>
---
drivers/pwm/Kconfig | 10 +
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-aspeed-ast2600.c | 325 +++++++++++++++++++++++++++++++
3 files changed, 336 insertions(+)
create mode 100644 drivers/pwm/pwm-aspeed-ast2600.c
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index aa29841bbb79..3313f074f15e 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -51,6 +51,16 @@ config PWM_AB8500
To compile this driver as a module, choose M here: the module
will be called pwm-ab8500.
+config PWM_ASPEED_AST2600
+ tristate "Aspeed ast2600 PWM support"
+ depends on ARCH_ASPEED || COMPILE_TEST
+ depends on HAVE_CLK && HAS_IOMEM
+ help
+ This driver provides support for Aspeed ast2600 PWM controllers.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-aspeed-ast2600.
+
config PWM_ATMEL
tristate "Atmel PWM support"
depends on ARCH_AT91 || COMPILE_TEST
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 708840b7fba8..6be0c67bf08a 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -2,6 +2,7 @@
obj-$(CONFIG_PWM) += core.o
obj-$(CONFIG_PWM_SYSFS) += sysfs.o
obj-$(CONFIG_PWM_AB8500) += pwm-ab8500.o
+obj-$(CONFIG_PWM_ASPEED_AST2600) += pwm-aspeed-ast2600.o
obj-$(CONFIG_PWM_ATMEL) += pwm-atmel.o
obj-$(CONFIG_PWM_ATMEL_HLCDC_PWM) += pwm-atmel-hlcdc.o
obj-$(CONFIG_PWM_ATMEL_TCB) += pwm-atmel-tcb.o
diff --git a/drivers/pwm/pwm-aspeed-ast2600.c b/drivers/pwm/pwm-aspeed-ast2600.c
new file mode 100644
index 000000000000..bf54eeb70372
--- /dev/null
+++ b/drivers/pwm/pwm-aspeed-ast2600.c
@@ -0,0 +1,325 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2021 Aspeed Technology Inc.
+ *
+ * PWM controller driver for Aspeed ast2600 SoCs.
+ * This drivers doesn't support earlier version of the IP.
+ *
+ * The hardware operates in time quantities of length
+ * Q := (DIV_L + 1) << DIV_H / input-clk
+ * The length of a PWM period is (DUTY_CYCLE_PERIOD + 1) * Q.
+ * The maximal value for DUTY_CYCLE_PERIOD is used here to provide
+ * a fine grained selection for the duty cycle.
+ *
+ * This driver uses DUTY_CYCLE_RISING_POINT = 0, so from the start of a
+ * period the output is active until DUTY_CYCLE_FALLING_POINT * Q. Note
+ * that if DUTY_CYCLE_RISING_POINT = DUTY_CYCLE_FALLING_POINT the output is
+ * always active.
+ *
+ * Register usage:
+ * PIN_ENABLE: When it is unset the pwm controller will emit inactive level to the external.
+ * Use to determine whether the PWM channel is enabled or disabled
+ * CLK_ENABLE: When it is unset the pwm controller will assert the duty counter reset and
+ * emit inactive level to the PIN_ENABLE mux after that the driver can still change the pwm period
+ * and duty and the value will apply when CLK_ENABLE be set again.
+ * Use to determine whether duty_cycle bigger than 0.
+ * PWM_ASPEED_CTRL_INVERSE: When it is toggled the output value will inverse immediately.
+ * PWM_ASPEED_DUTY_CYCLE_FALLING_POINT/PWM_ASPEED_DUTY_CYCLE_RISING_POINT: When these two
+ * values are equal it means the duty cycle = 100%.
+ *
+ * The glitch may generate at:
+ * - Enabled changing when the duty_cycle bigger than 0% and less than 100%.
+ * - Polarity changing when the duty_cycle bigger than 0% and less than 100%.
+ *
+ * Limitations:
+ * - When changing both duty cycle and period, we cannot prevent in
+ * software that the output might produce a period with mixed
+ * settings.
+ * - Disabling the PWM doesn't complete the current period.
+ *
+ * Improvements:
+ * - When only changing one of duty cycle or period, our pwm controller will not
+ * generate the glitch, the configure will change at next cycle of pwm.
+ * This improvement can disable/enable through PWM_ASPEED_CTRL_DUTY_SYNC_DISABLE.
+ */
+
+#include <linux/clk.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/sysfs.h>
+#include <linux/reset.h>
+#include <linux/regmap.h>
+#include <linux/bitfield.h>
+#include <linux/slab.h>
+#include <linux/pwm.h>
+#include <linux/math64.h>
+
+/* The channel number of Aspeed pwm controller */
+#define PWM_ASPEED_NR_PWMS 16
+
+/* PWM Control Register */
+#define PWM_ASPEED_CTRL(ch) ((ch) * 0x10 + 0x00)
+#define PWM_ASPEED_CTRL_LOAD_SEL_RISING_AS_WDT BIT(19)
+#define PWM_ASPEED_CTRL_DUTY_LOAD_AS_WDT_ENABLE BIT(18)
+#define PWM_ASPEED_CTRL_DUTY_SYNC_DISABLE BIT(17)
+#define PWM_ASPEED_CTRL_CLK_ENABLE BIT(16)
+#define PWM_ASPEED_CTRL_LEVEL_OUTPUT BIT(15)
+#define PWM_ASPEED_CTRL_INVERSE BIT(14)
+#define PWM_ASPEED_CTRL_OPEN_DRAIN_ENABLE BIT(13)
+#define PWM_ASPEED_CTRL_PIN_ENABLE BIT(12)
+#define PWM_ASPEED_CTRL_CLK_DIV_H GENMASK(11, 8)
+#define PWM_ASPEED_CTRL_CLK_DIV_L GENMASK(7, 0)
+
+/* PWM Duty Cycle Register */
+#define PWM_ASPEED_DUTY_CYCLE(ch) ((ch) * 0x10 + 0x04)
+#define PWM_ASPEED_DUTY_CYCLE_PERIOD GENMASK(31, 24)
+#define PWM_ASPEED_DUTY_CYCLE_POINT_AS_WDT GENMASK(23, 16)
+#define PWM_ASPEED_DUTY_CYCLE_FALLING_POINT GENMASK(15, 8)
+#define PWM_ASPEED_DUTY_CYCLE_RISING_POINT GENMASK(7, 0)
+
+/* PWM fixed value */
+#define PWM_ASPEED_FIXED_PERIOD FIELD_MAX(PWM_ASPEED_DUTY_CYCLE_PERIOD)
+
+struct aspeed_pwm_data {
+ struct pwm_chip chip;
+ struct clk *clk;
+ struct regmap *regmap;
+ struct reset_control *reset;
+};
+
+static inline struct aspeed_pwm_data *
+aspeed_pwm_chip_to_data(struct pwm_chip *chip)
+{
+ return container_of(chip, struct aspeed_pwm_data, chip);
+}
+
+static void aspeed_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
+ struct pwm_state *state)
+{
+ struct device *dev = chip->dev;
+ struct aspeed_pwm_data *priv = aspeed_pwm_chip_to_data(chip);
+ u32 hwpwm = pwm->hwpwm;
+ bool polarity, pin_en, clk_en;
+ u32 duty_pt, val;
+ unsigned long rate;
+ u64 div_h, div_l, duty_cycle_period, dividend;
+
+ regmap_read(priv->regmap, PWM_ASPEED_CTRL(hwpwm), &val);
+ polarity = FIELD_GET(PWM_ASPEED_CTRL_INVERSE, val);
+ pin_en = FIELD_GET(PWM_ASPEED_CTRL_PIN_ENABLE, val);
+ clk_en = FIELD_GET(PWM_ASPEED_CTRL_CLK_ENABLE, val);
+ div_h = FIELD_GET(PWM_ASPEED_CTRL_CLK_DIV_H, val);
+ div_l = FIELD_GET(PWM_ASPEED_CTRL_CLK_DIV_L, val);
+ regmap_read(priv->regmap, PWM_ASPEED_DUTY_CYCLE(hwpwm), &val);
+ duty_pt = FIELD_GET(PWM_ASPEED_DUTY_CYCLE_FALLING_POINT, val);
+ duty_cycle_period = FIELD_GET(PWM_ASPEED_DUTY_CYCLE_PERIOD, val);
+
+ rate = clk_get_rate(priv->clk);
+
+ /*
+ * This multiplication doesn't overflow, the upper bound is
+ * 1000000000 * 256 * 256 << 15 = 0x1dcd650000000000
+ */
+ dividend = (u64)NSEC_PER_SEC * (div_l + 1) * (duty_cycle_period + 1)
+ << div_h;
+ state->period = DIV_ROUND_UP_ULL(dividend, rate);
+
+ if (clk_en && duty_pt) {
+ dividend = (u64)NSEC_PER_SEC * (div_l + 1) * duty_pt
+ << div_h;
+ state->duty_cycle = DIV_ROUND_UP_ULL(dividend, rate);
+ } else {
+ state->duty_cycle = clk_en ? state->period : 0;
+ }
+ state->polarity = polarity ? PWM_POLARITY_INVERSED : PWM_POLARITY_NORMAL;
+ state->enabled = pin_en;
+ dev_dbg(dev, "get period: %lldns, duty_cycle: %lldns", state->period,
+ state->duty_cycle);
+}
+
+static int aspeed_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+ const struct pwm_state *state)
+{
+ struct device *dev = chip->dev;
+ struct aspeed_pwm_data *priv = aspeed_pwm_chip_to_data(chip);
+ u32 hwpwm = pwm->hwpwm, duty_pt;
+ unsigned long rate;
+ u64 div_h, div_l, divisor, expect_period;
+ bool clk_en;
+
+ rate = clk_get_rate(priv->clk);
+ expect_period = min(div64_u64(ULLONG_MAX, (u64)rate), state->period);
+ dev_dbg(dev, "expect period: %lldns, duty_cycle: %lldns", expect_period,
+ state->duty_cycle);
+ /*
+ * Pick the smallest value for div_h so that div_l can be the biggest
+ * which results in a finer resolution near the target period value.
+ */
+ divisor = (u64)NSEC_PER_SEC * (PWM_ASPEED_FIXED_PERIOD + 1) *
+ (FIELD_MAX(PWM_ASPEED_CTRL_CLK_DIV_L) + 1);
+ div_h = order_base_2(DIV64_U64_ROUND_UP(rate * expect_period, divisor));
+ if (div_h > 0xf)
+ div_h = 0xf;
+
+ divisor = ((u64)NSEC_PER_SEC * (PWM_ASPEED_FIXED_PERIOD + 1)) << div_h;
+ div_l = div64_u64(rate * expect_period, divisor);
+
+ if (div_l == 0)
+ return -ERANGE;
+
+ div_l -= 1;
+
+ if (div_l > 255)
+ div_l = 255;
+
+ dev_dbg(dev, "clk source: %ld div_h %lld, div_l : %lld\n", rate, div_h,
+ div_l);
+ /* duty_pt = duty_cycle * (PERIOD + 1) / period */
+ duty_pt = div64_u64(state->duty_cycle * rate,
+ (u64)NSEC_PER_SEC * (div_l + 1) << div_h);
+ dev_dbg(dev, "duty_cycle = %lld, duty_pt = %d\n", state->duty_cycle,
+ duty_pt);
+
+ /*
+ * Fixed DUTY_CYCLE_PERIOD to its max value to get a
+ * fine-grained resolution for duty_cycle at the expense of a
+ * coarser period resolution.
+ */
+ regmap_update_bits(priv->regmap, PWM_ASPEED_DUTY_CYCLE(hwpwm),
+ PWM_ASPEED_DUTY_CYCLE_PERIOD,
+ FIELD_PREP(PWM_ASPEED_DUTY_CYCLE_PERIOD,
+ PWM_ASPEED_FIXED_PERIOD));
+ if (duty_pt == 0) {
+ /* emit inactive level and assert the duty counter reset */
+ clk_en = 0;
+ } else {
+ clk_en = 1;
+ if (duty_pt >= (PWM_ASPEED_FIXED_PERIOD + 1))
+ duty_pt = 0;
+ regmap_update_bits(
+ priv->regmap, PWM_ASPEED_DUTY_CYCLE(hwpwm),
+ PWM_ASPEED_DUTY_CYCLE_RISING_POINT |
+ PWM_ASPEED_DUTY_CYCLE_FALLING_POINT,
+ FIELD_PREP(PWM_ASPEED_DUTY_CYCLE_FALLING_POINT,
+ duty_pt));
+ }
+
+ regmap_update_bits(
+ priv->regmap, PWM_ASPEED_CTRL(hwpwm),
+ PWM_ASPEED_CTRL_CLK_DIV_H | PWM_ASPEED_CTRL_CLK_DIV_L |
+ PWM_ASPEED_CTRL_PIN_ENABLE |
+ PWM_ASPEED_CTRL_CLK_ENABLE | PWM_ASPEED_CTRL_INVERSE,
+ FIELD_PREP(PWM_ASPEED_CTRL_CLK_DIV_H, div_h) |
+ FIELD_PREP(PWM_ASPEED_CTRL_CLK_DIV_L, div_l) |
+ FIELD_PREP(PWM_ASPEED_CTRL_PIN_ENABLE, state->enabled) |
+ FIELD_PREP(PWM_ASPEED_CTRL_CLK_ENABLE, clk_en) |
+ FIELD_PREP(PWM_ASPEED_CTRL_INVERSE, state->polarity));
+ return 0;
+}
+
+static const struct pwm_ops aspeed_pwm_ops = {
+ .apply = aspeed_pwm_apply,
+ .get_state = aspeed_pwm_get_state,
+ .owner = THIS_MODULE,
+};
+
+static int aspeed_pwm_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ int ret;
+ struct aspeed_pwm_data *priv;
+ struct device_node *np;
+ struct platform_device *parent_dev;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ np = pdev->dev.parent->of_node;
+ if (!of_device_is_compatible(np, "aspeed,ast2600-pwm-tach"))
+ return dev_err_probe(dev, -ENODEV,
+ "Unsupported pwm device binding\n");
+
+ priv->regmap = syscon_node_to_regmap(np);
+ if (IS_ERR(priv->regmap))
+ return dev_err_probe(dev, PTR_ERR(priv->regmap),
+ "Couldn't get regmap\n");
+
+ parent_dev = of_find_device_by_node(np);
+ priv->clk = devm_clk_get(&parent_dev->dev, 0);
+ if (IS_ERR(priv->clk))
+ return dev_err_probe(dev, PTR_ERR(priv->clk),
+ "Couldn't get clock\n");
+
+ priv->reset = devm_reset_control_get_shared(&parent_dev->dev, NULL);
+ if (IS_ERR(priv->reset))
+ return dev_err_probe(dev, PTR_ERR(priv->reset),
+ "Couldn't get reset control\n");
+
+ ret = clk_prepare_enable(priv->clk);
+ if (ret)
+ return dev_err_probe(dev, ret, "Couldn't enable clock\n");
+
+ ret = reset_control_deassert(priv->reset);
+ if (ret) {
+ dev_err_probe(dev, ret, "Couldn't deassert reset control\n");
+ goto err_disable_clk;
+ }
+
+ priv->chip.dev = dev;
+ priv->chip.ops = &aspeed_pwm_ops;
+ priv->chip.npwm = PWM_ASPEED_NR_PWMS;
+
+ ret = pwmchip_add(&priv->chip);
+ if (ret < 0) {
+ dev_err_probe(dev, ret, "Failed to add PWM chip\n");
+ goto err_assert_reset;
+ }
+ dev_set_drvdata(dev, priv);
+ return 0;
+err_assert_reset:
+ reset_control_assert(priv->reset);
+err_disable_clk:
+ clk_disable_unprepare(priv->clk);
+ return ret;
+}
+
+static int aspeed_pwm_remove(struct platform_device *dev)
+{
+ struct aspeed_pwm_data *priv = platform_get_drvdata(dev);
+
+ pwmchip_remove(&priv->chip);
+ reset_control_assert(priv->reset);
+ clk_disable_unprepare(priv->clk);
+
+ return 0;
+}
+
+static const struct of_device_id of_pwm_match_table[] = {
+ {
+ .compatible = "aspeed,ast2600-pwm",
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, of_pwm_match_table);
+
+static struct platform_driver aspeed_pwm_driver = {
+ .probe = aspeed_pwm_probe,
+ .remove = aspeed_pwm_remove,
+ .driver = {
+ .name = "aspeed-pwm",
+ .of_match_table = of_pwm_match_table,
+ },
+};
+
+module_platform_driver(aspeed_pwm_driver);
+
+MODULE_AUTHOR("Billy Tsai <[email protected]>");
+MODULE_DESCRIPTION("Aspeed ast2600 PWM device driver");
+MODULE_LICENSE("GPL v2");
--
2.25.1
On Mon, Oct 31, 2022 at 06:38:08PM +0800, Billy Tsai wrote:
> This patch add the support of Tachometer which can use to monitor the
> frequency of the input. The tach supports up to 16 channels and it's part
> function of multi-function device "pwm-tach controller".
>
> Signed-off-by: Billy Tsai <[email protected]>
> ---
> drivers/hwmon/Kconfig | 9 +
> drivers/hwmon/Makefile | 1 +
> drivers/hwmon/tach-aspeed-ast2600.c | 692 ++++++++++++++++++++++++++++
Please also provide Documentation/hwmon/tach-aspeed-ast2600.rst.
[ ... ]
> + hwmon = devm_hwmon_device_register_with_groups(dev, "aspeed_tach", priv,
> + priv->groups);
Please use the new hwmon api (devm_hwmon_device_register_with_info).
> + ret = PTR_ERR_OR_ZERO(hwmon);
> + if (ret) {
> + dev_err_probe(dev, ret, "Failed to register hwmon device\n");
> + goto err_assert_reset;
> + }
> + platform_set_drvdata(pdev, priv);
> + return 0;
> +err_assert_reset:
> + reset_control_assert(priv->reset);
> +err_disable_clk:
> + clk_disable_unprepare(priv->clk);
You should be able to use devm_clk_get_enabled() to handle
the clock. If reset handling has to come first, you could use
devm_add_action_or_reset() for it. This way you would
not need the remove function, and error cleanup would
be much simplified.
Thanks,
Guenter
> + return ret;
> +}
> +
> +static int aspeed_tach_remove(struct platform_device *pdev)
> +{
> + struct aspeed_tach_data *priv = platform_get_drvdata(pdev);
> +
> + reset_control_assert(priv->reset);
> + clk_disable_unprepare(priv->clk);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id of_stach_match_table[] = {
> + {
> + .compatible = "aspeed,ast2600-tach",
> + },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, of_stach_match_table);
> +
> +static struct platform_driver aspeed_tach_driver = {
> + .probe = aspeed_tach_probe,
> + .remove = aspeed_tach_remove,
> + .driver = {
> + .name = "aspeed_tach",
> + .of_match_table = of_stach_match_table,
> + },
> +};
> +
> +module_platform_driver(aspeed_tach_driver);
> +
> +MODULE_AUTHOR("Billy Tsai <[email protected]>");
> +MODULE_DESCRIPTION("Aspeed ast2600 TACH device driver");
> +MODULE_LICENSE("GPL v2");
> +
> --
> 2.25.1
>
Hi Billy,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on groeck-staging/hwmon-next]
[also build test WARNING on thierry-reding-pwm/for-next lee-mfd/for-mfd-next robh/for-next linus/master v6.1-rc3 next-20221101]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Billy-Tsai/Support-pwm-tach-driver-for-aspeed-ast26xx/20221031-183813
base: https://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging.git hwmon-next
patch link: https://lore.kernel.org/r/20221031103809.20225-3-billy_tsai%40aspeedtech.com
patch subject: [PATCH 2/3] pwm: Add Aspeed ast2600 PWM support
config: arm64-randconfig-s053-20221101
compiler: aarch64-linux-gcc (GCC) 12.1.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# apt-get install sparse
# sparse version: v0.6.4-39-gce1a6720-dirty
# https://github.com/intel-lab-lkp/linux/commit/1e73d9a570e9276911d41cce20e4dcdb0bcdc4d6
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Billy-Tsai/Support-pwm-tach-driver-for-aspeed-ast26xx/20221031-183813
git checkout 1e73d9a570e9276911d41cce20e4dcdb0bcdc4d6
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' O=build_dir ARCH=arm64 SHELL=/bin/bash drivers/perf/ drivers/pwm/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <[email protected]>
sparse warnings: (new ones prefixed by >>)
>> drivers/pwm/pwm-aspeed-ast2600.c:255:52: sparse: sparse: Using plain integer as NULL pointer
vim +255 drivers/pwm/pwm-aspeed-ast2600.c
231
232 static int aspeed_pwm_probe(struct platform_device *pdev)
233 {
234 struct device *dev = &pdev->dev;
235 int ret;
236 struct aspeed_pwm_data *priv;
237 struct device_node *np;
238 struct platform_device *parent_dev;
239
240 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
241 if (!priv)
242 return -ENOMEM;
243
244 np = pdev->dev.parent->of_node;
245 if (!of_device_is_compatible(np, "aspeed,ast2600-pwm-tach"))
246 return dev_err_probe(dev, -ENODEV,
247 "Unsupported pwm device binding\n");
248
249 priv->regmap = syscon_node_to_regmap(np);
250 if (IS_ERR(priv->regmap))
251 return dev_err_probe(dev, PTR_ERR(priv->regmap),
252 "Couldn't get regmap\n");
253
254 parent_dev = of_find_device_by_node(np);
> 255 priv->clk = devm_clk_get(&parent_dev->dev, 0);
256 if (IS_ERR(priv->clk))
257 return dev_err_probe(dev, PTR_ERR(priv->clk),
258 "Couldn't get clock\n");
259
260 priv->reset = devm_reset_control_get_shared(&parent_dev->dev, NULL);
261 if (IS_ERR(priv->reset))
262 return dev_err_probe(dev, PTR_ERR(priv->reset),
263 "Couldn't get reset control\n");
264
265 ret = clk_prepare_enable(priv->clk);
266 if (ret)
267 return dev_err_probe(dev, ret, "Couldn't enable clock\n");
268
269 ret = reset_control_deassert(priv->reset);
270 if (ret) {
271 dev_err_probe(dev, ret, "Couldn't deassert reset control\n");
272 goto err_disable_clk;
273 }
274
275 priv->chip.dev = dev;
276 priv->chip.ops = &aspeed_pwm_ops;
277 priv->chip.npwm = PWM_ASPEED_NR_PWMS;
278
279 ret = pwmchip_add(&priv->chip);
280 if (ret < 0) {
281 dev_err_probe(dev, ret, "Failed to add PWM chip\n");
282 goto err_assert_reset;
283 }
284 dev_set_drvdata(dev, priv);
285 return 0;
286 err_assert_reset:
287 reset_control_assert(priv->reset);
288 err_disable_clk:
289 clk_disable_unprepare(priv->clk);
290 return ret;
291 }
292
--
0-DAY CI Kernel Test Service
https://01.org/lkp
Hi Billy,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on groeck-staging/hwmon-next]
[also build test WARNING on thierry-reding-pwm/for-next lee-mfd/for-mfd-next robh/for-next linus/master v6.1-rc3 next-20221101]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Billy-Tsai/Support-pwm-tach-driver-for-aspeed-ast26xx/20221031-183813
base: https://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging.git hwmon-next
patch link: https://lore.kernel.org/r/20221031103809.20225-4-billy_tsai%40aspeedtech.com
patch subject: [PATCH 3/3] hwmon: Add Aspeed ast2600 TACH support
config: sparc-randconfig-s052-20221101
compiler: sparc64-linux-gcc (GCC) 12.1.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# apt-get install sparse
# sparse version: v0.6.4-39-gce1a6720-dirty
# https://github.com/intel-lab-lkp/linux/commit/34cbef9d62b8b6b352437c2ccaa6467de6524889
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Billy-Tsai/Support-pwm-tach-driver-for-aspeed-ast26xx/20221031-183813
git checkout 34cbef9d62b8b6b352437c2ccaa6467de6524889
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' O=build_dir ARCH=sparc SHELL=/bin/bash drivers/hwmon/ drivers/media/i2c/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <[email protected]>
sparse warnings: (new ones prefixed by >>)
>> drivers/hwmon/tach-aspeed-ast2600.c:615:52: sparse: sparse: Using plain integer as NULL pointer
vim +615 drivers/hwmon/tach-aspeed-ast2600.c
585
586 static int aspeed_tach_probe(struct platform_device *pdev)
587 {
588 struct device *dev = &pdev->dev;
589 struct device_node *np, *child;
590 struct aspeed_tach_data *priv;
591 struct device *hwmon;
592 struct platform_device *parent_dev;
593 int ret;
594
595 np = dev->parent->of_node;
596 if (!of_device_is_compatible(np, "aspeed,ast2600-pwm-tach"))
597 return dev_err_probe(dev, -ENODEV,
598 "Unsupported tach device binding\n");
599
600 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
601 if (!priv)
602 return -ENOMEM;
603 priv->dev = &pdev->dev;
604 priv->tach_channel =
605 devm_kzalloc(dev,
606 TACH_ASPEED_NR_TACHS * sizeof(*priv->tach_channel),
607 GFP_KERNEL);
608
609 priv->regmap = syscon_node_to_regmap(np);
610 if (IS_ERR(priv->regmap)) {
611 dev_err(priv->dev, "Couldn't get regmap\n");
612 return -ENODEV;
613 }
614 parent_dev = of_find_device_by_node(np);
> 615 priv->clk = devm_clk_get(&parent_dev->dev, 0);
616 if (IS_ERR(priv->clk))
617 return dev_err_probe(dev, PTR_ERR(priv->clk),
618 "Couldn't get clock\n");
619
620 priv->reset = devm_reset_control_get_shared(&parent_dev->dev, NULL);
621 if (IS_ERR(priv->reset))
622 return dev_err_probe(dev, PTR_ERR(priv->reset),
623 "Couldn't get reset control\n");
624
625 ret = clk_prepare_enable(priv->clk);
626 if (ret)
627 return dev_err_probe(dev, ret, "Couldn't enable clock\n");
628
629 ret = reset_control_deassert(priv->reset);
630 if (ret) {
631 dev_err_probe(dev, ret, "Couldn't deassert reset control\n");
632 goto err_disable_clk;
633 }
634 for_each_child_of_node(dev->of_node, child) {
635 ret = aspeed_tach_create_fan(dev, child, priv);
636 if (ret) {
637 of_node_put(child);
638 goto err_assert_reset;
639 }
640 }
641
642 priv->groups[0] = &fan_dev_group;
643 priv->groups[1] = NULL;
644 hwmon = devm_hwmon_device_register_with_groups(dev, "aspeed_tach", priv,
645 priv->groups);
646 ret = PTR_ERR_OR_ZERO(hwmon);
647 if (ret) {
648 dev_err_probe(dev, ret, "Failed to register hwmon device\n");
649 goto err_assert_reset;
650 }
651 platform_set_drvdata(pdev, priv);
652 return 0;
653 err_assert_reset:
654 reset_control_assert(priv->reset);
655 err_disable_clk:
656 clk_disable_unprepare(priv->clk);
657 return ret;
658 }
659
--
0-DAY CI Kernel Test Service
https://01.org/lkp