Hello again everyone!
This series enables the VTM nodes for all of Texas Instrument's K3 SoCs
Most of this series updates the k3_j72xx_bandgap driver to conditionally
map an eFuse region used by the j721e to work around an issue in its VTM
implementation and allows us to save the SPARE_FUSE region on other SoCs
We can then update the device tree bindings for the driver and finally
define the VTM nodes for each device
Thanks for reviewing again
~Bryan
****
v2 -> v3 changes[0]:
- removed a errant devm_iounmap() I introduced between patches in v2
- collected tags
v1 -> v2 changes[1]:
- when removing 'fuse_base' from the 'k3_j72xx_bandgap' structure, I
forgot to pass 'fuse_base' to get_efuse_values()
- removed the descriptions to the generic 'power-domains' property
- incorporated Krzysztof's suggestions to the binding description
- refactored binding to use allOf: if: {min,max}Items over what I was
doing :) Thanks Krzysztof
[0] https://lore.kernel.org/lkml/[email protected]/
[1] https://lore.kernel.org/lkml/[email protected]/
Bryan Brattlof (11):
thermal: k3_j72xx_bandgap: simplify k3_thermal_get_temp() function
thermal: k3_j72xx_bandgap: use bool for i2128 erratum flag
thermal: k3_j72xx_bandgap: remove fuse_base from structure
thermal: k3_j72xx_bandgap: map fuse_base only for erratum workaround
dt-bindings: thermal: k3-j72xx: elaborate on binding description
dt-bindings: thermal: k3-j72xx: conditionally require efuse reg range
arm64: dts: ti: k3-am64-main: add VTM node
arm64: dts: ti: k3-am62-wakeup: add VTM node
arm64: dts: ti: k3-j721e-mcu-wakeup: add VTM node
arm64: dts: ti: k3-j721s2-mcu-wakeup: add VTM node
arm64: dts: ti: k3-j7200-mcu-wakeup: add VTM node
.../bindings/thermal/ti,j72xx-thermal.yaml | 35 +++++-
arch/arm64/boot/dts/ti/k3-am62-thermal.dtsi | 33 ++++++
arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi | 8 ++
arch/arm64/boot/dts/ti/k3-am62.dtsi | 7 +-
arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 8 ++
arch/arm64/boot/dts/ti/k3-am64-thermal.dtsi | 33 ++++++
arch/arm64/boot/dts/ti/k3-am64.dtsi | 4 +
.../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 8 ++
arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi | 47 ++++++++
arch/arm64/boot/dts/ti/k3-j7200.dtsi | 3 +
.../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 9 ++
arch/arm64/boot/dts/ti/k3-j721e-thermal.dtsi | 75 +++++++++++++
arch/arm64/boot/dts/ti/k3-j721e.dtsi | 3 +
.../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 8 ++
arch/arm64/boot/dts/ti/k3-j721s2-thermal.dtsi | 103 ++++++++++++++++++
arch/arm64/boot/dts/ti/k3-j721s2.dtsi | 3 +
drivers/thermal/k3_j72xx_bandgap.c | 67 ++++++------
17 files changed, 420 insertions(+), 34 deletions(-)
create mode 100644 arch/arm64/boot/dts/ti/k3-am62-thermal.dtsi
create mode 100644 arch/arm64/boot/dts/ti/k3-am64-thermal.dtsi
create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi
create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-thermal.dtsi
create mode 100644 arch/arm64/boot/dts/ti/k3-j721s2-thermal.dtsi
--
2.38.1
The am62x supports a single Voltage and Thermal Management (VTM) module
located in the wakeup domain with two associated temperature monitors
located in hot spots of the die.
Signed-off-by: Bryan Brattlof <[email protected]>
---
arch/arm64/boot/dts/ti/k3-am62-thermal.dtsi | 33 +++++++++++++++++++++
arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi | 8 +++++
arch/arm64/boot/dts/ti/k3-am62.dtsi | 7 ++++-
3 files changed, 47 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/ti/k3-am62-thermal.dtsi
diff --git a/arch/arm64/boot/dts/ti/k3-am62-thermal.dtsi b/arch/arm64/boot/dts/ti/k3-am62-thermal.dtsi
new file mode 100644
index 0000000000000..1819a6948b19d
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am62-thermal.dtsi
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/thermal/thermal.h>
+
+thermal_zones: thermal-zones {
+ main0_thermal: main0-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&vtm0 0>;
+
+ trips {
+ main0_crit: main0-crit {
+ temperature = <105000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ main1_thermal: main1-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&vtm0 1>;
+
+ trips {
+ main1_crit: main1-crit {
+ temperature = <105000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi
index 4090134676cf6..3954a73a33f35 100644
--- a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi
@@ -38,4 +38,12 @@ wkup_i2c0: i2c@2b200000 {
clocks = <&k3_clks 107 4>;
clock-names = "fck";
};
+
+ vtm0: temperature-sensor@b00000 {
+ compatible = "ti,j7200-vtm";
+ reg = <0x00 0xb00000 0x00 0x400>,
+ <0x00 0xb01000 0x00 0x400>;
+ power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>;
+ #thermal-sensor-cells = <1>;
+ };
};
diff --git a/arch/arm64/boot/dts/ti/k3-am62.dtsi b/arch/arm64/boot/dts/ti/k3-am62.dtsi
index 37fcbe7a3c336..1795f3ee534e0 100644
--- a/arch/arm64/boot/dts/ti/k3-am62.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62.dtsi
@@ -80,6 +80,7 @@ cbass_main: bus@f0000 {
<0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>,
/* Wakeup Domain Range */
+ <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
<0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>,
<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>;
@@ -94,10 +95,14 @@ cbass_wakeup: bus@2b000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
- ranges = <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
+ ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
+ <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>;
};
};
+
+ #include "k3-am62-thermal.dtsi"
+
};
/* Now include the peripherals for each bus segments */
--
2.38.1
The j721e supports a single Voltage and Thermal Management (VTM) module
located in the wakeup domain with five associated temperature monitors
located in various hot spots on the die.
Signed-off-by: Bryan Brattlof <[email protected]>
---
.../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 9 +++
arch/arm64/boot/dts/ti/k3-j721e-thermal.dtsi | 75 +++++++++++++++++++
arch/arm64/boot/dts/ti/k3-j721e.dtsi | 3 +
3 files changed, 87 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-thermal.dtsi
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
index df08724bbf1c5..9a09f66c51c01 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
@@ -418,4 +418,13 @@ mcu_mcan1: can@40568000 {
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
};
+
+ vtm0: temperature-sensor@42040000 {
+ compatible = "ti,j721e-vtm";
+ reg = <0x00 0x42040000 0x00 0x350>,
+ <0x00 0x42050000 0x00 0x350>,
+ <0x00 0x43000300 0x00 0x10>;
+ power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
+ #thermal-sensor-cells = <1>;
+ };
};
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-thermal.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-thermal.dtsi
new file mode 100644
index 0000000000000..79641927a9092
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j721e-thermal.dtsi
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/thermal/thermal.h>
+
+thermal_zones: thermal-zones {
+ wkup_thermal: wkup-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&vtm0 0>;
+
+ trips {
+ wkup_crit: wkup-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ mpu_thermal: mpu-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&vtm0 1>;
+
+ trips {
+ mpu_crit: mpu-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ c7x_thermal: c7x-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&vtm0 2>;
+
+ trips {
+ c7x_crit: c7x-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ gpu_thermal: gpu-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&vtm0 3>;
+
+ trips {
+ gpu_crit: gpu-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ r5f_thermal: r5f-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&vtm0 4>;
+
+ trips {
+ r5f_crit: r5f-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
index 0e23886c9fd1d..cfab10e2455c4 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
@@ -181,6 +181,9 @@ cbass_mcu_wakeup: bus@28380000 {
<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/
};
};
+
+ #include "k3-j721e-thermal.dtsi"
+
};
/* Now include the peripherals for each bus segments */
--
2.38.1
Only some of TI's J721E SoCs will need a eFuse register range mapped to
determine if they're affected by TI's i2128 erratum. All other SoC will
not need this eFuse range to function properly
Update the bindings for the k3_j72xx_bandgap thermal driver so other
devices will only need two register ranges
Signed-off-by: Bryan Brattlof <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
---
.../bindings/thermal/ti,j72xx-thermal.yaml | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/Documentation/devicetree/bindings/thermal/ti,j72xx-thermal.yaml b/Documentation/devicetree/bindings/thermal/ti,j72xx-thermal.yaml
index 3bb870a26872f..0509c9cec224d 100644
--- a/Documentation/devicetree/bindings/thermal/ti,j72xx-thermal.yaml
+++ b/Documentation/devicetree/bindings/thermal/ti,j72xx-thermal.yaml
@@ -37,6 +37,7 @@ properties:
devices to function properly. This eFuse region provides
the information needed for these SoCs to report
temperatures accurately.
+ minItems: 2
power-domains:
maxItems: 1
@@ -44,6 +45,21 @@ properties:
"#thermal-sensor-cells":
const: 1
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: ti,j721e-vtm
+ then:
+ properties:
+ reg:
+ minItems: 3
+ else:
+ properties:
+ reg:
+ maxItems: 2
+
required:
- compatible
- reg
--
2.38.1
On 01/11/2022 00:26, Bryan Brattlof wrote:
> Hello again everyone!
>
> This series enables the VTM nodes for all of Texas Instrument's K3 SoCs
>
> Most of this series updates the k3_j72xx_bandgap driver to conditionally
> map an eFuse region used by the j721e to work around an issue in its VTM
> implementation and allows us to save the SPARE_FUSE region on other SoCs
>
> We can then update the device tree bindings for the driver and finally
> define the VTM nodes for each device
>
> Thanks for reviewing again
> ~Bryan
patch 1-6 applied, thanks
--
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