This series improves some more the support for MT8192 Asurada-based
Chromebooks, by enabling some missing functionality, namely the internal
display and audio.
In addition to that, aliases are also added for the i2c and mmc nodes,
which should've been done while adding the devices in the previous
series.
Some notable components that are still missing support are:
- external display/HDMI audio (waiting for [1])
- GPU (waiting for [2])
As part of testing the audio, an UCM file was used, which has already
been submitted upstream [3].
This series depends on some missing dt-binding properties on rt5682,
which are added by another series [4].
[1] https://lore.kernel.org/all/[email protected]/
[2] https://lore.kernel.org/all/[email protected]
[3] https://github.com/alsa-project/alsa-ucm-conf/pull/217
[4] https://lore.kernel.org/all/[email protected]
v2: https://lore.kernel.org/all/[email protected]
v1: https://lore.kernel.org/all/[email protected]/
Changes in v3:
- Moved codec and sound card compatibles to separate dtsi to prepare for
headset codec differences in newer revisions
- Added new supplies for rt5682
- Removed i2c aliases for unused controllers
Changes in v2:
- Extended series to also include patches 4 and 5 enabling audio and
adding aliases
- Adjusted display regulator hierarchy and voltages to reflect the
hardware
Nícolas F. R. A. Prado (5):
arm64: dts: mediatek: asurada: Add display regulators
arm64: dts: mediatek: asurada: Add display backlight
arm64: dts: mediatek: asurada: Enable internal display
arm64: dts: mediatek: asurada: Enable audio support
arm64: dts: mediatek: asurada: Add aliases for i2c and mmc
.../mt8192-asurada-audio-rt1015p-rt5682.dtsi | 19 +
.../mt8192-asurada-audio-rt1015p.dtsi | 26 +
.../mediatek/mt8192-asurada-audio-rt5682.dtsi | 21 +
.../dts/mediatek/mt8192-asurada-hayato-r1.dts | 1 +
.../mediatek/mt8192-asurada-spherion-r0.dts | 1 +
.../boot/dts/mediatek/mt8192-asurada.dtsi | 465 ++++++++++++++++++
6 files changed, 533 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-audio-rt1015p-rt5682.dtsi
create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-audio-rt1015p.dtsi
create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-audio-rt5682.dtsi
--
2.38.1
Add aliases for the i2c and mmc nodes on the Asurada platform DT to
ensure that we get stable ids for those devices on userspace.
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Signed-off-by: Nícolas F. R. A. Prado <[email protected]>
---
Changes in v3:
- Removed i2c4, 5, 6, 8 and 9 as they aren't used on asurada
Changes in v2:
- Added this commit
arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
index ce9e43475f9e..9f12257ab4e7 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
@@ -11,6 +11,13 @@
/ {
aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c7 = &i2c7;
+ mmc0 = &mmc0;
+ mmc1 = &mmc1;
serial0 = &uart0;
};
--
2.38.1
Enable audio support for the Asurada platform. This consists of the
machine sound card, the rt1015p codec for the speakers, the rt5682 codec
for the headset, and the dmic codec for the internal microphone.
Newer revisions of spherion and hayato use the rt5682s codec for the
headset instead, so the codecs and card compatible are added through
separate dtsi files to prepare for that.
HDMI audio support is left out for now since the DisplayPort chip
required isn't enabled yet.
Tested-by: Chen-Yu Tsai <[email protected]>
Signed-off-by: Nícolas F. R. A. Prado <[email protected]>
---
Changes in v3:
- Moved rt5682, rt1015p and sound card compatible to separate dtsi files
to prepare for future revisions using different codecs
- Made node names generic for rt5682, rt1015p and sound card
- Set sound-dai-cells to 1 for rt5682
- Added DBVDD and LDO1-IN supplies for rt5682
Changes in v2:
- Added this commit
.../mt8192-asurada-audio-rt1015p-rt5682.dtsi | 19 ++
.../mt8192-asurada-audio-rt1015p.dtsi | 26 ++
.../mediatek/mt8192-asurada-audio-rt5682.dtsi | 21 ++
.../dts/mediatek/mt8192-asurada-hayato-r1.dts | 1 +
.../mediatek/mt8192-asurada-spherion-r0.dts | 1 +
.../boot/dts/mediatek/mt8192-asurada.dtsi | 245 ++++++++++++++++++
6 files changed, 313 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-audio-rt1015p-rt5682.dtsi
create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-audio-rt1015p.dtsi
create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-audio-rt5682.dtsi
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-audio-rt1015p-rt5682.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada-audio-rt1015p-rt5682.dtsi
new file mode 100644
index 000000000000..f521f50d448f
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-audio-rt1015p-rt5682.dtsi
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2020 Google LLC
+ */
+
+#include "mt8192-asurada-audio-rt5682.dtsi"
+#include "mt8192-asurada-audio-rt1015p.dtsi"
+
+&sound {
+ compatible = "mediatek,mt8192_mt6359_rt1015p_rt5682";
+
+ speaker-codecs {
+ sound-dai = <&rt1015p>;
+ };
+
+ headset-codec {
+ sound-dai = <&rt5682 0>;
+ };
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-audio-rt1015p.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada-audio-rt1015p.dtsi
new file mode 100644
index 000000000000..e5743789934e
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-audio-rt1015p.dtsi
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
+
+/ {
+ rt1015p: audio-codec {
+ compatible = "realtek,rt1015p";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rt1015p_pins>;
+ sdb-gpios = <&pio 147 GPIO_ACTIVE_HIGH>;
+ #sound-dai-cells = <0>;
+ };
+};
+
+&pio {
+ rt1015p_pins: rt1015p-default-pins {
+ pins {
+ pinmux = <PINMUX_GPIO147__FUNC_GPIO147>;
+ output-low;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-audio-rt5682.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada-audio-rt5682.dtsi
new file mode 100644
index 000000000000..05e48b870a92
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-audio-rt5682.dtsi
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ */
+
+&i2c1 {
+ rt5682: audio-codec@1a {
+ compatible = "realtek,rt5682i";
+ reg = <0x1a>;
+ interrupts-extended = <&pio 18 IRQ_TYPE_LEVEL_LOW>;
+ realtek,jd-src = <1>;
+ realtek,btndet-delay = <16>;
+ #sound-dai-cells = <1>;
+
+ AVDD-supply = <&mt6359_vio18_ldo_reg>;
+ DBVDD-supply = <&mt6359_vio18_ldo_reg>;
+ LDO1-IN-supply = <&mt6359_vio18_ldo_reg>;
+ MICVDD-supply = <&pp3300_g>;
+ VBAT-supply = <&pp3300_ldo_z>;
+ };
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts
index 1e91491945f6..43a823990a92 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts
@@ -4,6 +4,7 @@
*/
/dts-v1/;
#include "mt8192-asurada.dtsi"
+#include "mt8192-asurada-audio-rt1015p-rt5682.dtsi"
/ {
model = "Google Hayato rev1";
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts
index fa3d9573f37a..c6ad10cec95e 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts
@@ -4,6 +4,7 @@
*/
/dts-v1/;
#include "mt8192-asurada.dtsi"
+#include "mt8192-asurada-audio-rt1015p-rt5682.dtsi"
#include <dt-bindings/leds/common.h>
/ {
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
index ace44827de17..ce9e43475f9e 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
@@ -33,6 +33,12 @@ backlight_lcd0: backlight-lcd0 {
default-brightness-level = <576>;
};
+ dmic_codec: dmic-codec {
+ compatible = "dmic-codec";
+ num-channels = <2>;
+ wakeup-delay-ms = <50>;
+ };
+
pp1000_dpbrdg: regulator-1v0-dpbrdg {
compatible = "regulator-fixed";
regulator-name = "pp1000_dpbrdg";
@@ -196,6 +202,62 @@ wifi_restricted_dma_region: wifi@c0000000 {
reg = <0 0xc0000000 0 0x4000000>;
};
};
+
+ sound: sound {
+ mediatek,platform = <&afe>;
+ pinctrl-names = "aud_clk_mosi_off",
+ "aud_clk_mosi_on",
+ "aud_dat_mosi_off",
+ "aud_dat_mosi_on",
+ "aud_dat_miso_off",
+ "aud_dat_miso_on",
+ "vow_dat_miso_off",
+ "vow_dat_miso_on",
+ "vow_clk_miso_off",
+ "vow_clk_miso_on",
+ "aud_nle_mosi_off",
+ "aud_nle_mosi_on",
+ "aud_dat_miso2_off",
+ "aud_dat_miso2_on",
+ "aud_gpio_i2s3_off",
+ "aud_gpio_i2s3_on",
+ "aud_gpio_i2s8_off",
+ "aud_gpio_i2s8_on",
+ "aud_gpio_i2s9_off",
+ "aud_gpio_i2s9_on",
+ "aud_dat_mosi_ch34_off",
+ "aud_dat_mosi_ch34_on",
+ "aud_dat_miso_ch34_off",
+ "aud_dat_miso_ch34_on",
+ "aud_gpio_tdm_off",
+ "aud_gpio_tdm_on";
+ pinctrl-0 = <&aud_clk_mosi_off_pins>;
+ pinctrl-1 = <&aud_clk_mosi_on_pins>;
+ pinctrl-2 = <&aud_dat_mosi_off_pins>;
+ pinctrl-3 = <&aud_dat_mosi_on_pins>;
+ pinctrl-4 = <&aud_dat_miso_off_pins>;
+ pinctrl-5 = <&aud_dat_miso_on_pins>;
+ pinctrl-6 = <&vow_dat_miso_off_pins>;
+ pinctrl-7 = <&vow_dat_miso_on_pins>;
+ pinctrl-8 = <&vow_clk_miso_off_pins>;
+ pinctrl-9 = <&vow_clk_miso_on_pins>;
+ pinctrl-10 = <&aud_nle_mosi_off_pins>;
+ pinctrl-11 = <&aud_nle_mosi_on_pins>;
+ pinctrl-12 = <&aud_dat_miso2_off_pins>;
+ pinctrl-13 = <&aud_dat_miso2_on_pins>;
+ pinctrl-14 = <&aud_gpio_i2s3_off_pins>;
+ pinctrl-15 = <&aud_gpio_i2s3_on_pins>;
+ pinctrl-16 = <&aud_gpio_i2s8_off_pins>;
+ pinctrl-17 = <&aud_gpio_i2s8_on_pins>;
+ pinctrl-18 = <&aud_gpio_i2s9_off_pins>;
+ pinctrl-19 = <&aud_gpio_i2s9_on_pins>;
+ pinctrl-20 = <&aud_dat_mosi_ch34_off_pins>;
+ pinctrl-21 = <&aud_dat_mosi_ch34_on_pins>;
+ pinctrl-22 = <&aud_dat_miso_ch34_off_pins>;
+ pinctrl-23 = <&aud_dat_miso_ch34_on_pins>;
+ pinctrl-24 = <&aud_gpio_tdm_off_pins>;
+ pinctrl-25 = <&aud_gpio_tdm_on_pins>;
+ };
};
&dsi0 {
@@ -660,6 +722,165 @@ pins-in {
};
};
+ aud_clk_mosi_off_pins: aud-clk-mosi-off-pins {
+ pins-mosi-off {
+ pinmux = <PINMUX_GPIO214__FUNC_GPIO214>,
+ <PINMUX_GPIO215__FUNC_GPIO215>;
+ };
+ };
+
+ aud_clk_mosi_on_pins: aud-clk-mosi-on-pins {
+ pins-mosi-on {
+ pinmux = <PINMUX_GPIO214__FUNC_AUD_CLK_MOSI>,
+ <PINMUX_GPIO215__FUNC_AUD_SYNC_MOSI>;
+ drive-strength = <10>;
+ };
+ };
+
+ aud_dat_miso_ch34_off_pins: aud-dat-miso-ch34-off-pins {
+ pins-miso-off {
+ pinmux = <PINMUX_GPIO199__FUNC_GPIO199>;
+ };
+ };
+
+ aud_dat_miso_ch34_on_pins: aud-dat-miso-ch34-on-pins {
+ pins-miso-on {
+ pinmux = <PINMUX_GPIO199__FUNC_AUD_DAT_MISO2>;
+ };
+ };
+
+ aud_dat_miso_off_pins: aud-dat-miso-off-pins {
+ pins-miso-off {
+ pinmux = <PINMUX_GPIO218__FUNC_GPIO218>,
+ <PINMUX_GPIO219__FUNC_GPIO219>;
+ };
+ };
+
+ aud_dat_miso_on_pins: aud-dat-miso-on-pins {
+ pins-miso-on {
+ pinmux = <PINMUX_GPIO218__FUNC_AUD_DAT_MISO0>,
+ <PINMUX_GPIO219__FUNC_AUD_DAT_MISO1>;
+ drive-strength = <10>;
+ };
+ };
+
+ aud_dat_miso2_off_pins: aud-dat-miso2-off-pins {
+ pins-miso-off {
+ pinmux = <PINMUX_GPIO199__FUNC_GPIO199>;
+ };
+ };
+
+ aud_dat_miso2_on_pins: aud-dat-miso2-on-pins {
+ pins-miso-on {
+ pinmux = <PINMUX_GPIO199__FUNC_AUD_DAT_MISO2>;
+ };
+ };
+
+ aud_dat_mosi_ch34_off_pins: aud-dat-mosi-ch34-off-pins {
+ pins-mosi-off {
+ pinmux = <PINMUX_GPIO196__FUNC_GPIO196>;
+ };
+ };
+
+ aud_dat_mosi_ch34_on_pins: aud-dat-mosi-ch34-on-pins {
+ pins-mosi-on {
+ pinmux = <PINMUX_GPIO196__FUNC_AUD_DAT_MOSI2>;
+ };
+ };
+
+ aud_dat_mosi_off_pins: aud-dat-mosi-off-pins {
+ pins-mosi-off {
+ pinmux = <PINMUX_GPIO216__FUNC_GPIO216>,
+ <PINMUX_GPIO217__FUNC_GPIO217>;
+ };
+ };
+
+ aud_dat_mosi_on_pins: aud-dat-mosi-on-pins {
+ pins-mosi-on {
+ pinmux = <PINMUX_GPIO216__FUNC_AUD_DAT_MOSI0>,
+ <PINMUX_GPIO217__FUNC_AUD_DAT_MOSI1>;
+ drive-strength = <10>;
+ };
+ };
+
+ aud_gpio_i2s3_off_pins: aud-gpio-i2s3-off-pins {
+ pins-i2s3-off {
+ pinmux = <PINMUX_GPIO32__FUNC_GPIO32>,
+ <PINMUX_GPIO33__FUNC_GPIO33>,
+ <PINMUX_GPIO35__FUNC_GPIO35>;
+ };
+ };
+
+ aud_gpio_i2s3_on_pins: aud-gpio-i2s3-on-pins {
+ pins-i2s3-on {
+ pinmux = <PINMUX_GPIO32__FUNC_I2S3_BCK>,
+ <PINMUX_GPIO33__FUNC_I2S3_LRCK>,
+ <PINMUX_GPIO35__FUNC_I2S3_DO>;
+ };
+ };
+
+ aud_gpio_i2s8_off_pins: aud-gpio-i2s8-off-pins {
+ pins-i2s8-off {
+ pinmux = <PINMUX_GPIO10__FUNC_GPIO10>,
+ <PINMUX_GPIO11__FUNC_GPIO11>,
+ <PINMUX_GPIO12__FUNC_GPIO12>,
+ <PINMUX_GPIO13__FUNC_GPIO13>;
+ };
+ };
+
+ aud_gpio_i2s8_on_pins: aud-gpio-i2s8-on-pins {
+ pins-i2s8-on {
+ pinmux = <PINMUX_GPIO10__FUNC_I2S8_MCK>,
+ <PINMUX_GPIO11__FUNC_I2S8_BCK>,
+ <PINMUX_GPIO12__FUNC_I2S8_LRCK>,
+ <PINMUX_GPIO13__FUNC_I2S8_DI>;
+ };
+ };
+
+ aud_gpio_i2s9_off_pins: aud-gpio-i2s9-off-pins {
+ pins-i2s9-off {
+ pinmux = <PINMUX_GPIO29__FUNC_GPIO29>;
+ };
+ };
+
+ aud_gpio_i2s9_on_pins: aud-gpio-i2s9-on-pins {
+ pins-i2s9-on {
+ pinmux = <PINMUX_GPIO29__FUNC_I2S9_DO>;
+ };
+ };
+
+ aud_gpio_tdm_off_pins: aud-gpio-tdm-off-pins {
+ pins-tdm-off {
+ pinmux = <PINMUX_GPIO0__FUNC_GPIO0>,
+ <PINMUX_GPIO1__FUNC_GPIO1>,
+ <PINMUX_GPIO2__FUNC_GPIO2>,
+ <PINMUX_GPIO3__FUNC_GPIO3>;
+ };
+ };
+
+ aud_gpio_tdm_on_pins: aud-gpio-tdm-on-pins {
+ pins-tdm-on {
+ pinmux = <PINMUX_GPIO0__FUNC_TDM_LRCK>,
+ <PINMUX_GPIO1__FUNC_TDM_BCK>,
+ <PINMUX_GPIO2__FUNC_TDM_MCK>,
+ <PINMUX_GPIO3__FUNC_TDM_DATA0>;
+ };
+ };
+
+ aud_nle_mosi_off_pins: aud-nle-mosi-off-pins {
+ pins-nle-mosi-off {
+ pinmux = <PINMUX_GPIO197__FUNC_GPIO197>,
+ <PINMUX_GPIO198__FUNC_GPIO198>;
+ };
+ };
+
+ aud_nle_mosi_on_pins: aud-nle-mosi-on-pins {
+ pins-nle-mosi-on {
+ pinmux = <PINMUX_GPIO197__FUNC_AUD_NLE_MOSI1>,
+ <PINMUX_GPIO198__FUNC_AUD_NLE_MOSI0>;
+ };
+ };
+
cr50_int: cr50-irq-default-pins {
pins-gsc-ap-int-odl {
pinmux = <PINMUX_GPIO171__FUNC_GPIO171>;
@@ -987,6 +1208,30 @@ pins-report-sw {
output-low;
};
};
+
+ vow_clk_miso_off_pins: vow-clk-miso-off-pins {
+ pins-miso-off {
+ pinmux = <PINMUX_GPIO219__FUNC_GPIO219>;
+ };
+ };
+
+ vow_clk_miso_on_pins: vow-clk-miso-on-pins {
+ pins-miso-on {
+ pinmux = <PINMUX_GPIO219__FUNC_VOW_CLK_MISO>;
+ };
+ };
+
+ vow_dat_miso_off_pins: vow-dat-miso-off-pins {
+ pins-miso-off {
+ pinmux = <PINMUX_GPIO218__FUNC_GPIO218>;
+ };
+ };
+
+ vow_dat_miso_on_pins: vow-dat-miso-on-pins {
+ pins-miso-on {
+ pinmux = <PINMUX_GPIO218__FUNC_VOW_DAT_MISO>;
+ };
+ };
};
&pmic {
--
2.38.1
Add the regulators present on the Asurada platform that are used to
power the internal and external displays.
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Tested-by: Chen-Yu Tsai <[email protected]>
Signed-off-by: Nícolas F. R. A. Prado <[email protected]>
---
(no changes since v2)
Changes in v2:
- Added missing vin-supply to regulators
- Removed min/max-microvolt from regulators that are simple switches
.../boot/dts/mediatek/mt8192-asurada.dtsi | 112 ++++++++++++++++++
1 file changed, 112 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
index 4b314435f8fd..fafca7428539 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
@@ -23,6 +23,43 @@ memory@40000000 {
reg = <0 0x40000000 0 0x80000000>;
};
+ pp1000_dpbrdg: regulator-1v0-dpbrdg {
+ compatible = "regulator-fixed";
+ regulator-name = "pp1000_dpbrdg";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pp1000_dpbrdg_en_pins>;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ enable-active-high;
+ regulator-boot-on;
+ gpio = <&pio 19 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&mt6359_vs2_buck_reg>;
+ };
+
+ pp1000_mipibrdg: regulator-1v0-mipibrdg {
+ compatible = "regulator-fixed";
+ regulator-name = "pp1000_mipibrdg";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pp1000_mipibrdg_en_pins>;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ enable-active-high;
+ regulator-boot-on;
+ gpio = <&pio 129 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&mt6359_vs2_buck_reg>;
+ };
+
+ pp1800_dpbrdg: regulator-1v8-dpbrdg {
+ compatible = "regulator-fixed";
+ regulator-name = "pp1800_dpbrdg";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pp1800_dpbrdg_en_pins>;
+ enable-active-high;
+ regulator-boot-on;
+ gpio = <&pio 126 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&mt6359_vio18_ldo_reg>;
+ };
+
/* system wide LDO 1.8V power rail */
pp1800_ldo_g: regulator-1v8-g {
compatible = "regulator-fixed";
@@ -34,6 +71,28 @@ pp1800_ldo_g: regulator-1v8-g {
vin-supply = <&pp3300_g>;
};
+ pp1800_mipibrdg: regulator-1v8-mipibrdg {
+ compatible = "regulator-fixed";
+ regulator-name = "pp1800_mipibrdg";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pp1800_mipibrdg_en_pins>;
+ enable-active-high;
+ regulator-boot-on;
+ gpio = <&pio 128 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&mt6359_vio18_ldo_reg>;
+ };
+
+ pp3300_dpbrdg: regulator-3v3-dpbrdg {
+ compatible = "regulator-fixed";
+ regulator-name = "pp3300_dpbrdg";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pp3300_dpbrdg_en_pins>;
+ enable-active-high;
+ regulator-boot-on;
+ gpio = <&pio 26 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&pp3300_g>;
+ };
+
/* system wide switching 3.3V power rail */
pp3300_g: regulator-3v3-g {
compatible = "regulator-fixed";
@@ -56,6 +115,17 @@ pp3300_ldo_z: regulator-3v3-z {
vin-supply = <&ppvar_sys>;
};
+ pp3300_mipibrdg: regulator-3v3-mipibrdg {
+ compatible = "regulator-fixed";
+ regulator-name = "pp3300_mipibrdg";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pp3300_mipibrdg_en_pins>;
+ enable-active-high;
+ regulator-boot-on;
+ gpio = <&pio 127 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&pp3300_g>;
+ };
+
/* separately switched 3.3V power rail */
pp3300_u: regulator-3v3-u {
compatible = "regulator-fixed";
@@ -719,6 +789,48 @@ pins-wifi-kill {
};
};
+ pp1000_dpbrdg_en_pins: pp1000-dpbrdg-en-pins {
+ pins-en {
+ pinmux = <PINMUX_GPIO19__FUNC_GPIO19>;
+ output-low;
+ };
+ };
+
+ pp1000_mipibrdg_en_pins: pp1000-mipibrdg-en-pins {
+ pins-en {
+ pinmux = <PINMUX_GPIO129__FUNC_GPIO129>;
+ output-low;
+ };
+ };
+
+ pp1800_dpbrdg_en_pins: pp1800-dpbrdg-en-pins {
+ pins-en {
+ pinmux = <PINMUX_GPIO126__FUNC_GPIO126>;
+ output-low;
+ };
+ };
+
+ pp1800_mipibrdg_en_pins: pp1800-mipibrd-en-pins {
+ pins-en {
+ pinmux = <PINMUX_GPIO128__FUNC_GPIO128>;
+ output-low;
+ };
+ };
+
+ pp3300_dpbrdg_en_pins: pp3300-dpbrdg-en-pins {
+ pins-en {
+ pinmux = <PINMUX_GPIO26__FUNC_GPIO26>;
+ output-low;
+ };
+ };
+
+ pp3300_mipibrdg_en_pins: pp3300-mipibrdg-en-pins {
+ pins-en {
+ pinmux = <PINMUX_GPIO127__FUNC_GPIO127>;
+ output-low;
+ };
+ };
+
pp3300_wlan_pins: pp3300-wlan-pins {
pins-pcie-en-pp3300-wlan {
pinmux = <PINMUX_GPIO143__FUNC_GPIO143>;
--
2.38.1
Add the display backlight for the Asurada platform. It relies on the
display PWM controller, so also enable and configure this component.
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Tested-by: Chen-Yu Tsai <[email protected]>
Signed-off-by: Nícolas F. R. A. Prado <[email protected]>
---
(no changes since v1)
.../boot/dts/mediatek/mt8192-asurada.dtsi | 28 +++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
index fafca7428539..666021ca4d4f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
@@ -23,6 +23,16 @@ memory@40000000 {
reg = <0 0x40000000 0 0x80000000>;
};
+ backlight_lcd0: backlight-lcd0 {
+ compatible = "pwm-backlight";
+ pwms = <&pwm0 0 500000>;
+ power-supply = <&ppvar_sys>;
+ enable-gpios = <&pio 152 0>;
+ brightness-levels = <0 1023>;
+ num-interpolated-steps = <1023>;
+ default-brightness-level = <576>;
+ };
+
pp1000_dpbrdg: regulator-1v0-dpbrdg {
compatible = "regulator-fixed";
regulator-name = "pp1000_dpbrdg";
@@ -838,6 +848,17 @@ pins-pcie-en-pp3300-wlan {
};
};
+ pwm0_pins: pwm0-default-pins {
+ pins-pwm {
+ pinmux = <PINMUX_GPIO40__FUNC_DISP_PWM>;
+ };
+
+ pins-inhibit {
+ pinmux = <PINMUX_GPIO152__FUNC_GPIO152>;
+ output-high;
+ };
+ };
+
scp_pins: scp-pins {
pins-vreq-vao {
pinmux = <PINMUX_GPIO195__FUNC_SCP_VREQ_VAO>;
@@ -899,6 +920,13 @@ &pmic {
interrupts-extended = <&pio 214 IRQ_TYPE_LEVEL_HIGH>;
};
+&pwm0 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_pins>;
+};
+
&scp {
status = "okay";
--
2.38.1
The asurada platform has an ANX7625 bridge connecting the DSI's output
to the internal eDP panel. Add and enable these devices in order to get
a usable internal display.
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Tested-by: Chen-Yu Tsai <[email protected]>
Signed-off-by: Nícolas F. R. A. Prado <[email protected]>
---
(no changes since v1)
.../boot/dts/mediatek/mt8192-asurada.dtsi | 73 +++++++++++++++++++
1 file changed, 73 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
index 666021ca4d4f..ace44827de17 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
@@ -198,6 +198,14 @@ wifi_restricted_dma_region: wifi@c0000000 {
};
};
+&dsi0 {
+ status = "okay";
+};
+
+&dsi_out {
+ remote-endpoint = <&anx7625_in>;
+};
+
&i2c0 {
status = "okay";
@@ -246,6 +254,53 @@ &i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&i2c3_pins>;
+
+ anx_bridge: anx7625@58 {
+ compatible = "analogix,anx7625";
+ reg = <0x58>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&anx7625_pins>;
+ enable-gpios = <&pio 41 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&pio 42 GPIO_ACTIVE_HIGH>;
+ vdd10-supply = <&pp1000_mipibrdg>;
+ vdd18-supply = <&pp1800_mipibrdg>;
+ vdd33-supply = <&pp3300_mipibrdg>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ anx7625_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ anx7625_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+
+ aux-bus {
+ panel: panel {
+ compatible = "edp-panel";
+ power-supply = <&pp3300_mipibrdg>;
+ backlight = <&backlight_lcd0>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&anx7625_out>;
+ };
+ };
+ };
+ };
+ };
};
&i2c7 {
@@ -256,6 +311,10 @@ &i2c7 {
pinctrl-0 = <&i2c7_pins>;
};
+&mipi_tx0 {
+ status = "okay";
+};
+
&mmc0 {
status = "okay";
@@ -587,6 +646,20 @@ &pio {
"AUD_DAT_MISO0",
"AUD_DAT_MISO1";
+ anx7625_pins: anx7625-default-pins {
+ pins-out {
+ pinmux = <PINMUX_GPIO41__FUNC_GPIO41>,
+ <PINMUX_GPIO42__FUNC_GPIO42>;
+ output-low;
+ };
+
+ pins-in {
+ pinmux = <PINMUX_GPIO6__FUNC_GPIO6>;
+ input-enable;
+ bias-pull-up;
+ };
+ };
+
cr50_int: cr50-irq-default-pins {
pins-gsc-ap-int-odl {
pinmux = <PINMUX_GPIO171__FUNC_GPIO171>;
--
2.38.1
Il 02/11/22 20:06, Nícolas F. R. A. Prado ha scritto:
> Enable audio support for the Asurada platform. This consists of the
> machine sound card, the rt1015p codec for the speakers, the rt5682 codec
> for the headset, and the dmic codec for the internal microphone.
>
> Newer revisions of spherion and hayato use the rt5682s codec for the
> headset instead, so the codecs and card compatible are added through
> separate dtsi files to prepare for that.
>
> HDMI audio support is left out for now since the DisplayPort chip
> required isn't enabled yet.
>
> Tested-by: Chen-Yu Tsai <[email protected]>
> Signed-off-by: Nícolas F. R. A. Prado <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
On Thu, Nov 3, 2022 at 3:06 AM Nícolas F. R. A. Prado
<[email protected]> wrote:
>
>
> This series improves some more the support for MT8192 Asurada-based
> Chromebooks, by enabling some missing functionality, namely the internal
> display and audio.
>
> In addition to that, aliases are also added for the i2c and mmc nodes,
> which should've been done while adding the devices in the previous
> series.
>
> Some notable components that are still missing support are:
> - external display/HDMI audio (waiting for [1])
> - GPU (waiting for [2])
>
> As part of testing the audio, an UCM file was used, which has already
> been submitted upstream [3].
>
> This series depends on some missing dt-binding properties on rt5682,
> which are added by another series [4].
Hi Matthias,
This series has been floating around for some time now, and has been fully
tested by multiple parties. The rt5682 dt-binding changes have also been
merged.
Could you queue it up?
Thanks
ChenYu
On 30/11/2022 04:11, Chen-Yu Tsai wrote:
> On Thu, Nov 3, 2022 at 3:06 AM Nícolas F. R. A. Prado
> <[email protected]> wrote:
>>
>>
>> This series improves some more the support for MT8192 Asurada-based
>> Chromebooks, by enabling some missing functionality, namely the internal
>> display and audio.
>>
>> In addition to that, aliases are also added for the i2c and mmc nodes,
>> which should've been done while adding the devices in the previous
>> series.
>>
>> Some notable components that are still missing support are:
>> - external display/HDMI audio (waiting for [1])
>> - GPU (waiting for [2])
>>
>> As part of testing the audio, an UCM file was used, which has already
>> been submitted upstream [3].
>>
>> This series depends on some missing dt-binding properties on rt5682,
>> which are added by another series [4].
>
> Hi Matthias,
>
> This series has been floating around for some time now, and has been fully
> tested by multiple parties. The rt5682 dt-binding changes have also been
> merged.
>
> Could you queue it up?
>
Applied now. Sorry for the delay!
Matthias