The following series of patches enables RPi header
on j721e sk. It is a 40 pin io expasion header which
brings out i2c5, ehrpwm 2,3 and some pins of gpio 0,1
v6:
- Rebased to 6.1-rc1
v5:
- Enable only gpio's and i2c on the RPi Header
as per the discussion in the v4
v4:
- Correct the node name in dt binding example
v3:
- Change node name from clock to clock-controller
- Add correct description for clock-controller node
v2:
- Add full path for clock property $ref
- Remove the discription for clock pattern property,
since $ref is added
- Remove the label in the example
- Fix the indentation in the example
Sinthu Raja (1):
arm64: dts: ti: k3-j721e-sk: Add pinmux for RPi Header
Vijay Pothukuchi (1):
arm64: dts: ti: k3-j721e-*: Add dts nodes for EHRPWMs
.../dts/ti/k3-j721e-common-proc-board.dts | 24 ++++++
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 62 ++++++++++++++-
arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 79 ++++++++++++++++++-
3 files changed, 163 insertions(+), 2 deletions(-)
--
2.38.0
From: Vijay Pothukuchi <[email protected]>
Add dts nodes for 6 EHRPWM instances on SoC
Signed-off-by: Vijay Pothukuchi <[email protected]>
Signed-off-by: Rahul T R <[email protected]>
---
.../dts/ti/k3-j721e-common-proc-board.dts | 24 +++++++
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 62 ++++++++++++++++++-
arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 24 +++++++
3 files changed, 109 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index b1691ac3442d..4f8ab839fbc4 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -995,3 +995,27 @@ &main_mcan12 {
&main_mcan13 {
status = "disabled";
};
+
+&main_ehrpwm0 {
+ status = "disabled";
+};
+
+&main_ehrpwm1 {
+ status = "disabled";
+};
+
+&main_ehrpwm2 {
+ status = "disabled";
+};
+
+&main_ehrpwm3 {
+ status = "disabled";
+};
+
+&main_ehrpwm4 {
+ status = "disabled";
+};
+
+&main_ehrpwm5 {
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 917c9dc99efa..2027c724a2d6 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -66,7 +66,67 @@ usb_serdes_mux: mux-controller@4000 {
#mux-control-cells = <1>;
mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */
<0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */
- };
+ };
+
+ ehrpwm_tbclk: clock-controller@4140 {
+ compatible = "ti,am654-ehrpwm-tbclk", "syscon";
+ reg = <0x4140 0x18>;
+ #clock-cells = <1>;
+ };
+ };
+
+ main_ehrpwm0: pwm@3000000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x00 0x3000000 0x00 0x100>;
+ power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 0>, <&k3_clks 83 0>;
+ clock-names = "tbclk", "fck";
+ };
+
+ main_ehrpwm1: pwm@3010000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x00 0x3010000 0x00 0x100>;
+ power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 1>, <&k3_clks 84 0>;
+ clock-names = "tbclk", "fck";
+ };
+
+ main_ehrpwm2: pwm@3020000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x00 0x3020000 0x00 0x100>;
+ power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 2>, <&k3_clks 85 0>;
+ clock-names = "tbclk", "fck";
+ };
+
+ main_ehrpwm3: pwm@3030000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x00 0x3030000 0x00 0x100>;
+ power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 3>, <&k3_clks 86 0>;
+ clock-names = "tbclk", "fck";
+ };
+
+ main_ehrpwm4: pwm@3040000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x00 0x3040000 0x00 0x100>;
+ power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 4>, <&k3_clks 87 0>;
+ clock-names = "tbclk", "fck";
+ };
+
+ main_ehrpwm5: pwm@3050000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x00 0x3050000 0x00 0x100>;
+ power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 5>, <&k3_clks 88 0>;
+ clock-names = "tbclk", "fck";
};
gic500: interrupt-controller@1800000 {
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
index 80358cba6954..98a55778f3fe 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
@@ -1129,3 +1129,27 @@ &c71_0 {
memory-region = <&c71_0_dma_memory_region>,
<&c71_0_memory_region>;
};
+
+&main_ehrpwm0 {
+ status = "disabled";
+};
+
+&main_ehrpwm1 {
+ status = "disabled";
+};
+
+&main_ehrpwm2 {
+ status = "disabled";
+};
+
+&main_ehrpwm3 {
+ status = "disabled";
+};
+
+&main_ehrpwm4 {
+ status = "disabled";
+};
+
+&main_ehrpwm5 {
+ status = "disabled";
+};
--
2.38.0
On 22:59-20221021, Rahul T R wrote:
> The following series of patches enables RPi header
> on j721e sk. It is a 40 pin io expasion header which
> brings out i2c5, ehrpwm 2,3 and some pins of gpio 0,1
>
> v6:
> - Rebased to 6.1-rc1
Now that the cleanups are in place, we'd need one additional rebase
please.
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
Hi Nishanth,
On 23:41-20221102, Nishanth Menon wrote:
> On 22:59-20221021, Rahul T R wrote:
> > The following series of patches enables RPi header
> > on j721e sk. It is a 40 pin io expasion header which
> > brings out i2c5, ehrpwm 2,3 and some pins of gpio 0,1
> >
> > v6:
> > - Rebased to 6.1-rc1
>
> Now that the cleanups are in place, we'd need one additional rebase
> please.
>
I have rebased and sent v7
Regards
Rahul T R
> --
> Regards,
> Nishanth Menon
> Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D