Apologies, resending because I botched the label in previous series.
Please reply to this series rather than the one sent previously.
Hi,
This series enables CPUFreq for AM625. This version is a fixup and
rebase of the patch series by Dave Gerlach on v6.1-rc3 [1].
It updates the ti-cpufreq driver to support parsing of the speed grade
value out of the JTAG_USER_ID register and adds necessary support code
to use cpufreq-dt.
The operating-points table that gets added support 200,400,600,800 for
all variants and then 1GHz for the S Speed grade only and 1.25 for the T
Speed grade only. 1.4GHz has been added in board specific dts file as it
requires VDD_CORE to be at 0.85V.
The latency between pre and post frequency transition was measured in
CPUFreq driver for all combinations of OPP changes. The average value
was selected as overall clock-latency.
Tested on am62-sk board using manual frequency changes and then reading
back frequency with k3conf, and this shows matching frequency to what
was set.
This should not impact existing K3 platforms that do not have operating
points table defined.
Regards,
Vibhore
[1] https://github.com/dgerlach/linux-pm/tree/v5.18/am62x-cpufreq
Dave Gerlach (4):
cpufreq: ti-cpufreq: Add support for AM625
cpufreq: dt-platdev: Blacklist ti,am625 SoC
arm64: dts: ti: k3-am625: Introduce operating-points table
cpufreq: ti: Enable ti-cpufreq for ARCH_K3
Vibhore Vardhan (1):
arm64: dts: ti: k3-am625-sk: Add 1.4GHz OPP
arch/arm64/boot/dts/ti/k3-am625-sk.dts | 9 +++++
arch/arm64/boot/dts/ti/k3-am625.dtsi | 51 ++++++++++++++++++++++++++
drivers/cpufreq/Kconfig.arm | 4 +-
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
drivers/cpufreq/ti-cpufreq.c | 36 ++++++++++++++++++
5 files changed, 99 insertions(+), 2 deletions(-)
--
2.34.1
From: Dave Gerlach <[email protected]>
Add ti,am625 SoC to the blacklist as the ti-cpufreq driver will handle
creating the cpufreq-dt platform device after it completes so it is not
created twice.
Signed-off-by: Dave Gerlach <[email protected]>
Signed-off-by: Vibhore Vardhan <[email protected]>
---
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index 6ac3800db450..85ee11f79840 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -160,6 +160,7 @@ static const struct of_device_id blocklist[] __initconst = {
{ .compatible = "ti,am43", },
{ .compatible = "ti,dra7", },
{ .compatible = "ti,omap3", },
+ { .compatible = "ti,am625", },
{ .compatible = "qcom,ipq8064", },
{ .compatible = "qcom,apq8064", },
--
2.34.1
From: Dave Gerlach <[email protected]>
Introduce an operating-points table for the A53 cores, containing only
frequency values as this platform operates on a fixed voltage for the
CPUs. Also provide opp-supported-hw values to ensure appropriate OPPs
are enabled based on which type of silicon is in use.
The latency between pre and post frequency transition was measured in
CPUFreq driver for all combinations of OPP changes. The average value
was selected as overall clock-latency-ns.
Signed-off-by: Dave Gerlach <[email protected]>
Signed-off-by: Vibhore Vardhan <[email protected]>
---
arch/arm64/boot/dts/ti/k3-am625.dtsi | 51 ++++++++++++++++++++++++++++
1 file changed, 51 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am625.dtsi b/arch/arm64/boot/dts/ti/k3-am625.dtsi
index 887f31c23fef..cea2cc7de5dd 100644
--- a/arch/arm64/boot/dts/ti/k3-am625.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am625.dtsi
@@ -48,6 +48,8 @@ cpu0: cpu@0 {
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&L2_0>;
+ operating-points-v2 = <&a53_opp_table>;
+ clocks = <&k3_clks 135 0>;
};
cpu1: cpu@1 {
@@ -62,6 +64,8 @@ cpu1: cpu@1 {
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&L2_0>;
+ operating-points-v2 = <&a53_opp_table>;
+ clocks = <&k3_clks 136 0>;
};
cpu2: cpu@2 {
@@ -76,6 +80,8 @@ cpu2: cpu@2 {
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&L2_0>;
+ operating-points-v2 = <&a53_opp_table>;
+ clocks = <&k3_clks 137 0>;
};
cpu3: cpu@3 {
@@ -90,6 +96,51 @@ cpu3: cpu@3 {
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&L2_0>;
+ operating-points-v2 = <&a53_opp_table>;
+ clocks = <&k3_clks 138 0>;
+ };
+ };
+
+ a53_opp_table: opp-table {
+ compatible = "operating-points-v2-ti-cpu";
+ opp-shared;
+ syscon = <&wkup_conf>;
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-supported-hw = <0x01 0x0007>;
+ clock-latency-ns = <6000000>;
+ };
+
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-supported-hw = <0x01 0x0007>;
+ clock-latency-ns = <6000000>;
+ };
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-supported-hw = <0x01 0x0007>;
+ clock-latency-ns = <6000000>;
+ };
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-supported-hw = <0x01 0x0007>;
+ clock-latency-ns = <6000000>;
+ };
+
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-supported-hw = <0x01 0x0006>;
+ clock-latency-ns = <6000000>;
+ };
+
+ opp-1250000000 {
+ opp-hz = /bits/ 64 <1250000000>;
+ opp-supported-hw = <0x01 0x0004>;
+ clock-latency-ns = <6000000>;
+ opp-suspend;
};
};
--
2.34.1
From: Dave Gerlach <[email protected]>
Make ti-cpufreq driver depend on ARCH_K3 and set it to `default y` so it
is always enabled for platforms that it depends on.
Signed-off-by: Dave Gerlach <[email protected]>
Signed-off-by: Vibhore Vardhan <[email protected]>
---
drivers/cpufreq/Kconfig.arm | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index 82e5de1f6f8c..be590f498e6a 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -340,8 +340,8 @@ config ARM_TEGRA194_CPUFREQ
config ARM_TI_CPUFREQ
bool "Texas Instruments CPUFreq support"
- depends on ARCH_OMAP2PLUS
- default ARCH_OMAP2PLUS
+ depends on ARCH_OMAP2PLUS || ARCH_K3
+ default y
help
This driver enables valid OPPs on the running platform based on
values contained within the SoC in use. Enable this in order to
--
2.34.1
The 1.4 GHz OPP requires supported silicon variant (T speed grade) and
also VDD_CORE to be at 0.85V. All production revisions of the AM625-SK
have both so we can enable the 1.4 GHz OPP for it. Any other boards
based on this design should verify that they have the right silicon
variant and the right power tree before adding 1.4 GHz support in their
board dts file.
Signed-off-by: Vibhore Vardhan <[email protected]>
---
arch/arm64/boot/dts/ti/k3-am625-sk.dts | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/ti/k3-am625-sk.dts
index 93a5f0817efc..4620ef5e19bb 100644
--- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts
@@ -31,6 +31,15 @@ chosen {
bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
};
+ opp-table {
+ /* Add 1.4GHz OPP for am625-sk board. Requires VDD_CORE to be at 0.85V */
+ opp-1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ opp-supported-hw = <0x01 0x0004>;
+ clock-latency-ns = <6000000>;
+ };
+ };
+
memory@80000000 {
device_type = "memory";
/* 2G RAM */
--
2.34.1
From: Dave Gerlach <[email protected]>
Add support for TI K3 AM625 SoC to read speed and revision values from
hardware and pass to OPP layer.
Signed-off-by: Dave Gerlach <[email protected]>
Signed-off-by: Vibhore Vardhan <[email protected]>
---
drivers/cpufreq/ti-cpufreq.c | 36 ++++++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/drivers/cpufreq/ti-cpufreq.c b/drivers/cpufreq/ti-cpufreq.c
index f64180dd2005..be4209d97cb3 100644
--- a/drivers/cpufreq/ti-cpufreq.c
+++ b/drivers/cpufreq/ti-cpufreq.c
@@ -39,6 +39,14 @@
#define OMAP34xx_ProdID_SKUID 0x4830A20C
#define OMAP3_SYSCON_BASE (0x48000000 + 0x2000 + 0x270)
+#define AM625_EFUSE_K_MPU_OPP 11
+#define AM625_EFUSE_S_MPU_OPP 19
+#define AM625_EFUSE_T_MPU_OPP 20
+
+#define AM625_SUPPORT_K_MPU_OPP BIT(0)
+#define AM625_SUPPORT_S_MPU_OPP BIT(1)
+#define AM625_SUPPORT_T_MPU_OPP BIT(2)
+
#define VERSION_COUNT 2
struct ti_cpufreq_data;
@@ -104,6 +112,25 @@ static unsigned long omap3_efuse_xlate(struct ti_cpufreq_data *opp_data,
return BIT(efuse);
}
+static unsigned long am625_efuse_xlate(struct ti_cpufreq_data *opp_data,
+ unsigned long efuse)
+{
+ unsigned long calculated_efuse = AM625_SUPPORT_K_MPU_OPP;
+
+ switch (efuse) {
+ case AM625_EFUSE_T_MPU_OPP:
+ calculated_efuse |= AM625_SUPPORT_T_MPU_OPP;
+ fallthrough;
+ case AM625_EFUSE_S_MPU_OPP:
+ calculated_efuse |= AM625_SUPPORT_S_MPU_OPP;
+ fallthrough;
+ case AM625_EFUSE_K_MPU_OPP:
+ calculated_efuse |= AM625_SUPPORT_K_MPU_OPP;
+ }
+
+ return calculated_efuse;
+}
+
static struct ti_cpufreq_soc_data am3x_soc_data = {
.efuse_xlate = amx3_efuse_xlate,
.efuse_fallback = AM33XX_800M_ARM_MPU_MAX_FREQ,
@@ -198,6 +225,14 @@ static struct ti_cpufreq_soc_data am3517_soc_data = {
.multi_regulator = false,
};
+static struct ti_cpufreq_soc_data am625_soc_data = {
+ .efuse_xlate = am625_efuse_xlate,
+ .efuse_offset = 0x0018,
+ .efuse_mask = 0x07c0,
+ .efuse_shift = 0x6,
+ .rev_offset = 0x0014,
+ .multi_regulator = false,
+};
/**
* ti_cpufreq_get_efuse() - Parse and return efuse value present on SoC
@@ -301,6 +336,7 @@ static const struct of_device_id ti_cpufreq_of_match[] = {
{ .compatible = "ti,dra7", .data = &dra7_soc_data },
{ .compatible = "ti,omap34xx", .data = &omap34xx_soc_data, },
{ .compatible = "ti,omap36xx", .data = &omap36xx_soc_data, },
+ { .compatible = "ti,am625", .data = &am625_soc_data, },
/* legacy */
{ .compatible = "ti,omap3430", .data = &omap34xx_soc_data, },
{ .compatible = "ti,omap3630", .data = &omap36xx_soc_data, },
--
2.34.1
On 01-11-22, 13:09, Vibhore Vardhan wrote:
> Apologies, resending because I botched the label in previous series.
> Please reply to this series rather than the one sent previously.
>
> Hi,
> This series enables CPUFreq for AM625. This version is a fixup and
> rebase of the patch series by Dave Gerlach on v6.1-rc3 [1].
>
> It updates the ti-cpufreq driver to support parsing of the speed grade
> value out of the JTAG_USER_ID register and adds necessary support code
> to use cpufreq-dt.
>
> The operating-points table that gets added support 200,400,600,800 for
> all variants and then 1GHz for the S Speed grade only and 1.25 for the T
> Speed grade only. 1.4GHz has been added in board specific dts file as it
> requires VDD_CORE to be at 0.85V.
>
> The latency between pre and post frequency transition was measured in
> CPUFreq driver for all combinations of OPP changes. The average value
> was selected as overall clock-latency.
>
> Tested on am62-sk board using manual frequency changes and then reading
> back frequency with k3conf, and this shows matching frequency to what
> was set.
>
> This should not impact existing K3 platforms that do not have operating
> points table defined.
Applied. Thanks.
--
viresh