2022-11-13 18:48:36

by Dario Binacchi

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Subject: [PATCH 0/5] clk: imx8mn: miscellaneous cleanups and bug fixes

This series has been tested on the BSH SystemMaster (SMM) S2 board.


Dario Binacchi (5):
clk: imx8mn: rename vpu_pll to m7_alt_pll
clk: imx: replace osc_hdmi with dummy
clk: imx: rename video_pll1 to video_pll
clk: imx8mn: fix imx8mn_sai2_sels clocks list
clk: imx8mn: fix imx8mn_enet_phy_sels clocks list

drivers/clk/imx/clk-imx8mn.c | 116 +++++++++++------------
include/dt-bindings/clock/imx8mn-clock.h | 16 ++--
2 files changed, 66 insertions(+), 66 deletions(-)

--
2.32.0



2022-11-13 18:48:38

by Dario Binacchi

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Subject: [PATCH 5/5] clk: imx8mn: fix imx8mn_enet_phy_sels clocks list

According to the "Clock Root" table of the reference manual (document
IMX8MNRM Rev 2, 07/2022):

Clock Root offset Source Select (CCM_TARGET_ROOTn[MUX])
... ... ...
ENET_PHY_REF_CLK_ROOT 0xAA80 000 - 24M_REF_CLK
001 - SYSTEM_PLL2_DIV20
010 - SYSTEM_PLL2_DIV8
011 - SYSTEM_PLL2_DIV5
100 - SYSTEM_PLL2_DIV2
101 - AUDIO_PLL1_CLK
110 - VIDEO_PLL_CLK
111 - AUDIO_PLL2_CLK
... ... ...

while the imx8mn_enet_phy_sels list didn't contained audio_pll1_out for
source select bits 101b.

Fixes: 96d6392b54dbb ("clk: imx: Add support for i.MX8MN clock driver")
Signed-off-by: Dario Binacchi <[email protected]>

---

drivers/clk/imx/clk-imx8mn.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index 37128c35198d..2afea905f7f3 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -140,8 +140,8 @@ static const char * const imx8mn_enet_timer_sels[] = {"osc_24m", "sys_pll2_100m"
"clk_ext4", "video_pll_out", };

static const char * const imx8mn_enet_phy_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll2_125m",
- "sys_pll2_200m", "sys_pll2_500m", "video_pll_out",
- "audio_pll2_out", };
+ "sys_pll2_200m", "sys_pll2_500m", "audio_pll1_out",
+ "video_pll_out", "audio_pll2_out", };

static const char * const imx8mn_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out",
"sys_pll1_400m", "audio_pll2_out", "sys_pll3_out",
--
2.32.0


2022-11-13 18:48:45

by Dario Binacchi

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Subject: [PATCH 4/5] clk: imx8mn: fix imx8mn_sai2_sels clocks list

According to the "Clock Root" table of the reference manual (document
IMX8MNRM Rev 2, 07/2022):

Clock Root offset Source Select (CCM_TARGET_ROOTn[MUX])
... ... ...
SAI2_CLK_ROOT 0xA600 000 - 24M_REF_CLK
001 - AUDIO_PLL1_CLK
010 - AUDIO_PLL2_CLK
011 - VIDEO_PLL_CLK
100 - SYSTEM_PLL1_DIV6
110 - EXT_CLK_2
111 - EXT_CLK_3
... ... ...

while the imx8mn_sai2_sels list contained clk_ext3 and clk_ext4 for
source select bits 110b and 111b.

Fixes: 96d6392b54dbb ("clk: imx: Add support for i.MX8MN clock driver")
Signed-off-by: Dario Binacchi <[email protected]>
---

drivers/clk/imx/clk-imx8mn.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index b80af5d1ef46..37128c35198d 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -109,7 +109,7 @@ static const char * const imx8mn_disp_pixel_sels[] = {"osc_24m", "video_pll_out"

static const char * const imx8mn_sai2_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
"video_pll_out", "sys_pll1_133m", "dummy",
- "clk_ext3", "clk_ext4", };
+ "clk_ext2", "clk_ext3", };

static const char * const imx8mn_sai3_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
"video_pll_out", "sys_pll1_133m", "dummy",
--
2.32.0


2022-11-13 20:05:12

by Dario Binacchi

[permalink] [raw]
Subject: [PATCH 3/5] clk: imx: rename video_pll1 to video_pll

Unlike audio_pll1 and audio_pll2, there is no video_pll2. Further, the
name used in the RM is video_pll. So, let's rename "video_pll1" to
"video_pll" to be consistent with the RM and avoid misunderstandings.

No functional changes intended.

Signed-off-by: Dario Binacchi <[email protected]>
---

drivers/clk/imx/clk-imx8mn.c | 96 ++++++++++++------------
include/dt-bindings/clock/imx8mn-clock.h | 8 +-
2 files changed, 52 insertions(+), 52 deletions(-)

diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index 0fae97e61e2c..b80af5d1ef46 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -27,7 +27,7 @@ static u32 share_count_nand;
static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", };
static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", };
static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", };
-static const char * const video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", };
+static const char * const video_pll_bypass_sels[] = {"video_pll", "video_pll_ref_sel", };
static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
static const char * const m7_alt_pll_bypass_sels[] = {"m7_alt_pll", "m7_alt_pll_ref_sel", };
@@ -41,23 +41,23 @@ static const char * const imx8mn_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pl
static const char * const imx8mn_a53_core_sels[] = {"arm_a53_div", "arm_pll_out", };

static const char * const imx8mn_m7_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_250m", "m7_alt_pll_out",
- "sys_pll1_800m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", };
+ "sys_pll1_800m", "audio_pll1_out", "video_pll_out", "sys_pll3_out", };

static const char * const imx8mn_gpu_core_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m",
"sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
- "video_pll1_out", "audio_pll2_out", };
+ "video_pll_out", "audio_pll2_out", };

static const char * const imx8mn_gpu_shader_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m",
"sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
- "video_pll1_out", "audio_pll2_out", };
+ "video_pll_out", "audio_pll2_out", };

static const char * const imx8mn_main_axi_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll1_800m",
"sys_pll2_250m", "sys_pll2_1000m", "audio_pll1_out",
- "video_pll1_out", "sys_pll1_100m",};
+ "video_pll_out", "sys_pll1_100m",};

static const char * const imx8mn_enet_axi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m",
"sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out",
- "video_pll1_out", "sys_pll3_out", };
+ "video_pll_out", "sys_pll3_out", };

static const char * const imx8mn_nand_usdhc_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m",
"sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out",
@@ -77,23 +77,23 @@ static const char * const imx8mn_usb_bus_sels[] = {"osc_24m", "sys_pll2_500m", "

static const char * const imx8mn_gpu_axi_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out",
"sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
- "video_pll1_out", "audio_pll2_out", };
+ "video_pll_out", "audio_pll2_out", };

static const char * const imx8mn_gpu_ahb_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out",
"sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
- "video_pll1_out", "audio_pll2_out", };
+ "video_pll_out", "audio_pll2_out", };

static const char * const imx8mn_noc_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll3_out",
"sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out",
- "video_pll1_out", "audio_pll2_out", };
+ "video_pll_out", "audio_pll2_out", };

static const char * const imx8mn_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m",
"sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out",
- "audio_pll1_out", "video_pll1_out", };
+ "audio_pll1_out", "video_pll_out", };

static const char * const imx8mn_audio_ahb_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m",
"sys_pll2_1000m", "sys_pll2_166m", "sys_pll3_out",
- "audio_pll1_out", "video_pll1_out", };
+ "audio_pll1_out", "video_pll_out", };

static const char * const imx8mn_dram_alt_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll1_100m",
"sys_pll2_500m", "sys_pll2_1000m", "sys_pll3_out",
@@ -103,49 +103,49 @@ static const char * const imx8mn_dram_apb_sels[] = {"osc_24m", "sys_pll2_200m",
"sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
"sys_pll2_250m", "audio_pll2_out", };

-static const char * const imx8mn_disp_pixel_sels[] = {"osc_24m", "video_pll1_out", "audio_pll2_out",
+static const char * const imx8mn_disp_pixel_sels[] = {"osc_24m", "video_pll_out", "audio_pll2_out",
"audio_pll1_out", "sys_pll1_800m", "sys_pll2_1000m",
"sys_pll3_out", "clk_ext4", };

static const char * const imx8mn_sai2_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
- "video_pll1_out", "sys_pll1_133m", "dummy",
+ "video_pll_out", "sys_pll1_133m", "dummy",
"clk_ext3", "clk_ext4", };

static const char * const imx8mn_sai3_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
- "video_pll1_out", "sys_pll1_133m", "dummy",
+ "video_pll_out", "sys_pll1_133m", "dummy",
"clk_ext3", "clk_ext4", };

static const char * const imx8mn_sai5_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
- "video_pll1_out", "sys_pll1_133m", "dummy",
+ "video_pll_out", "sys_pll1_133m", "dummy",
"clk_ext2", "clk_ext3", };

static const char * const imx8mn_sai6_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
- "video_pll1_out", "sys_pll1_133m", "dummy",
+ "video_pll_out", "sys_pll1_133m", "dummy",
"clk_ext3", "clk_ext4", };

static const char * const imx8mn_sai7_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
- "video_pll1_out", "sys_pll1_133m", "dummy",
+ "video_pll_out", "sys_pll1_133m", "dummy",
"clk_ext3", "clk_ext4", };

static const char * const imx8mn_spdif1_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
- "video_pll1_out", "sys_pll1_133m", "dummy",
+ "video_pll_out", "sys_pll1_133m", "dummy",
"clk_ext2", "clk_ext3", };

static const char * const imx8mn_enet_ref_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m",
"sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out",
- "video_pll1_out", "clk_ext4", };
+ "video_pll_out", "clk_ext4", };

static const char * const imx8mn_enet_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out",
"clk_ext1", "clk_ext2", "clk_ext3",
- "clk_ext4", "video_pll1_out", };
+ "clk_ext4", "video_pll_out", };

static const char * const imx8mn_enet_phy_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll2_125m",
- "sys_pll2_200m", "sys_pll2_500m", "video_pll1_out",
+ "sys_pll2_200m", "sys_pll2_500m", "video_pll_out",
"audio_pll2_out", };

static const char * const imx8mn_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out",
"sys_pll1_400m", "audio_pll2_out", "sys_pll3_out",
- "sys_pll2_250m", "video_pll1_out", };
+ "sys_pll2_250m", "video_pll_out", };

static const char * const imx8mn_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll2_333m",
"sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m",
@@ -160,19 +160,19 @@ static const char * const imx8mn_usdhc2_sels[] = {"osc_24m", "sys_pll1_400m", "s
"audio_pll2_out", "sys_pll1_100m", };

static const char * const imx8mn_i2c1_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
- "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
+ "sys_pll3_out", "audio_pll1_out", "video_pll_out",
"audio_pll2_out", "sys_pll1_133m", };

static const char * const imx8mn_i2c2_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
- "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
+ "sys_pll3_out", "audio_pll1_out", "video_pll_out",
"audio_pll2_out", "sys_pll1_133m", };

static const char * const imx8mn_i2c3_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
- "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
+ "sys_pll3_out", "audio_pll1_out", "video_pll_out",
"audio_pll2_out", "sys_pll1_133m", };

static const char * const imx8mn_i2c4_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
- "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
+ "sys_pll3_out", "audio_pll1_out", "video_pll_out",
"audio_pll2_out", "sys_pll1_133m", };

static const char * const imx8mn_uart1_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
@@ -213,42 +213,42 @@ static const char * const imx8mn_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "s

static const char * const imx8mn_pwm1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
"sys_pll1_40m", "sys_pll3_out", "clk_ext1",
- "sys_pll1_80m", "video_pll1_out", };
+ "sys_pll1_80m", "video_pll_out", };

static const char * const imx8mn_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
"sys_pll1_40m", "sys_pll3_out", "clk_ext1",
- "sys_pll1_80m", "video_pll1_out", };
+ "sys_pll1_80m", "video_pll_out", };

static const char * const imx8mn_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
"sys_pll1_40m", "sys_pll3_out", "clk_ext2",
- "sys_pll1_80m", "video_pll1_out", };
+ "sys_pll1_80m", "video_pll_out", };

static const char * const imx8mn_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
"sys_pll1_40m", "sys_pll3_out", "clk_ext2",
- "sys_pll1_80m", "video_pll1_out", };
+ "sys_pll1_80m", "video_pll_out", };

static const char * const imx8mn_gpt1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
- "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
+ "sys_pll1_40m", "video_pll_out", "sys_pll1_80m",
"audio_pll1_out", "clk_ext1", };

static const char * const imx8mn_gpt2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
- "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
+ "sys_pll1_40m", "video_pll_out", "sys_pll1_80m",
"audio_pll1_out", "clk_ext1", };

static const char * const imx8mn_gpt3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
- "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
+ "sys_pll1_40m", "video_pll_out", "sys_pll1_80m",
"audio_pll1_out", "clk_ext1", };

static const char * const imx8mn_gpt4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
- "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
+ "sys_pll1_40m", "video_pll_out", "sys_pll1_80m",
"audio_pll1_out", "clk_ext1", };

static const char * const imx8mn_gpt5_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
- "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
+ "sys_pll1_40m", "video_pll_out", "sys_pll1_80m",
"audio_pll1_out", "clk_ext1", };

static const char * const imx8mn_gpt6_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
- "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
+ "sys_pll1_40m", "video_pll_out", "sys_pll1_80m",
"audio_pll1_out", "clk_ext1", };

static const char * const imx8mn_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m",
@@ -261,15 +261,15 @@ static const char * const imx8mn_wrclk_sels[] = {"osc_24m", "sys_pll1_40m", "m7_

static const char * const imx8mn_dsi_core_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m",
"sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
- "audio_pll2_out", "video_pll1_out", };
+ "audio_pll2_out", "video_pll_out", };

static const char * const imx8mn_dsi_phy_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_100m",
"sys_pll1_800m", "sys_pll2_1000m", "clk_ext2",
- "audio_pll2_out", "video_pll1_out", };
+ "audio_pll2_out", "video_pll_out", };

static const char * const imx8mn_dsi_dbi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_100m",
"sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
- "audio_pll2_out", "video_pll1_out", };
+ "audio_pll2_out", "video_pll_out", };

static const char * const imx8mn_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
"sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
@@ -277,15 +277,15 @@ static const char * const imx8mn_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "s

static const char * const imx8mn_camera_pixel_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m",
"sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
- "audio_pll2_out", "video_pll1_out", };
+ "audio_pll2_out", "video_pll_out", };

static const char * const imx8mn_csi1_phy_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m",
"sys_pll1_800m", "sys_pll2_1000m", "clk_ext2",
- "audio_pll2_out", "video_pll1_out", };
+ "audio_pll2_out", "video_pll_out", };

static const char * const imx8mn_csi2_phy_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m",
"sys_pll1_800m", "sys_pll2_1000m", "clk_ext2",
- "audio_pll2_out", "video_pll1_out", };
+ "audio_pll2_out", "video_pll_out", };

static const char * const imx8mn_csi2_esc_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_80m",
"sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
@@ -306,9 +306,9 @@ static const char * const imx8mn_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "du
"dummy", "sys_pll1_80m", };
static const char * const imx8mn_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_400m",
"sys_pll2_166m", "sys_pll3_out", "audio_pll1_out",
- "video_pll1_out", "osc_32k", };
+ "video_pll_out", "osc_32k", };

-static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll1_out",
+static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll_out",
"dummy", "dummy", "gpu_pll_out", "dummy",
"arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3",
"dummy", "dummy", "osc_24m", "dummy", "osc_32k"};
@@ -349,7 +349,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)

hws[IMX8MN_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
hws[IMX8MN_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
- hws[IMX8MN_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ hws[IMX8MN_VIDEO_PLL_REF_SEL] = imx_clk_hw_mux("video_pll_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
hws[IMX8MN_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
hws[IMX8MN_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
hws[IMX8MN_M7_ALT_PLL_REF_SEL] = imx_clk_hw_mux("m7_alt_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
@@ -358,7 +358,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)

hws[IMX8MN_AUDIO_PLL1] = imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_ref_sel", base, &imx_1443x_pll);
hws[IMX8MN_AUDIO_PLL2] = imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_ref_sel", base + 0x14, &imx_1443x_pll);
- hws[IMX8MN_VIDEO_PLL1] = imx_clk_hw_pll14xx("video_pll1", "video_pll1_ref_sel", base + 0x28, &imx_1443x_pll);
+ hws[IMX8MN_VIDEO_PLL] = imx_clk_hw_pll14xx("video_pll", "video_pll_ref_sel", base + 0x28, &imx_1443x_pll);
hws[IMX8MN_DRAM_PLL] = imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx_1443x_dram_pll);
hws[IMX8MN_GPU_PLL] = imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, &imx_1416x_pll);
hws[IMX8MN_M7_ALT_PLL] = imx_clk_hw_pll14xx("m7_alt_pll", "m7_alt_pll_ref_sel", base + 0x74, &imx_1416x_pll);
@@ -370,7 +370,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
/* PLL bypass out */
hws[IMX8MN_AUDIO_PLL1_BYPASS] = imx_clk_hw_mux_flags("audio_pll1_bypass", base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT);
hws[IMX8MN_AUDIO_PLL2_BYPASS] = imx_clk_hw_mux_flags("audio_pll2_bypass", base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT);
- hws[IMX8MN_VIDEO_PLL1_BYPASS] = imx_clk_hw_mux_flags("video_pll1_bypass", base + 0x28, 16, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels), CLK_SET_RATE_PARENT);
+ hws[IMX8MN_VIDEO_PLL_BYPASS] = imx_clk_hw_mux_flags("video_pll_bypass", base + 0x28, 16, 1, video_pll_bypass_sels, ARRAY_SIZE(video_pll_bypass_sels), CLK_SET_RATE_PARENT);
hws[IMX8MN_DRAM_PLL_BYPASS] = imx_clk_hw_mux_flags("dram_pll_bypass", base + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT);
hws[IMX8MN_GPU_PLL_BYPASS] = imx_clk_hw_mux_flags("gpu_pll_bypass", base + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
hws[IMX8MN_M7_ALT_PLL_BYPASS] = imx_clk_hw_mux_flags("m7_alt_pll_bypass", base + 0x74, 28, 1, m7_alt_pll_bypass_sels, ARRAY_SIZE(m7_alt_pll_bypass_sels), CLK_SET_RATE_PARENT);
@@ -380,7 +380,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
/* PLL out gate */
hws[IMX8MN_AUDIO_PLL1_OUT] = imx_clk_hw_gate("audio_pll1_out", "audio_pll1_bypass", base, 13);
hws[IMX8MN_AUDIO_PLL2_OUT] = imx_clk_hw_gate("audio_pll2_out", "audio_pll2_bypass", base + 0x14, 13);
- hws[IMX8MN_VIDEO_PLL1_OUT] = imx_clk_hw_gate("video_pll1_out", "video_pll1_bypass", base + 0x28, 13);
+ hws[IMX8MN_VIDEO_PLL_OUT] = imx_clk_hw_gate("video_pll_out", "video_pll_bypass", base + 0x28, 13);
hws[IMX8MN_DRAM_PLL_OUT] = imx_clk_hw_gate("dram_pll_out", "dram_pll_bypass", base + 0x50, 13);
hws[IMX8MN_GPU_PLL_OUT] = imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x64, 11);
hws[IMX8MN_M7_ALT_PLL_OUT] = imx_clk_hw_gate("m7_alt_pll_out", "m7_alt_pll_bypass", base + 0x74, 11);
diff --git a/include/dt-bindings/clock/imx8mn-clock.h b/include/dt-bindings/clock/imx8mn-clock.h
index f103b008a12a..5ab6916e444f 100644
--- a/include/dt-bindings/clock/imx8mn-clock.h
+++ b/include/dt-bindings/clock/imx8mn-clock.h
@@ -16,7 +16,7 @@
#define IMX8MN_CLK_EXT4 7
#define IMX8MN_AUDIO_PLL1_REF_SEL 8
#define IMX8MN_AUDIO_PLL2_REF_SEL 9
-#define IMX8MN_VIDEO_PLL1_REF_SEL 10
+#define IMX8MN_VIDEO_PLL_REF_SEL 10
#define IMX8MN_DRAM_PLL_REF_SEL 11
#define IMX8MN_GPU_PLL_REF_SEL 12
#define IMX8MN_M7_ALT_PLL_REF_SEL 13
@@ -26,7 +26,7 @@
#define IMX8MN_SYS_PLL3_REF_SEL 17
#define IMX8MN_AUDIO_PLL1 18
#define IMX8MN_AUDIO_PLL2 19
-#define IMX8MN_VIDEO_PLL1 20
+#define IMX8MN_VIDEO_PLL 20
#define IMX8MN_DRAM_PLL 21
#define IMX8MN_GPU_PLL 22
#define IMX8MN_M7_ALT_PLL 23
@@ -36,7 +36,7 @@
#define IMX8MN_SYS_PLL3 27
#define IMX8MN_AUDIO_PLL1_BYPASS 28
#define IMX8MN_AUDIO_PLL2_BYPASS 29
-#define IMX8MN_VIDEO_PLL1_BYPASS 30
+#define IMX8MN_VIDEO_PLL_BYPASS 30
#define IMX8MN_DRAM_PLL_BYPASS 31
#define IMX8MN_GPU_PLL_BYPASS 32
#define IMX8MN_M7_ALT_PLL_BYPASS 33
@@ -46,7 +46,7 @@
#define IMX8MN_SYS_PLL3_BYPASS 37
#define IMX8MN_AUDIO_PLL1_OUT 38
#define IMX8MN_AUDIO_PLL2_OUT 39
-#define IMX8MN_VIDEO_PLL1_OUT 40
+#define IMX8MN_VIDEO_PLL_OUT 40
#define IMX8MN_DRAM_PLL_OUT 41
#define IMX8MN_GPU_PLL_OUT 42
#define IMX8MN_M7_ALT_PLL_OUT 43
--
2.32.0


2022-11-14 08:58:55

by Marco Felsch

[permalink] [raw]
Subject: Re: [PATCH 0/5] clk: imx8mn: miscellaneous cleanups and bug fixes

Hi Dario,

On 22-11-13, Dario Binacchi wrote:
> This series has been tested on the BSH SystemMaster (SMM) S2 board.

the series LGTM, except for the two patches I commented. Also I think
that all patches can contain the Fixes tag.

Regards,
Marco

>
> Dario Binacchi (5):
> clk: imx8mn: rename vpu_pll to m7_alt_pll
> clk: imx: replace osc_hdmi with dummy
> clk: imx: rename video_pll1 to video_pll
> clk: imx8mn: fix imx8mn_sai2_sels clocks list
> clk: imx8mn: fix imx8mn_enet_phy_sels clocks list
>
> drivers/clk/imx/clk-imx8mn.c | 116 +++++++++++------------
> include/dt-bindings/clock/imx8mn-clock.h | 16 ++--
> 2 files changed, 66 insertions(+), 66 deletions(-)
>
> --
> 2.32.0
>
>
>

2022-11-14 08:59:18

by Marco Felsch

[permalink] [raw]
Subject: Re: [PATCH 3/5] clk: imx: rename video_pll1 to video_pll

Hi Dario,

On 22-11-13, Dario Binacchi wrote:
> Unlike audio_pll1 and audio_pll2, there is no video_pll2. Further, the
> name used in the RM is video_pll. So, let's rename "video_pll1" to
> "video_pll" to be consistent with the RM and avoid misunderstandings.
>
> No functional changes intended.
>
> Signed-off-by: Dario Binacchi <[email protected]>
> ---
>
> drivers/clk/imx/clk-imx8mn.c | 96 ++++++++++++------------
> include/dt-bindings/clock/imx8mn-clock.h | 8 +-
> 2 files changed, 52 insertions(+), 52 deletions(-)
>
> diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
> index 0fae97e61e2c..b80af5d1ef46 100644
> --- a/drivers/clk/imx/clk-imx8mn.c
> +++ b/drivers/clk/imx/clk-imx8mn.c
> @@ -27,7 +27,7 @@ static u32 share_count_nand;
> static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", };
> static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", };
> static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", };
> -static const char * const video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", };
> +static const char * const video_pll_bypass_sels[] = {"video_pll", "video_pll_ref_sel", };
> static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
> static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
> static const char * const m7_alt_pll_bypass_sels[] = {"m7_alt_pll", "m7_alt_pll_ref_sel", };
> @@ -41,23 +41,23 @@ static const char * const imx8mn_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pl
> static const char * const imx8mn_a53_core_sels[] = {"arm_a53_div", "arm_pll_out", };
>
> static const char * const imx8mn_m7_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_250m", "m7_alt_pll_out",
> - "sys_pll1_800m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", };
> + "sys_pll1_800m", "audio_pll1_out", "video_pll_out", "sys_pll3_out", };
>
> static const char * const imx8mn_gpu_core_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m",
> "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
> - "video_pll1_out", "audio_pll2_out", };
> + "video_pll_out", "audio_pll2_out", };
>
> static const char * const imx8mn_gpu_shader_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m",
> "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
> - "video_pll1_out", "audio_pll2_out", };
> + "video_pll_out", "audio_pll2_out", };
>
> static const char * const imx8mn_main_axi_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll1_800m",
> "sys_pll2_250m", "sys_pll2_1000m", "audio_pll1_out",
> - "video_pll1_out", "sys_pll1_100m",};
> + "video_pll_out", "sys_pll1_100m",};
>
> static const char * const imx8mn_enet_axi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m",
> "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out",
> - "video_pll1_out", "sys_pll3_out", };
> + "video_pll_out", "sys_pll3_out", };
>
> static const char * const imx8mn_nand_usdhc_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m",
> "sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out",
> @@ -77,23 +77,23 @@ static const char * const imx8mn_usb_bus_sels[] = {"osc_24m", "sys_pll2_500m", "
>
> static const char * const imx8mn_gpu_axi_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out",
> "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
> - "video_pll1_out", "audio_pll2_out", };
> + "video_pll_out", "audio_pll2_out", };
>
> static const char * const imx8mn_gpu_ahb_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out",
> "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
> - "video_pll1_out", "audio_pll2_out", };
> + "video_pll_out", "audio_pll2_out", };
>
> static const char * const imx8mn_noc_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll3_out",
> "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out",
> - "video_pll1_out", "audio_pll2_out", };
> + "video_pll_out", "audio_pll2_out", };
>
> static const char * const imx8mn_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m",
> "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out",
> - "audio_pll1_out", "video_pll1_out", };
> + "audio_pll1_out", "video_pll_out", };
>
> static const char * const imx8mn_audio_ahb_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m",
> "sys_pll2_1000m", "sys_pll2_166m", "sys_pll3_out",
> - "audio_pll1_out", "video_pll1_out", };
> + "audio_pll1_out", "video_pll_out", };
>
> static const char * const imx8mn_dram_alt_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll1_100m",
> "sys_pll2_500m", "sys_pll2_1000m", "sys_pll3_out",
> @@ -103,49 +103,49 @@ static const char * const imx8mn_dram_apb_sels[] = {"osc_24m", "sys_pll2_200m",
> "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
> "sys_pll2_250m", "audio_pll2_out", };
>
> -static const char * const imx8mn_disp_pixel_sels[] = {"osc_24m", "video_pll1_out", "audio_pll2_out",
> +static const char * const imx8mn_disp_pixel_sels[] = {"osc_24m", "video_pll_out", "audio_pll2_out",
> "audio_pll1_out", "sys_pll1_800m", "sys_pll2_1000m",
> "sys_pll3_out", "clk_ext4", };
>
> static const char * const imx8mn_sai2_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
> - "video_pll1_out", "sys_pll1_133m", "dummy",
> + "video_pll_out", "sys_pll1_133m", "dummy",
> "clk_ext3", "clk_ext4", };
>
> static const char * const imx8mn_sai3_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
> - "video_pll1_out", "sys_pll1_133m", "dummy",
> + "video_pll_out", "sys_pll1_133m", "dummy",
> "clk_ext3", "clk_ext4", };
>
> static const char * const imx8mn_sai5_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
> - "video_pll1_out", "sys_pll1_133m", "dummy",
> + "video_pll_out", "sys_pll1_133m", "dummy",
> "clk_ext2", "clk_ext3", };
>
> static const char * const imx8mn_sai6_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
> - "video_pll1_out", "sys_pll1_133m", "dummy",
> + "video_pll_out", "sys_pll1_133m", "dummy",
> "clk_ext3", "clk_ext4", };
>
> static const char * const imx8mn_sai7_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
> - "video_pll1_out", "sys_pll1_133m", "dummy",
> + "video_pll_out", "sys_pll1_133m", "dummy",
> "clk_ext3", "clk_ext4", };
>
> static const char * const imx8mn_spdif1_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
> - "video_pll1_out", "sys_pll1_133m", "dummy",
> + "video_pll_out", "sys_pll1_133m", "dummy",
> "clk_ext2", "clk_ext3", };
>
> static const char * const imx8mn_enet_ref_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m",
> "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out",
> - "video_pll1_out", "clk_ext4", };
> + "video_pll_out", "clk_ext4", };
>
> static const char * const imx8mn_enet_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out",
> "clk_ext1", "clk_ext2", "clk_ext3",
> - "clk_ext4", "video_pll1_out", };
> + "clk_ext4", "video_pll_out", };
>
> static const char * const imx8mn_enet_phy_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll2_125m",
> - "sys_pll2_200m", "sys_pll2_500m", "video_pll1_out",
> + "sys_pll2_200m", "sys_pll2_500m", "video_pll_out",
> "audio_pll2_out", };
>
> static const char * const imx8mn_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out",
> "sys_pll1_400m", "audio_pll2_out", "sys_pll3_out",
> - "sys_pll2_250m", "video_pll1_out", };
> + "sys_pll2_250m", "video_pll_out", };
>
> static const char * const imx8mn_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll2_333m",
> "sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m",
> @@ -160,19 +160,19 @@ static const char * const imx8mn_usdhc2_sels[] = {"osc_24m", "sys_pll1_400m", "s
> "audio_pll2_out", "sys_pll1_100m", };
>
> static const char * const imx8mn_i2c1_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
> - "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
> + "sys_pll3_out", "audio_pll1_out", "video_pll_out",
> "audio_pll2_out", "sys_pll1_133m", };
>
> static const char * const imx8mn_i2c2_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
> - "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
> + "sys_pll3_out", "audio_pll1_out", "video_pll_out",
> "audio_pll2_out", "sys_pll1_133m", };
>
> static const char * const imx8mn_i2c3_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
> - "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
> + "sys_pll3_out", "audio_pll1_out", "video_pll_out",
> "audio_pll2_out", "sys_pll1_133m", };
>
> static const char * const imx8mn_i2c4_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
> - "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
> + "sys_pll3_out", "audio_pll1_out", "video_pll_out",
> "audio_pll2_out", "sys_pll1_133m", };
>
> static const char * const imx8mn_uart1_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
> @@ -213,42 +213,42 @@ static const char * const imx8mn_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "s
>
> static const char * const imx8mn_pwm1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
> "sys_pll1_40m", "sys_pll3_out", "clk_ext1",
> - "sys_pll1_80m", "video_pll1_out", };
> + "sys_pll1_80m", "video_pll_out", };
>
> static const char * const imx8mn_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
> "sys_pll1_40m", "sys_pll3_out", "clk_ext1",
> - "sys_pll1_80m", "video_pll1_out", };
> + "sys_pll1_80m", "video_pll_out", };
>
> static const char * const imx8mn_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
> "sys_pll1_40m", "sys_pll3_out", "clk_ext2",
> - "sys_pll1_80m", "video_pll1_out", };
> + "sys_pll1_80m", "video_pll_out", };
>
> static const char * const imx8mn_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
> "sys_pll1_40m", "sys_pll3_out", "clk_ext2",
> - "sys_pll1_80m", "video_pll1_out", };
> + "sys_pll1_80m", "video_pll_out", };
>
> static const char * const imx8mn_gpt1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
> - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
> + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m",
> "audio_pll1_out", "clk_ext1", };
>
> static const char * const imx8mn_gpt2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
> - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
> + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m",
> "audio_pll1_out", "clk_ext1", };
>
> static const char * const imx8mn_gpt3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
> - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
> + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m",
> "audio_pll1_out", "clk_ext1", };
>
> static const char * const imx8mn_gpt4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
> - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
> + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m",
> "audio_pll1_out", "clk_ext1", };
>
> static const char * const imx8mn_gpt5_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
> - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
> + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m",
> "audio_pll1_out", "clk_ext1", };
>
> static const char * const imx8mn_gpt6_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
> - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
> + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m",
> "audio_pll1_out", "clk_ext1", };
>
> static const char * const imx8mn_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m",
> @@ -261,15 +261,15 @@ static const char * const imx8mn_wrclk_sels[] = {"osc_24m", "sys_pll1_40m", "m7_
>
> static const char * const imx8mn_dsi_core_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m",
> "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
> - "audio_pll2_out", "video_pll1_out", };
> + "audio_pll2_out", "video_pll_out", };
>
> static const char * const imx8mn_dsi_phy_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_100m",
> "sys_pll1_800m", "sys_pll2_1000m", "clk_ext2",
> - "audio_pll2_out", "video_pll1_out", };
> + "audio_pll2_out", "video_pll_out", };
>
> static const char * const imx8mn_dsi_dbi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_100m",
> "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
> - "audio_pll2_out", "video_pll1_out", };
> + "audio_pll2_out", "video_pll_out", };
>
> static const char * const imx8mn_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
> "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
> @@ -277,15 +277,15 @@ static const char * const imx8mn_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "s
>
> static const char * const imx8mn_camera_pixel_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m",
> "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
> - "audio_pll2_out", "video_pll1_out", };
> + "audio_pll2_out", "video_pll_out", };
>
> static const char * const imx8mn_csi1_phy_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m",
> "sys_pll1_800m", "sys_pll2_1000m", "clk_ext2",
> - "audio_pll2_out", "video_pll1_out", };
> + "audio_pll2_out", "video_pll_out", };
>
> static const char * const imx8mn_csi2_phy_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m",
> "sys_pll1_800m", "sys_pll2_1000m", "clk_ext2",
> - "audio_pll2_out", "video_pll1_out", };
> + "audio_pll2_out", "video_pll_out", };
>
> static const char * const imx8mn_csi2_esc_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_80m",
> "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
> @@ -306,9 +306,9 @@ static const char * const imx8mn_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "du
> "dummy", "sys_pll1_80m", };
> static const char * const imx8mn_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_400m",
> "sys_pll2_166m", "sys_pll3_out", "audio_pll1_out",
> - "video_pll1_out", "osc_32k", };
> + "video_pll_out", "osc_32k", };
>
> -static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll1_out",
> +static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll_out",
> "dummy", "dummy", "gpu_pll_out", "dummy",
> "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3",
> "dummy", "dummy", "osc_24m", "dummy", "osc_32k"};
> @@ -349,7 +349,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
>
> hws[IMX8MN_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
> hws[IMX8MN_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
> - hws[IMX8MN_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
> + hws[IMX8MN_VIDEO_PLL_REF_SEL] = imx_clk_hw_mux("video_pll_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
> hws[IMX8MN_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
> hws[IMX8MN_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
> hws[IMX8MN_M7_ALT_PLL_REF_SEL] = imx_clk_hw_mux("m7_alt_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
> @@ -358,7 +358,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
>
> hws[IMX8MN_AUDIO_PLL1] = imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_ref_sel", base, &imx_1443x_pll);
> hws[IMX8MN_AUDIO_PLL2] = imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_ref_sel", base + 0x14, &imx_1443x_pll);
> - hws[IMX8MN_VIDEO_PLL1] = imx_clk_hw_pll14xx("video_pll1", "video_pll1_ref_sel", base + 0x28, &imx_1443x_pll);
> + hws[IMX8MN_VIDEO_PLL] = imx_clk_hw_pll14xx("video_pll", "video_pll_ref_sel", base + 0x28, &imx_1443x_pll);
> hws[IMX8MN_DRAM_PLL] = imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx_1443x_dram_pll);
> hws[IMX8MN_GPU_PLL] = imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, &imx_1416x_pll);
> hws[IMX8MN_M7_ALT_PLL] = imx_clk_hw_pll14xx("m7_alt_pll", "m7_alt_pll_ref_sel", base + 0x74, &imx_1416x_pll);
> @@ -370,7 +370,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
> /* PLL bypass out */
> hws[IMX8MN_AUDIO_PLL1_BYPASS] = imx_clk_hw_mux_flags("audio_pll1_bypass", base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT);
> hws[IMX8MN_AUDIO_PLL2_BYPASS] = imx_clk_hw_mux_flags("audio_pll2_bypass", base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT);
> - hws[IMX8MN_VIDEO_PLL1_BYPASS] = imx_clk_hw_mux_flags("video_pll1_bypass", base + 0x28, 16, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels), CLK_SET_RATE_PARENT);
> + hws[IMX8MN_VIDEO_PLL_BYPASS] = imx_clk_hw_mux_flags("video_pll_bypass", base + 0x28, 16, 1, video_pll_bypass_sels, ARRAY_SIZE(video_pll_bypass_sels), CLK_SET_RATE_PARENT);
> hws[IMX8MN_DRAM_PLL_BYPASS] = imx_clk_hw_mux_flags("dram_pll_bypass", base + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT);
> hws[IMX8MN_GPU_PLL_BYPASS] = imx_clk_hw_mux_flags("gpu_pll_bypass", base + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
> hws[IMX8MN_M7_ALT_PLL_BYPASS] = imx_clk_hw_mux_flags("m7_alt_pll_bypass", base + 0x74, 28, 1, m7_alt_pll_bypass_sels, ARRAY_SIZE(m7_alt_pll_bypass_sels), CLK_SET_RATE_PARENT);
> @@ -380,7 +380,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
> /* PLL out gate */
> hws[IMX8MN_AUDIO_PLL1_OUT] = imx_clk_hw_gate("audio_pll1_out", "audio_pll1_bypass", base, 13);
> hws[IMX8MN_AUDIO_PLL2_OUT] = imx_clk_hw_gate("audio_pll2_out", "audio_pll2_bypass", base + 0x14, 13);
> - hws[IMX8MN_VIDEO_PLL1_OUT] = imx_clk_hw_gate("video_pll1_out", "video_pll1_bypass", base + 0x28, 13);
> + hws[IMX8MN_VIDEO_PLL_OUT] = imx_clk_hw_gate("video_pll_out", "video_pll_bypass", base + 0x28, 13);
> hws[IMX8MN_DRAM_PLL_OUT] = imx_clk_hw_gate("dram_pll_out", "dram_pll_bypass", base + 0x50, 13);
> hws[IMX8MN_GPU_PLL_OUT] = imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x64, 11);
> hws[IMX8MN_M7_ALT_PLL_OUT] = imx_clk_hw_gate("m7_alt_pll_out", "m7_alt_pll_bypass", base + 0x74, 11);


All this changes LGTM.

> diff --git a/include/dt-bindings/clock/imx8mn-clock.h b/include/dt-bindings/clock/imx8mn-clock.h
> index f103b008a12a..5ab6916e444f 100644
> --- a/include/dt-bindings/clock/imx8mn-clock.h
> +++ b/include/dt-bindings/clock/imx8mn-clock.h
> @@ -16,7 +16,7 @@
> #define IMX8MN_CLK_EXT4 7
> #define IMX8MN_AUDIO_PLL1_REF_SEL 8
> #define IMX8MN_AUDIO_PLL2_REF_SEL 9
> -#define IMX8MN_VIDEO_PLL1_REF_SEL 10
> +#define IMX8MN_VIDEO_PLL_REF_SEL 10

Same as in patch-1.

Regards,
Marco

> #define IMX8MN_DRAM_PLL_REF_SEL 11
> #define IMX8MN_GPU_PLL_REF_SEL 12
> #define IMX8MN_M7_ALT_PLL_REF_SEL 13
> @@ -26,7 +26,7 @@
> #define IMX8MN_SYS_PLL3_REF_SEL 17
> #define IMX8MN_AUDIO_PLL1 18
> #define IMX8MN_AUDIO_PLL2 19
> -#define IMX8MN_VIDEO_PLL1 20
> +#define IMX8MN_VIDEO_PLL 20
> #define IMX8MN_DRAM_PLL 21
> #define IMX8MN_GPU_PLL 22
> #define IMX8MN_M7_ALT_PLL 23
> @@ -36,7 +36,7 @@
> #define IMX8MN_SYS_PLL3 27
> #define IMX8MN_AUDIO_PLL1_BYPASS 28
> #define IMX8MN_AUDIO_PLL2_BYPASS 29
> -#define IMX8MN_VIDEO_PLL1_BYPASS 30
> +#define IMX8MN_VIDEO_PLL_BYPASS 30
> #define IMX8MN_DRAM_PLL_BYPASS 31
> #define IMX8MN_GPU_PLL_BYPASS 32
> #define IMX8MN_M7_ALT_PLL_BYPASS 33
> @@ -46,7 +46,7 @@
> #define IMX8MN_SYS_PLL3_BYPASS 37
> #define IMX8MN_AUDIO_PLL1_OUT 38
> #define IMX8MN_AUDIO_PLL2_OUT 39
> -#define IMX8MN_VIDEO_PLL1_OUT 40
> +#define IMX8MN_VIDEO_PLL_OUT 40
> #define IMX8MN_DRAM_PLL_OUT 41
> #define IMX8MN_GPU_PLL_OUT 42
> #define IMX8MN_M7_ALT_PLL_OUT 43
> --
> 2.32.0
>
>
>