Dependencies:
https://lore.kernel.org/all/[email protected]/
https://lore.kernel.org/all/[email protected]/
https://lore.kernel.org/all/[email protected]/
Branch:
https://git.linaro.org/people/robert.foss/linux.git/log/?h=sm8350_dsi_v2
This series implements display support for SM8350 and
enables HDMI output for the SM8350-HDK platform.
Changes from v1:
- Added R-b tags from v1
- Added qcom,sm8350-dpu binding patch
- Added qcom,sm8350-mdss binding patch
- Corrected sm8350.dtsi according to new dpu/mdss bindings
- Bjorn: Removed regulator-always-on property from lt9611_1v2 regulator
- Bjorn: Moved lt9611 pinctl pins into a common node
- Bjorn/Krzysztof: Moved status property to last in node
- Krzysztof: Changed hdmi-out to hdmi-connector
- Krzysztof: Fixed regulator node name
- Krzysztof: Changed &mdss to status=disabled as default
- Krzysztof: Changed &mdss_mdp node name to display-controller
- Krzysztof: Fixed opp-table node name
- Krzysztof: Fixed phy node name
- Dmitry: Split commit containing dpu & mdss compatibles string
- Dmitry: Added msm_mdss_enable case
- Dmitry: Fixed dpu ctl features
Robert Foss (12):
dt-bindings: display: msm: Add qcom,sm8350-dpu binding
dt-bindings: display: msm: Add qcom,sm8350-mdss binding
drm/msm/dpu: Refactor sc7280_pp location
drm/msm/dpu: Add SM8350 to hw catalog
drm/msm/dpu: Add support for SM8350
drm/msm: Add support for SM8350
arm64: dts: qcom: sm8350: Add &tlmm gpio-line-names
arm64: dts: qcom: sm8350: Remove mmxc power-domain-name
arm64: dts: qcom: sm8350: Use 2 interconnect cells
arm64: dts: qcom: sm8350: Add display system nodes
arm64: dts: qcom: sm8350-hdk: Enable display & dsi nodes
arm64: dts: qcom: sm8350-hdk: Enable lt9611uxc dsi-hdmi bridge
.../bindings/display/msm/qcom,sm8350-dpu.yaml | 120 +++++++
.../display/msm/qcom,sm8350-mdss.yaml | 240 +++++++++++++
arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 332 ++++++++++++++++++
arch/arm64/boot/dts/qcom/sm8350.dtsi | 226 +++++++++++-
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 210 ++++++++++-
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
drivers/gpu/drm/msm/msm_mdss.c | 4 +
8 files changed, 1108 insertions(+), 26 deletions(-)
create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml
create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
--
2.34.1
The sc7280_pp declaration is not located by the other _pp
declarations, but rather hidden around the _merge_3d
declarations. Let's fix this to avoid confusion.
Signed-off-by: Robert Foss <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 4dac90ee5b8a..8f2d634f7b6b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -1294,6 +1294,13 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = {
-1),
};
+static const struct dpu_pingpong_cfg sc7280_pp[] = {
+ PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk, -1, -1),
+ PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1),
+ PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1),
+ PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1),
+};
+
static struct dpu_pingpong_cfg qcm2290_pp[] = {
PP_BLK("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
@@ -1352,13 +1359,6 @@ static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = {
MERGE_3D_BLK("merge_3d_3", MERGE_3D_3, 0x65f00),
};
-static const struct dpu_pingpong_cfg sc7280_pp[] = {
- PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk, -1, -1),
- PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1),
- PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1),
- PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1),
-};
-
/*************************************************************
* DSC sub blocks config
*************************************************************/
--
2.34.1
Mobile Display Subsystem (MDSS) encapsulates sub-blocks
like DPU display controller, DSI etc. Add YAML schema for MDSS device
tree bindings
Signed-off-by: Robert Foss <[email protected]>
---
.../display/msm/qcom,sm8350-mdss.yaml | 240 ++++++++++++++++++
1 file changed, 240 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
new file mode 100644
index 000000000000..9a0694853576
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
@@ -0,0 +1,240 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm8350-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8350 Display MDSS
+
+maintainers:
+ - Robert Foss <[email protected]>
+
+description:
+ Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
+ sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
+ bindings of MDSS are mentioned for SM8350 target.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+ compatible:
+ items:
+ - const: qcom,sm8350-mdss
+
+ clocks:
+ items:
+ - description: Display AHB clock from gcc
+ - description: Display hf axi clock
+ - description: Display sf axi clock
+ - description: Display core clock
+
+ clock-names:
+ items:
+ - const: iface
+ - const: bus
+ - const: nrt_bus
+ - const: core
+
+ iommus:
+ maxItems: 1
+
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ maxItems: 2
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ const: qcom,sm8350-dpu
+
+ "^dsi@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ const: qcom,mdss-dsi-ctrl
+
+ "^phy@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ const: qcom,dsi-phy-5nm-8350
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,dispcc-sm8350.h>
+ #include <dt-bindings/clock/qcom,gcc-sm8350.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interconnect/qcom,sm8350.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ display-subsystem@ae00000 {
+ compatible = "qcom,sm8350-mdss";
+ reg = <0x0ae00000 0x1000>;
+ reg-names = "mdss";
+
+ interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
+ <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "mdp0-mem", "mdp1-mem";
+
+ power-domains = <&dispcc MDSS_GDSC>;
+ resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_SF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface", "bus", "nrt_bus", "core";
+
+ iommus = <&apps_smmu 0x820 0x402>;
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ display-controller@ae01000 {
+ compatible = "qcom,sm8350-dpu";
+ reg = <0x0ae01000 0x8f000>,
+ <0x0aeb0000 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_SF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "bus",
+ "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmhpd SM8350_MMCX>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+ };
+
+ mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-345000000 {
+ opp-hz = /bits/ 64 <345000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-460000000 {
+ opp-hz = /bits/ 64 <460000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
+ dsi0: dsi@ae94000 {
+ compatible = "qcom,mdss-dsi-ctrl";
+ reg = <0x0ae94000 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4>;
+
+ clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&dsi0_phy 0>,
+ <&dsi0_phy 1>;
+
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmhpd SM8350_MMCX>;
+
+ phys = <&dsi0_phy>;
+ phy-names = "dsi";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi0_in: endpoint {
+ remote-endpoint = <&dpu_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi0_out: endpoint {
+ };
+ };
+ };
+ };
+
+ dsi0_phy: phy@ae94400 {
+ compatible = "qcom,dsi-phy-5nm-8350";
+ reg = <0x0ae94400 0x200>,
+ <0x0ae94600 0x280>,
+ <0x0ae94900 0x260>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+
+ vdds-supply = <&vreg_l5b_0p88>;
+ };
+ };
+...
--
2.34.1
Mobile Display Subsystem (MDSS) encapsulates sub-blocks
like DPU display controller, DSI etc. Add YAML schema for DPU device
tree bindings
Signed-off-by: Robert Foss <[email protected]>
---
.../bindings/display/msm/qcom,sm8350-dpu.yaml | 120 ++++++++++++++++++
1 file changed, 120 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml
new file mode 100644
index 000000000000..120500395c9a
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml
@@ -0,0 +1,120 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm8350-dpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8350 Display DPU
+
+maintainers:
+ - Robert Foss <[email protected]>
+
+$ref: /schemas/display/msm/dpu-common.yaml#
+
+properties:
+ compatible:
+ const: qcom,sm8350-dpu
+
+ reg:
+ items:
+ - description: Address offset and size for mdp register set
+ - description: Address offset and size for vbif register set
+
+ reg-names:
+ items:
+ - const: mdp
+ - const: vbif
+
+ clocks:
+ items:
+ - description: Display hf axi clock
+ - description: Display sf axi clock
+ - description: Display ahb clock
+ - description: Display lut clock
+ - description: Display core clock
+ - description: Display vsync clock
+
+ clock-names:
+ items:
+ - const: bus
+ - const: nrt_bus
+ - const: iface
+ - const: lut
+ - const: core
+ - const: vsync
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,dispcc-sm8350.h>
+ #include <dt-bindings/clock/qcom,gcc-sm8350.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interconnect/qcom,sm8350.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ display-controller@ae01000 {
+ compatible = "qcom,sm8350-dpu";
+ reg = <0x0ae01000 0x8f000>,
+ <0x0aeb0000 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_SF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "bus",
+ "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmhpd SM8350_MMCX>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+ };
+
+ mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-345000000 {
+ opp-hz = /bits/ 64 <345000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-460000000 {
+ opp-hz = /bits/ 64 <460000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+...
--
2.34.1
On 15/11/2022 12:17, Robert Foss wrote:
> Dependencies:
> https://lore.kernel.org/all/[email protected]/
> https://lore.kernel.org/all/[email protected]/
> https://lore.kernel.org/all/[email protected]/
>
Looks like only patches 0-3 reached linux-arm-msm and freedreno lists?
Konrad
> Branch:
> https://git.linaro.org/people/robert.foss/linux.git/log/?h=sm8350_dsi_v2
>
> This series implements display support for SM8350 and
> enables HDMI output for the SM8350-HDK platform.
>
> Changes from v1:
> - Added R-b tags from v1
> - Added qcom,sm8350-dpu binding patch
> - Added qcom,sm8350-mdss binding patch
> - Corrected sm8350.dtsi according to new dpu/mdss bindings
> - Bjorn: Removed regulator-always-on property from lt9611_1v2 regulator
> - Bjorn: Moved lt9611 pinctl pins into a common node
> - Bjorn/Krzysztof: Moved status property to last in node
> - Krzysztof: Changed hdmi-out to hdmi-connector
> - Krzysztof: Fixed regulator node name
> - Krzysztof: Changed &mdss to status=disabled as default
> - Krzysztof: Changed &mdss_mdp node name to display-controller
> - Krzysztof: Fixed opp-table node name
> - Krzysztof: Fixed phy node name
> - Dmitry: Split commit containing dpu & mdss compatibles string
> - Dmitry: Added msm_mdss_enable case
> - Dmitry: Fixed dpu ctl features
>
>
> Robert Foss (12):
> dt-bindings: display: msm: Add qcom,sm8350-dpu binding
> dt-bindings: display: msm: Add qcom,sm8350-mdss binding
> drm/msm/dpu: Refactor sc7280_pp location
> drm/msm/dpu: Add SM8350 to hw catalog
> drm/msm/dpu: Add support for SM8350
> drm/msm: Add support for SM8350
> arm64: dts: qcom: sm8350: Add &tlmm gpio-line-names
> arm64: dts: qcom: sm8350: Remove mmxc power-domain-name
> arm64: dts: qcom: sm8350: Use 2 interconnect cells
> arm64: dts: qcom: sm8350: Add display system nodes
> arm64: dts: qcom: sm8350-hdk: Enable display & dsi nodes
> arm64: dts: qcom: sm8350-hdk: Enable lt9611uxc dsi-hdmi bridge
>
> .../bindings/display/msm/qcom,sm8350-dpu.yaml | 120 +++++++
> .../display/msm/qcom,sm8350-mdss.yaml | 240 +++++++++++++
> arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 332 ++++++++++++++++++
> arch/arm64/boot/dts/qcom/sm8350.dtsi | 226 +++++++++++-
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 210 ++++++++++-
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
> drivers/gpu/drm/msm/msm_mdss.c | 4 +
> 8 files changed, 1108 insertions(+), 26 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml
> create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
>
On Tue, 15 Nov 2022 12:17:11 +0100, Robert Foss wrote:
> Mobile Display Subsystem (MDSS) encapsulates sub-blocks
> like DPU display controller, DSI etc. Add YAML schema for MDSS device
> tree bindings
>
> Signed-off-by: Robert Foss <[email protected]>
> ---
> .../display/msm/qcom,sm8350-mdss.yaml | 240 ++++++++++++++++++
> 1 file changed, 240 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
./Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml: Unable to find schema file matching $id: http://devicetree.org/schemas/display/msm/mdss-common.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.example.dtb: display-subsystem@ae00000: False schema does not allow {'compatible': ['qcom,sm8350-mdss'], 'reg': [[182452224, 4096]], 'reg-names': ['mdss'], 'interconnects': [[4294967295, 7, 0, 4294967295, 1, 0], [4294967295, 8, 0, 4294967295, 1, 0]], 'interconnect-names': ['mdp0-mem', 'mdp1-mem'], 'power-domains': [[4294967295, 0]], 'resets': [[4294967295, 0]], 'clocks': [[4294967295, 0], [4294967295, 27], [4294967295, 28], [4294967295, 32]], 'clock-names': ['iface', 'bus', 'nrt_bus', 'core'], 'iommus': [[4294967295, 2080, 1026]], 'interrupts': [[0, 83, 4]], 'interrupt-controller': True, '#interrupt-cells': [[1]], '#address-cells': [[1]], '#size-cells': [[1]], 'ranges': True, 'display-controller@ae01000': {'compatible': ['qcom,sm8350-dpu'], 'reg': [[182456320, 585728], [183173120, 8200]], 'reg-names': ['mdp', 'vbif'], 'clocks': [[4294967295, 27], [4294967295, 28], [4294967295, 0], [42
94967295, 34], [4294967295, 32], [4294967295, 44]], 'clock-names': ['bus', 'nrt_bus', 'iface', 'lut', 'core', 'vsync'], 'assigned-clocks': [[4294967295, 44]], 'assigned-clock-rates': [[19200000]], 'operating-points-v2': [[1]], 'power-domains': [[4294967295, 6]], 'interrupts': [[0]], 'ports': {'#address-cells': [[1]], '#size-cells': [[0]], 'port@0': {'reg': [[0]], 'endpoint': {'remote-endpoint': [[2]], 'phandle': [[4]]}}}, 'opp-table': {'compatible': ['operating-points-v2'], 'phandle': [[1]], 'opp-200000000': {'opp-hz': [[0], [200000000]], 'required-opps': [[4294967295]]}, 'opp-300000000': {'opp-hz': [[0], [300000000]], 'required-opps': [[4294967295]]}, 'opp-345000000': {'opp-hz': [[0], [345000000]], 'required-opps': [[4294967295]]}, 'opp-460000000': {'opp-hz': [[0], [460000000]], 'required-opps': [[4294967295]]}}}, 'dsi@ae94000': {'compatible': ['qcom,mdss-dsi-ctrl'], 'reg': [[183058432, 1024]], 'reg-names': ['dsi_ctrl'], 'interrupts': [[4]], 'clocks': [[4294967295, 2], [4294967295,
5], [4294967295, 36], [4294967295, 28], [4294967295, 0], [4294967295, 27]], 'clock-names': ['byte', 'byte_intf', 'pixel', 'core', 'iface', 'bus'], 'assigned-clocks': [[4294967295, 3], [4294967295, 37]], 'assigned-clock-parents': [[3, 0], [3, 1]], 'operating-points-v2': [[4294967295]], 'power-domains': [[4294967295, 6]], 'phys': [[3]], 'phy-names': ['dsi'], 'ports': {'#address-cells': [[1]], '#size-cells': [[0]], 'port@0': {'reg': [[0]], 'endpoint': {'remote-endpoint': [[4]], 'phandle': [[2]]}}, 'port@1': {'reg': [[1]], 'endpoint': {}}}}, 'phy@ae94400': {'compatible': ['qcom,dsi-phy-5nm-8350'], 'reg': [[183059456, 512], [183059968, 640], [183060736, 608]], 'reg-names': ['dsi_phy', 'dsi_phy_lane', 'dsi_pll'], '#clock-cells': [[1]], '#phy-cells': [[0]], 'clocks': [[4294967295, 0], [4294967295, 0]], 'clock-names': ['iface', 'ref'], 'vdds-supply': [[4294967295]], 'phandle': [[3]]}, '$nodename': ['display-subsystem@ae00000']}
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.example.dtb: display-subsystem@ae00000: Unevaluated properties are not allowed ('#address-cells', '#interrupt-cells', '#size-cells', 'interrupt-controller', 'interrupts', 'power-domains', 'ranges', 'reg', 'reg-names', 'resets' were unexpected)
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
On Tue, 15 Nov 2022 12:17:10 +0100, Robert Foss wrote:
> Mobile Display Subsystem (MDSS) encapsulates sub-blocks
> like DPU display controller, DSI etc. Add YAML schema for DPU device
> tree bindings
>
> Signed-off-by: Robert Foss <[email protected]>
> ---
> .../bindings/display/msm/qcom,sm8350-dpu.yaml | 120 ++++++++++++++++++
> 1 file changed, 120 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
./Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml: Unable to find schema file matching $id: http://devicetree.org/schemas/display/msm/dpu-common.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.example.dtb: display-controller@ae01000: False schema does not allow {'compatible': ['qcom,sm8350-dpu'], 'reg': [[182456320, 585728], [183173120, 8200]], 'reg-names': ['mdp', 'vbif'], 'clocks': [[4294967295, 27], [4294967295, 28], [4294967295, 0], [4294967295, 34], [4294967295, 32], [4294967295, 44]], 'clock-names': ['bus', 'nrt_bus', 'iface', 'lut', 'core', 'vsync'], 'assigned-clocks': [[4294967295, 44]], 'assigned-clock-rates': [[19200000]], 'operating-points-v2': [[1]], 'power-domains': [[4294967295, 6]], 'interrupts': [[0]], 'ports': {'#address-cells': [[1]], '#size-cells': [[0]], 'port@0': {'reg': [[0]], 'endpoint': {'remote-endpoint': [[4294967295]]}}}, 'opp-table': {'compatible': ['operating-points-v2'], 'phandle': [[1]], 'opp-200000000': {'opp-hz': [[0], [200000000]], 'required-opps': [[4294967295]]}, 'opp-300000000': {'opp-hz': [[0], [300000000]], 'required-opps': [[4294967295
]]}, 'opp-345000000': {'opp-hz': [[0], [345000000]], 'required-opps': [[4294967295]]}, 'opp-460000000': {'opp-hz': [[0], [460000000]], 'required-opps': [[4294967295]]}}, '$nodename': ['display-controller@ae01000']}
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.example.dtb: display-controller@ae01000: Unevaluated properties are not allowed ('interrupts', 'operating-points-v2', 'opp-table', 'ports', 'power-domains' were unexpected)
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
On Tue, Nov 15, 2022 at 12:17:10PM +0100, Robert Foss wrote:
> Mobile Display Subsystem (MDSS) encapsulates sub-blocks
> like DPU display controller, DSI etc. Add YAML schema for DPU device
> tree bindings
>
> Signed-off-by: Robert Foss <[email protected]>
> ---
> .../bindings/display/msm/qcom,sm8350-dpu.yaml | 120 ++++++++++++++++++
> 1 file changed, 120 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml
Reviewed-by: Rob Herring <[email protected]>
But since there is a dependency, no idea if this passes validation.
On Tue, Nov 15, 2022 at 12:17:11PM +0100, Robert Foss wrote:
> Mobile Display Subsystem (MDSS) encapsulates sub-blocks
> like DPU display controller, DSI etc. Add YAML schema for MDSS device
> tree bindings
>
> Signed-off-by: Robert Foss <[email protected]>
> ---
> .../display/msm/qcom,sm8350-mdss.yaml | 240 ++++++++++++++++++
> 1 file changed, 240 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
> new file mode 100644
> index 000000000000..9a0694853576
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
> @@ -0,0 +1,240 @@
> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/msm/qcom,sm8350-mdss.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm SM8350 Display MDSS
> +
> +maintainers:
> + - Robert Foss <[email protected]>
> +
> +description:
> + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
Drop 'Device tree bindings for '. Describe what this h/w is.
> + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
> + bindings of MDSS are mentioned for SM8350 target.
> +
> +$ref: /schemas/display/msm/mdss-common.yaml#
> +
> +properties:
> + compatible:
> + items:
> + - const: qcom,sm8350-mdss
> +
> + clocks:
> + items:
> + - description: Display AHB clock from gcc
> + - description: Display hf axi clock
> + - description: Display sf axi clock
> + - description: Display core clock
> +
> + clock-names:
> + items:
> + - const: iface
> + - const: bus
> + - const: nrt_bus
> + - const: core
> +
> + iommus:
> + maxItems: 1
> +
> + interconnects:
> + maxItems: 2
> +
> + interconnect-names:
> + maxItems: 2
Need to define the names.
> +
> +patternProperties:
> + "^display-controller@[0-9a-f]+$":
> + type: object
> + properties:
> + compatible:
> + const: qcom,sm8350-dpu
> +
> + "^dsi@[0-9a-f]+$":
> + type: object
> + properties:
> + compatible:
> + const: qcom,mdss-dsi-ctrl
> +
> + "^phy@[0-9a-f]+$":
> + type: object
> + properties:
> + compatible:
> + const: qcom,dsi-phy-5nm-8350
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,dispcc-sm8350.h>
> + #include <dt-bindings/clock/qcom,gcc-sm8350.h>
> + #include <dt-bindings/clock/qcom,rpmh.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interconnect/qcom,sm8350.h>
> + #include <dt-bindings/power/qcom-rpmpd.h>
> +
> + display-subsystem@ae00000 {
> + compatible = "qcom,sm8350-mdss";
> + reg = <0x0ae00000 0x1000>;
> + reg-names = "mdss";
> +
> + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
> + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "mdp0-mem", "mdp1-mem";
> +
> + power-domains = <&dispcc MDSS_GDSC>;
> + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&gcc GCC_DISP_HF_AXI_CLK>,
> + <&gcc GCC_DISP_SF_AXI_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_CLK>;
> + clock-names = "iface", "bus", "nrt_bus", "core";
> +
> + iommus = <&apps_smmu 0x820 0x402>;
> +
> + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + display-controller@ae01000 {
> + compatible = "qcom,sm8350-dpu";
> + reg = <0x0ae01000 0x8f000>,
> + <0x0aeb0000 0x2008>;
> + reg-names = "mdp", "vbif";
> +
> + clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
> + <&gcc GCC_DISP_SF_AXI_CLK>,
> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_CLK>,
> + <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> + clock-names = "bus",
> + "nrt_bus",
> + "iface",
> + "lut",
> + "core",
> + "vsync";
> +
> + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> + assigned-clock-rates = <19200000>;
> +
> + operating-points-v2 = <&mdp_opp_table>;
> + power-domains = <&rpmhpd SM8350_MMCX>;
> +
> + interrupt-parent = <&mdss>;
> + interrupts = <0>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dpu_intf1_out: endpoint {
> + remote-endpoint = <&dsi0_in>;
> + };
> + };
> + };
> +
> + mdp_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-200000000 {
> + opp-hz = /bits/ 64 <200000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-300000000 {
> + opp-hz = /bits/ 64 <300000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
> +
> + opp-345000000 {
> + opp-hz = /bits/ 64 <345000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + };
> +
> + opp-460000000 {
> + opp-hz = /bits/ 64 <460000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + };
> + };
> + };
> +
> + dsi0: dsi@ae94000 {
> + compatible = "qcom,mdss-dsi-ctrl";
> + reg = <0x0ae94000 0x400>;
> + reg-names = "dsi_ctrl";
> +
> + interrupt-parent = <&mdss>;
> + interrupts = <4>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
> + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
> + <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
> + <&dispcc DISP_CC_MDSS_ESC0_CLK>,
> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&gcc GCC_DISP_HF_AXI_CLK>;
> + clock-names = "byte",
> + "byte_intf",
> + "pixel",
> + "core",
> + "iface",
> + "bus";
> +
> + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
> + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
> + assigned-clock-parents = <&dsi0_phy 0>,
> + <&dsi0_phy 1>;
> +
> + operating-points-v2 = <&dsi_opp_table>;
> + power-domains = <&rpmhpd SM8350_MMCX>;
> +
> + phys = <&dsi0_phy>;
> + phy-names = "dsi";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dsi0_in: endpoint {
> + remote-endpoint = <&dpu_intf1_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dsi0_out: endpoint {
> + };
> + };
> + };
> + };
> +
> + dsi0_phy: phy@ae94400 {
I assume the phy has its own example somewhere else and its not really
relevant to this binding. So drop.
> + compatible = "qcom,dsi-phy-5nm-8350";
> + reg = <0x0ae94400 0x200>,
> + <0x0ae94600 0x280>,
> + <0x0ae94900 0x260>;
> + reg-names = "dsi_phy",
> + "dsi_phy_lane",
> + "dsi_pll";
> +
> + #clock-cells = <1>;
> + #phy-cells = <0>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "iface", "ref";
> +
> + vdds-supply = <&vreg_l5b_0p88>;
> + };
> + };
> +...
> --
> 2.34.1
>
>
On Tue, 15 Nov 2022 at 17:49, Rob Herring <[email protected]> wrote:
>
> On Tue, Nov 15, 2022 at 12:17:11PM +0100, Robert Foss wrote:
> > Mobile Display Subsystem (MDSS) encapsulates sub-blocks
> > like DPU display controller, DSI etc. Add YAML schema for MDSS device
> > tree bindings
> >
> > Signed-off-by: Robert Foss <[email protected]>
> > ---
> > .../display/msm/qcom,sm8350-mdss.yaml | 240 ++++++++++++++++++
> > 1 file changed, 240 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
> > new file mode 100644
> > index 000000000000..9a0694853576
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
> > @@ -0,0 +1,240 @@
> > +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/msm/qcom,sm8350-mdss.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Qualcomm SM8350 Display MDSS
> > +
> > +maintainers:
> > + - Robert Foss <[email protected]>
> > +
> > +description:
> > + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
>
> Drop 'Device tree bindings for '. Describe what this h/w is.
Ack
>
> > + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
> > + bindings of MDSS are mentioned for SM8350 target.
> > +
> > +$ref: /schemas/display/msm/mdss-common.yaml#
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - const: qcom,sm8350-mdss
> > +
> > + clocks:
> > + items:
> > + - description: Display AHB clock from gcc
> > + - description: Display hf axi clock
> > + - description: Display sf axi clock
> > + - description: Display core clock
> > +
> > + clock-names:
> > + items:
> > + - const: iface
> > + - const: bus
> > + - const: nrt_bus
> > + - const: core
> > +
> > + iommus:
> > + maxItems: 1
> > +
> > + interconnects:
> > + maxItems: 2
> > +
> > + interconnect-names:
> > + maxItems: 2
>
> Need to define the names.
>
> > +
> > +patternProperties:
> > + "^display-controller@[0-9a-f]+$":
> > + type: object
> > + properties:
> > + compatible:
> > + const: qcom,sm8350-dpu
> > +
> > + "^dsi@[0-9a-f]+$":
> > + type: object
> > + properties:
> > + compatible:
> > + const: qcom,mdss-dsi-ctrl
> > +
> > + "^phy@[0-9a-f]+$":
> > + type: object
> > + properties:
> > + compatible:
> > + const: qcom,dsi-phy-5nm-8350
> > +
> > +unevaluatedProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/qcom,dispcc-sm8350.h>
> > + #include <dt-bindings/clock/qcom,gcc-sm8350.h>
> > + #include <dt-bindings/clock/qcom,rpmh.h>
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > + #include <dt-bindings/interconnect/qcom,sm8350.h>
> > + #include <dt-bindings/power/qcom-rpmpd.h>
> > +
> > + display-subsystem@ae00000 {
> > + compatible = "qcom,sm8350-mdss";
> > + reg = <0x0ae00000 0x1000>;
> > + reg-names = "mdss";
> > +
> > + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
> > + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
> > + interconnect-names = "mdp0-mem", "mdp1-mem";
> > +
> > + power-domains = <&dispcc MDSS_GDSC>;
> > + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
> > +
> > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> > + <&gcc GCC_DISP_HF_AXI_CLK>,
> > + <&gcc GCC_DISP_SF_AXI_CLK>,
> > + <&dispcc DISP_CC_MDSS_MDP_CLK>;
> > + clock-names = "iface", "bus", "nrt_bus", "core";
> > +
> > + iommus = <&apps_smmu 0x820 0x402>;
> > +
> > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > +
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges;
> > +
> > + display-controller@ae01000 {
> > + compatible = "qcom,sm8350-dpu";
> > + reg = <0x0ae01000 0x8f000>,
> > + <0x0aeb0000 0x2008>;
> > + reg-names = "mdp", "vbif";
> > +
> > + clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
> > + <&gcc GCC_DISP_SF_AXI_CLK>,
> > + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> > + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
> > + <&dispcc DISP_CC_MDSS_MDP_CLK>,
> > + <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> > + clock-names = "bus",
> > + "nrt_bus",
> > + "iface",
> > + "lut",
> > + "core",
> > + "vsync";
> > +
> > + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> > + assigned-clock-rates = <19200000>;
> > +
> > + operating-points-v2 = <&mdp_opp_table>;
> > + power-domains = <&rpmhpd SM8350_MMCX>;
> > +
> > + interrupt-parent = <&mdss>;
> > + interrupts = <0>;
> > +
> > + ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + port@0 {
> > + reg = <0>;
> > + dpu_intf1_out: endpoint {
> > + remote-endpoint = <&dsi0_in>;
> > + };
> > + };
> > + };
> > +
> > + mdp_opp_table: opp-table {
> > + compatible = "operating-points-v2";
> > +
> > + opp-200000000 {
> > + opp-hz = /bits/ 64 <200000000>;
> > + required-opps = <&rpmhpd_opp_low_svs>;
> > + };
> > +
> > + opp-300000000 {
> > + opp-hz = /bits/ 64 <300000000>;
> > + required-opps = <&rpmhpd_opp_svs>;
> > + };
> > +
> > + opp-345000000 {
> > + opp-hz = /bits/ 64 <345000000>;
> > + required-opps = <&rpmhpd_opp_svs_l1>;
> > + };
> > +
> > + opp-460000000 {
> > + opp-hz = /bits/ 64 <460000000>;
> > + required-opps = <&rpmhpd_opp_nom>;
> > + };
> > + };
> > + };
> > +
> > + dsi0: dsi@ae94000 {
> > + compatible = "qcom,mdss-dsi-ctrl";
> > + reg = <0x0ae94000 0x400>;
> > + reg-names = "dsi_ctrl";
> > +
> > + interrupt-parent = <&mdss>;
> > + interrupts = <4>;
> > +
> > + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
> > + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
> > + <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
> > + <&dispcc DISP_CC_MDSS_ESC0_CLK>,
> > + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> > + <&gcc GCC_DISP_HF_AXI_CLK>;
> > + clock-names = "byte",
> > + "byte_intf",
> > + "pixel",
> > + "core",
> > + "iface",
> > + "bus";
> > +
> > + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
> > + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
> > + assigned-clock-parents = <&dsi0_phy 0>,
> > + <&dsi0_phy 1>;
> > +
> > + operating-points-v2 = <&dsi_opp_table>;
> > + power-domains = <&rpmhpd SM8350_MMCX>;
> > +
> > + phys = <&dsi0_phy>;
> > + phy-names = "dsi";
> > +
> > + ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + port@0 {
> > + reg = <0>;
> > + dsi0_in: endpoint {
> > + remote-endpoint = <&dpu_intf1_out>;
> > + };
> > + };
> > +
> > + port@1 {
> > + reg = <1>;
> > + dsi0_out: endpoint {
> > + };
> > + };
> > + };
> > + };
> > +
> > + dsi0_phy: phy@ae94400 {
>
> I assume the phy has its own example somewhere else and its not really
> relevant to this binding. So drop.
Ack.
>
> > + compatible = "qcom,dsi-phy-5nm-8350";
> > + reg = <0x0ae94400 0x200>,
> > + <0x0ae94600 0x280>,
> > + <0x0ae94900 0x260>;
> > + reg-names = "dsi_phy",
> > + "dsi_phy_lane",
> > + "dsi_pll";
> > +
> > + #clock-cells = <1>;
> > + #phy-cells = <0>;
> > +
> > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> > + <&rpmhcc RPMH_CXO_CLK>;
> > + clock-names = "iface", "ref";
> > +
> > + vdds-supply = <&vreg_l5b_0p88>;
> > + };
> > + };
> > +...
> > --
> > 2.34.1
> >
> >