This series adds support for Arm SPEv1.2 which is part of the
Armv8.7/Armv9.2 architecture. There's 2 new features that affect the
kernel: a new event filter bit, branch 'not taken', and an inverted
event filter register.
Since this support adds new registers and fields, first the SPE register
defines are converted to automatic generation.
Note that the 'config3' addition in sysfs format files causes SPE to
break. A stable fix e552b7be12ed ("perf: Skip and warn on unknown format
'configN' attrs") landed in v6.1-rc1.
The perf tool side changes are available here[1].
Tested on FVP.
[1] https://lore.kernel.org/all/[email protected]/
Signed-off-by: Rob Herring <[email protected]>
---
Changes in v3:
- Add some more missing SPE register fields and use Enums for some
fields
- Use the new PMSIDR_EL1 register Enum defines in the SPE driver
- Link to v2: https://lore.kernel.org/r/[email protected]
Changes in v2:
- Convert the SPE register defines to automatic generation
- Fixed access to SYS_PMSNEVFR_EL1 when not present
- Rebase on v6.1-rc1
- Link to v1: https://lore.kernel.org/r/[email protected]
---
Rob Herring (8):
perf: arm_spe: Use feature numbering for PMSEVFR_EL1 defines
arm64: Drop SYS_ from SPE register defines
arm64/sysreg: Convert SPE registers to automatic generation
perf: arm_spe: Drop BIT() and use FIELD_GET/PREP accessors
perf: arm_spe: Use new PMSIDR_EL1 register enums
perf: arm_spe: Support new SPEv1.2/v8.7 'not taken' event
perf: Add perf_event_attr::config3
perf: arm_spe: Add support for SPEv1.2 inverted event filtering
arch/arm64/include/asm/el2_setup.h | 6 +-
arch/arm64/include/asm/sysreg.h | 99 +++--------------------
arch/arm64/kvm/debug.c | 2 +-
arch/arm64/kvm/hyp/nvhe/debug-sr.c | 2 +-
arch/arm64/tools/sysreg | 139 +++++++++++++++++++++++++++++++++
drivers/perf/arm_spe_pmu.c | 156 ++++++++++++++++++++++++-------------
include/uapi/linux/perf_event.h | 3 +
7 files changed, 257 insertions(+), 150 deletions(-)
---
base-commit: 9abf2313adc1ca1b6180c508c25f22f9395cc780
change-id: 20220825-arm-spe-v8-7-fedf04e16f23
Best regards,
--
Rob Herring <[email protected]>
Similar to commit 121a8fc088f1 ("arm64/sysreg: Use feature numbering for
PMU and SPE revisions") use feature numbering instead of architecture
versions for the PMSEVFR_EL1 Res0 defines.
Tested-by: James Clark <[email protected]>
Signed-off-by: Rob Herring <[email protected]>
---
v3:
- No change
v2:
- New patch
---
arch/arm64/include/asm/sysreg.h | 6 +++---
drivers/perf/arm_spe_pmu.c | 4 ++--
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 7d301700d1a9..9a4cf12e3e16 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -294,11 +294,11 @@
#define SYS_PMSFCR_EL1_ST_SHIFT 18
#define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5)
-#define SYS_PMSEVFR_EL1_RES0_8_2 \
+#define PMSEVFR_EL1_RES0_IMP \
(GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\
BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0))
-#define SYS_PMSEVFR_EL1_RES0_8_3 \
- (SYS_PMSEVFR_EL1_RES0_8_2 & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11)))
+#define PMSEVFR_EL1_RES0_V1P1 \
+ (PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11)))
#define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6)
#define SYS_PMSLATFR_EL1_MINLAT_SHIFT 0
diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c
index 00e3a637f7b6..65cf93dcc8ee 100644
--- a/drivers/perf/arm_spe_pmu.c
+++ b/drivers/perf/arm_spe_pmu.c
@@ -677,11 +677,11 @@ static u64 arm_spe_pmsevfr_res0(u16 pmsver)
{
switch (pmsver) {
case ID_AA64DFR0_EL1_PMSVer_IMP:
- return SYS_PMSEVFR_EL1_RES0_8_2;
+ return PMSEVFR_EL1_RES0_IMP;
case ID_AA64DFR0_EL1_PMSVer_V1P1:
/* Return the highest version we support in default */
default:
- return SYS_PMSEVFR_EL1_RES0_8_3;
+ return PMSEVFR_EL1_RES0_V1P1;
}
}
--
b4 0.11.0-dev
Arm SPEv1.2 adds another 64-bits of event filtering control. As the
existing perf_event_attr::configN fields are all used up for SPE PMU, an
additional field is needed. Add a new 'config3' field.
Tested-by: James Clark <[email protected]>
Signed-off-by: Rob Herring <[email protected]>
---
v3:
- No change
v2:
- Drop tools/ side update
---
include/uapi/linux/perf_event.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h
index 85be78e0e7f6..b2b1d7b54097 100644
--- a/include/uapi/linux/perf_event.h
+++ b/include/uapi/linux/perf_event.h
@@ -374,6 +374,7 @@ enum perf_event_read_format {
#define PERF_ATTR_SIZE_VER5 112 /* add: aux_watermark */
#define PERF_ATTR_SIZE_VER6 120 /* add: aux_sample_size */
#define PERF_ATTR_SIZE_VER7 128 /* add: sig_data */
+#define PERF_ATTR_SIZE_VER8 136 /* add: config3 */
/*
* Hardware event_id to monitor via a performance monitoring event:
@@ -515,6 +516,8 @@ struct perf_event_attr {
* truncated accordingly on 32 bit architectures.
*/
__u64 sig_data;
+
+ __u64 config3; /* extension of config2 */
};
/*
--
b4 0.11.0-dev
Convert all the SPE register defines to automatic generation. No
functional changes.
New registers and fields for SPEv1.2 are added with the conversion.
Some of the PMBSR MSS field defines are kept as the automatic generation
has no way to create multiple names for the same register bits. The
meaning of the MSS field depends on other bits.
Tested-by: James Clark <[email protected]>
Signed-off-by: Rob Herring <[email protected]>
---
v3:
- Make some fields enums and add some missing fields
v2:
- New patch
---
arch/arm64/include/asm/sysreg.h | 91 ++------------------------
arch/arm64/tools/sysreg | 139 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 144 insertions(+), 86 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 8df8a0a51273..d002dd00e53e 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -237,99 +237,18 @@
#define SYS_PAR_EL1_FST GENMASK(6, 1)
/*** Statistical Profiling Extension ***/
-/* ID registers */
-#define SYS_PMSIDR_EL1 sys_reg(3, 0, 9, 9, 7)
-#define PMSIDR_EL1_FE_SHIFT 0
-#define PMSIDR_EL1_FT_SHIFT 1
-#define PMSIDR_EL1_FL_SHIFT 2
-#define PMSIDR_EL1_ARCHINST_SHIFT 3
-#define PMSIDR_EL1_LDS_SHIFT 4
-#define PMSIDR_EL1_ERND_SHIFT 5
-#define PMSIDR_EL1_INTERVAL_SHIFT 8
-#define PMSIDR_EL1_INTERVAL_MASK GENMASK_ULL(11, 8)
-#define PMSIDR_EL1_MAXSIZE_SHIFT 12
-#define PMSIDR_EL1_MAXSIZE_MASK GENMASK_ULL(15, 12)
-#define PMSIDR_EL1_COUNTSIZE_SHIFT 16
-#define PMSIDR_EL1_COUNTSIZE_MASK GENMASK_ULL(19, 16)
-
-#define SYS_PMBIDR_EL1 sys_reg(3, 0, 9, 10, 7)
-#define PMBIDR_EL1_ALIGN_SHIFT 0
-#define PMBIDR_EL1_ALIGN_MASK 0xfU
-#define PMBIDR_EL1_P_SHIFT 4
-#define PMBIDR_EL1_F_SHIFT 5
-
-/* Sampling controls */
-#define SYS_PMSCR_EL1 sys_reg(3, 0, 9, 9, 0)
-#define PMSCR_EL1_E0SPE_SHIFT 0
-#define PMSCR_EL1_E1SPE_SHIFT 1
-#define PMSCR_EL1_CX_SHIFT 3
-#define PMSCR_EL1_PA_SHIFT 4
-#define PMSCR_EL1_TS_SHIFT 5
-#define PMSCR_EL1_PCT_SHIFT 6
-
-#define SYS_PMSCR_EL2 sys_reg(3, 4, 9, 9, 0)
-#define PMSCR_EL2_E0HSPE_SHIFT 0
-#define PMSCR_EL2_E2SPE_SHIFT 1
-#define PMSCR_EL2_CX_SHIFT 3
-#define PMSCR_EL2_PA_SHIFT 4
-#define PMSCR_EL2_TS_SHIFT 5
-#define PMSCR_EL2_PCT_SHIFT 6
-
-#define SYS_PMSICR_EL1 sys_reg(3, 0, 9, 9, 2)
-
-#define SYS_PMSIRR_EL1 sys_reg(3, 0, 9, 9, 3)
-#define PMSIRR_EL1_RND_SHIFT 0
-#define PMSIRR_EL1_INTERVAL_SHIFT 8
-#define PMSIRR_EL1_INTERVAL_MASK GENMASK_ULL(31, 8)
-
-/* Filtering controls */
-#define SYS_PMSNEVFR_EL1 sys_reg(3, 0, 9, 9, 1)
-
-#define SYS_PMSFCR_EL1 sys_reg(3, 0, 9, 9, 4)
-#define PMSFCR_EL1_FE_SHIFT 0
-#define PMSFCR_EL1_FT_SHIFT 1
-#define PMSFCR_EL1_FL_SHIFT 2
-#define PMSFCR_EL1_B_SHIFT 16
-#define PMSFCR_EL1_LD_SHIFT 17
-#define PMSFCR_EL1_ST_SHIFT 18
-
-#define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5)
#define PMSEVFR_EL1_RES0_IMP \
(GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\
BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0))
#define PMSEVFR_EL1_RES0_V1P1 \
(PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11)))
-#define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6)
-#define PMSLATFR_EL1_MINLAT_SHIFT 0
-
-/* Buffer controls */
-#define SYS_PMBLIMITR_EL1 sys_reg(3, 0, 9, 10, 0)
-#define PMBLIMITR_EL1_E_SHIFT 0
-#define PMBLIMITR_EL1_FM_SHIFT 1
-#define PMBLIMITR_EL1_FM_MASK GENMASK_ULL(2, 1)
-#define PMBLIMITR_EL1_FM_STOP_IRQ 0
-
-#define SYS_PMBPTR_EL1 sys_reg(3, 0, 9, 10, 1)
-
/* Buffer error reporting */
-#define SYS_PMBSR_EL1 sys_reg(3, 0, 9, 10, 3)
-#define PMBSR_EL1_COLL_SHIFT 16
-#define PMBSR_EL1_S_SHIFT 17
-#define PMBSR_EL1_EA_SHIFT 18
-#define PMBSR_EL1_DL_SHIFT 19
-#define PMBSR_EL1_EC_SHIFT 26
-#define PMBSR_EL1_EC_MASK GENMASK_ULL(31, 26)
-
-#define PMBSR_EL1_EC_BUF 0x0UL
-#define PMBSR_EL1_EC_FAULT_S1 0x24UL
-#define PMBSR_EL1_EC_FAULT_S2 0x25UL
-
-#define PMBSR_EL1_FAULT_FSC_SHIFT 0
-#define PMBSR_EL1_FAULT_FSC_MASK 0x3fUL
-
-#define PMBSR_EL1_BUF_BSC_SHIFT 0
-#define PMBSR_EL1_BUF_BSC_MASK 0x3fUL
+#define PMBSR_EL1_FAULT_FSC_SHIFT PMBSR_EL1_MSS_SHIFT
+#define PMBSR_EL1_FAULT_FSC_MASK PMBSR_EL1_MSS_MASK
+
+#define PMBSR_EL1_BUF_BSC_SHIFT PMBSR_EL1_MSS_SHIFT
+#define PMBSR_EL1_BUF_BSC_MASK PMBSR_EL1_MSS_MASK
#define PMBSR_EL1_BUF_BSC_FULL 0x1UL
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 384757a7eda9..04741f446c46 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -854,6 +854,130 @@ Sysreg FAR_EL1 3 0 6 0 0
Field 63:0 ADDR
EndSysreg
+Sysreg PMSCR_EL1 3 0 9 9 0
+Res0 63:8
+Field 7:6 PCT
+Field 5 TS
+Field 4 PA
+Field 3 CX
+Res0 2
+Field 1 E1SPE
+Field 0 E0SPE
+EndSysreg
+
+Sysreg PMSNEVFR_EL1 3 0 9 9 1
+Field 63:0 E
+EndSysreg
+
+Sysreg PMSICR_EL1 3 0 9 9 2
+Field 63:56 ECOUNT
+Res0 55:32
+Field 31:0 COUNT
+EndSysreg
+
+Sysreg PMSIRR_EL1 3 0 9 9 3
+Res0 63:32
+Field 31:8 INTERVAL
+Res0 7:1
+Field 0 RND
+EndSysreg
+
+Sysreg PMSFCR_EL1 3 0 9 9 4
+Res0 63:19
+Field 18 ST
+Field 17 LD
+Field 16 B
+Res0 15:4
+Field 3 FnE
+Field 2 FL
+Field 1 FT
+Field 0 FE
+EndSysreg
+
+Sysreg PMSEVFR_EL1 3 0 9 9 5
+Field 63:0 E
+EndSysreg
+
+Sysreg PMSLATFR_EL1 3 0 9 9 6
+Res0 63:16
+Field 15:0 MINLAT
+EndSysreg
+
+Sysreg PMSIDR_EL1 3 0 9 9 7
+Res0 63:25
+Field 24 PBT
+Field 23:20 FORMAT
+Enum 19:16 COUNTSIZE
+ 0b0010 12_BIT_SAT
+ 0b0011 16_BIT_SAT
+EndEnum
+Field 15:12 MAXSIZE
+Enum 11:8 INTERVAL
+ 0b0000 256
+ 0b0010 512
+ 0b0011 768
+ 0b0100 1024
+ 0b0101 1536
+ 0b0110 2048
+ 0b0111 3072
+ 0b1000 4096
+EndEnum
+Res0 7
+Field 6 FnE
+Field 5 ERND
+Field 4 LDS
+Field 3 ARCHINST
+Field 2 FL
+Field 1 FT
+Field 0 FE
+EndSysreg
+
+Sysreg PMBLIMITR_EL1 3 0 9 10 0
+Field 63:12 LIMIT
+Res0 11:6
+Field 5 PMFZ
+Res0 4:3
+Enum 2:1 FM
+ 0b00 FILL
+ 0b10 DISCARD
+EndEnum
+Field 0 E
+EndSysreg
+
+Sysreg PMBPTR_EL1 3 0 9 10 1
+Field 63:0 PTR
+EndSysreg
+
+Sysreg PMBSR_EL1 3 0 9 10 3
+Res0 63:32
+Enum 31:26 EC
+ 0b000000 BUF
+ 0b100100 FAULT_S1
+ 0b100101 FAULT_S2
+ 0b011110 FAULT_GPC
+ 0b011111 IMP_DEF
+EndEnum
+Res0 25:20
+Field 19 DL
+Field 18 EA
+Field 17 S
+Field 16 COLL
+Field 15:0 MSS
+EndSysreg
+
+Sysreg PMBIDR_EL1 3 0 9 10 7
+Res0 63:12
+Enum 11:8 EA
+ 0b0000 NotDescribed
+ 0b0001 Ignored
+ 0b0010 SError
+EndEnum
+Res0 7:6
+Field 5 F
+Field 4 P
+Field 3:0 ALIGN
+EndSysreg
+
SysregFields CONTEXTIDR_ELx
Res0 63:32
Field 31:0 PROCID
@@ -1008,6 +1132,21 @@ Sysreg FAR_EL2 3 4 6 0 0
Field 63:0 ADDR
EndSysreg
+Sysreg PMSCR_EL2 3 4 9 9 0
+Res0 63:8
+Enum 7:6 PCT
+ 0b00 VIRT
+ 0b01 PHYS
+ 0b11 GUEST
+EndEnum
+Field 5 TS
+Field 4 PA
+Field 3 CX
+Res0 2
+Field 1 E2SPE
+Field 0 E0HSPE
+EndSysreg
+
Sysreg CONTEXTIDR_EL2 3 4 13 0 1
Fields CONTEXTIDR_ELx
EndSysreg
--
b4 0.11.0-dev
Arm SPEv1.2 (Armv8.7/v9.2) adds a new event, 'not taken', in bit 6 of
the PMSEVFR_EL1 register. Update arm_spe_pmsevfr_res0() to support the
additional event.
Tested-by: James Clark <[email protected]>
Signed-off-by: Rob Herring <[email protected]>
---
v3:
- No change
v2:
- Update for v6.1 sysreg generated header changes
---
arch/arm64/include/asm/sysreg.h | 2 ++
drivers/perf/arm_spe_pmu.c | 4 +++-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index d002dd00e53e..06231e896832 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -242,6 +242,8 @@
BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0))
#define PMSEVFR_EL1_RES0_V1P1 \
(PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11)))
+#define PMSEVFR_EL1_RES0_V1P2 \
+ (PMSEVFR_EL1_RES0_V1P1 & ~BIT_ULL(6))
/* Buffer error reporting */
#define PMBSR_EL1_FAULT_FSC_SHIFT PMBSR_EL1_MSS_SHIFT
diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c
index af6d3867c3e7..82f67e941bc4 100644
--- a/drivers/perf/arm_spe_pmu.c
+++ b/drivers/perf/arm_spe_pmu.c
@@ -677,9 +677,11 @@ static u64 arm_spe_pmsevfr_res0(u16 pmsver)
case ID_AA64DFR0_EL1_PMSVer_IMP:
return PMSEVFR_EL1_RES0_IMP;
case ID_AA64DFR0_EL1_PMSVer_V1P1:
+ return PMSEVFR_EL1_RES0_V1P1;
+ case ID_AA64DFR0_EL1_PMSVer_V1P2:
/* Return the highest version we support in default */
default:
- return PMSEVFR_EL1_RES0_V1P1;
+ return PMSEVFR_EL1_RES0_V1P2;
}
}
--
b4 0.11.0-dev
On Fri, Nov 04, 2022 at 10:55:03AM -0500, Rob Herring wrote:
> Convert all the SPE register defines to automatic generation. No
> functional changes.
>
> New registers and fields for SPEv1.2 are added with the conversion.
>
> Some of the PMBSR MSS field defines are kept as the automatic generation
> has no way to create multiple names for the same register bits. The
> meaning of the MSS field depends on other bits.
Reviewed-by: Mark Brown <[email protected]>
> +Sysreg PMSNEVFR_EL1 3 0 9 9 1
> +Field 63:0 E
> +EndSysreg
JFTR as noted last time this looks nothing like the spec but is clearly
a sensible interpretation.
I do note that one advantage of doing this register by register rather
than en masse is that it makes it a lot easier to avoid re-reviewing the
same register...
On Fri, Nov 4, 2022 at 10:55 AM Rob Herring <[email protected]> wrote:
>
> This series adds support for Arm SPEv1.2 which is part of the
> Armv8.7/Armv9.2 architecture. There's 2 new features that affect the
> kernel: a new event filter bit, branch 'not taken', and an inverted
> event filter register.
>
> Since this support adds new registers and fields, first the SPE register
> defines are converted to automatic generation.
>
> Note that the 'config3' addition in sysfs format files causes SPE to
> break. A stable fix e552b7be12ed ("perf: Skip and warn on unknown format
> 'configN' attrs") landed in v6.1-rc1.
>
> The perf tool side changes are available here[1].
>
> Tested on FVP.
>
> [1] https://lore.kernel.org/all/[email protected]/
>
> Signed-off-by: Rob Herring <[email protected]>
> ---
> Changes in v3:
> - Add some more missing SPE register fields and use Enums for some
> fields
> - Use the new PMSIDR_EL1 register Enum defines in the SPE driver
> - Link to v2: https://lore.kernel.org/r/[email protected]
>
> Changes in v2:
> - Convert the SPE register defines to automatic generation
> - Fixed access to SYS_PMSNEVFR_EL1 when not present
> - Rebase on v6.1-rc1
> - Link to v1: https://lore.kernel.org/r/[email protected]
>
> ---
> Rob Herring (8):
> perf: arm_spe: Use feature numbering for PMSEVFR_EL1 defines
> arm64: Drop SYS_ from SPE register defines
> arm64/sysreg: Convert SPE registers to automatic generation
> perf: arm_spe: Drop BIT() and use FIELD_GET/PREP accessors
> perf: arm_spe: Use new PMSIDR_EL1 register enums
> perf: arm_spe: Support new SPEv1.2/v8.7 'not taken' event
> perf: Add perf_event_attr::config3
> perf: arm_spe: Add support for SPEv1.2 inverted event filtering
>
> arch/arm64/include/asm/el2_setup.h | 6 +-
> arch/arm64/include/asm/sysreg.h | 99 +++--------------------
> arch/arm64/kvm/debug.c | 2 +-
> arch/arm64/kvm/hyp/nvhe/debug-sr.c | 2 +-
> arch/arm64/tools/sysreg | 139 +++++++++++++++++++++++++++++++++
> drivers/perf/arm_spe_pmu.c | 156 ++++++++++++++++++++++++-------------
> include/uapi/linux/perf_event.h | 3 +
> 7 files changed, 257 insertions(+), 150 deletions(-)
Will, any comments on this series?
On Fri, Nov 04, 2022 at 10:55:07AM -0500, Rob Herring wrote:
> Arm SPEv1.2 adds another 64-bits of event filtering control. As the
> existing perf_event_attr::configN fields are all used up for SPE PMU, an
> additional field is needed. Add a new 'config3' field.
>
> Tested-by: James Clark <[email protected]>
> Signed-off-by: Rob Herring <[email protected]>
> ---
> v3:
> - No change
> v2:
> - Drop tools/ side update
> ---
> include/uapi/linux/perf_event.h | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h
> index 85be78e0e7f6..b2b1d7b54097 100644
> --- a/include/uapi/linux/perf_event.h
> +++ b/include/uapi/linux/perf_event.h
> @@ -374,6 +374,7 @@ enum perf_event_read_format {
> #define PERF_ATTR_SIZE_VER5 112 /* add: aux_watermark */
> #define PERF_ATTR_SIZE_VER6 120 /* add: aux_sample_size */
> #define PERF_ATTR_SIZE_VER7 128 /* add: sig_data */
> +#define PERF_ATTR_SIZE_VER8 136 /* add: config3 */
>
> /*
> * Hardware event_id to monitor via a performance monitoring event:
> @@ -515,6 +516,8 @@ struct perf_event_attr {
> * truncated accordingly on 32 bit architectures.
> */
> __u64 sig_data;
> +
> + __u64 config3; /* extension of config2 */
I need an ack from the perf core maintainers before I can take this.
Will
On Thu, Nov 17, 2022 at 08:43:17AM -0600, Rob Herring wrote:
> On Fri, Nov 4, 2022 at 10:55 AM Rob Herring <[email protected]> wrote:
> >
> > This series adds support for Arm SPEv1.2 which is part of the
> > Armv8.7/Armv9.2 architecture. There's 2 new features that affect the
> > kernel: a new event filter bit, branch 'not taken', and an inverted
> > event filter register.
> >
> > Since this support adds new registers and fields, first the SPE register
> > defines are converted to automatic generation.
> >
> > Note that the 'config3' addition in sysfs format files causes SPE to
> > break. A stable fix e552b7be12ed ("perf: Skip and warn on unknown format
> > 'configN' attrs") landed in v6.1-rc1.
> >
> > The perf tool side changes are available here[1].
> >
> > Tested on FVP.
> >
> > [1] https://lore.kernel.org/all/[email protected]/
> >
> > Signed-off-by: Rob Herring <[email protected]>
> > ---
> > Changes in v3:
> > - Add some more missing SPE register fields and use Enums for some
> > fields
> > - Use the new PMSIDR_EL1 register Enum defines in the SPE driver
> > - Link to v2: https://lore.kernel.org/r/[email protected]
> >
> > Changes in v2:
> > - Convert the SPE register defines to automatic generation
> > - Fixed access to SYS_PMSNEVFR_EL1 when not present
> > - Rebase on v6.1-rc1
> > - Link to v1: https://lore.kernel.org/r/[email protected]
> >
> > ---
> > Rob Herring (8):
> > perf: arm_spe: Use feature numbering for PMSEVFR_EL1 defines
> > arm64: Drop SYS_ from SPE register defines
> > arm64/sysreg: Convert SPE registers to automatic generation
> > perf: arm_spe: Drop BIT() and use FIELD_GET/PREP accessors
> > perf: arm_spe: Use new PMSIDR_EL1 register enums
> > perf: arm_spe: Support new SPEv1.2/v8.7 'not taken' event
> > perf: Add perf_event_attr::config3
> > perf: arm_spe: Add support for SPEv1.2 inverted event filtering
> >
> > arch/arm64/include/asm/el2_setup.h | 6 +-
> > arch/arm64/include/asm/sysreg.h | 99 +++--------------------
> > arch/arm64/kvm/debug.c | 2 +-
> > arch/arm64/kvm/hyp/nvhe/debug-sr.c | 2 +-
> > arch/arm64/tools/sysreg | 139 +++++++++++++++++++++++++++++++++
> > drivers/perf/arm_spe_pmu.c | 156 ++++++++++++++++++++++++-------------
> > include/uapi/linux/perf_event.h | 3 +
> > 7 files changed, 257 insertions(+), 150 deletions(-)
>
> Will, any comments on this series?
Looks fine to me. Happy to queue it once the uapi change has been acked.
Will
On Fri, Nov 18, 2022 at 10:49 AM Will Deacon <[email protected]> wrote:
>
> On Fri, Nov 04, 2022 at 10:55:07AM -0500, Rob Herring wrote:
> > Arm SPEv1.2 adds another 64-bits of event filtering control. As the
> > existing perf_event_attr::configN fields are all used up for SPE PMU, an
> > additional field is needed. Add a new 'config3' field.
> >
> > Tested-by: James Clark <[email protected]>
> > Signed-off-by: Rob Herring <[email protected]>
> > ---
> > v3:
> > - No change
> > v2:
> > - Drop tools/ side update
> > ---
> > include/uapi/linux/perf_event.h | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h
> > index 85be78e0e7f6..b2b1d7b54097 100644
> > --- a/include/uapi/linux/perf_event.h
> > +++ b/include/uapi/linux/perf_event.h
> > @@ -374,6 +374,7 @@ enum perf_event_read_format {
> > #define PERF_ATTR_SIZE_VER5 112 /* add: aux_watermark */
> > #define PERF_ATTR_SIZE_VER6 120 /* add: aux_sample_size */
> > #define PERF_ATTR_SIZE_VER7 128 /* add: sig_data */
> > +#define PERF_ATTR_SIZE_VER8 136 /* add: config3 */
> >
> > /*
> > * Hardware event_id to monitor via a performance monitoring event:
> > @@ -515,6 +516,8 @@ struct perf_event_attr {
> > * truncated accordingly on 32 bit architectures.
> > */
> > __u64 sig_data;
> > +
> > + __u64 config3; /* extension of config2 */
>
> I need an ack from the perf core maintainers before I can take this.
Peter, Arnaldo, Ingo,
Can I get an ack on this please.
Rob
Rob Herring <[email protected]> writes:
> On Fri, Nov 18, 2022 at 10:49 AM Will Deacon <[email protected]> wrote:
>>
>> On Fri, Nov 04, 2022 at 10:55:07AM -0500, Rob Herring wrote:
>> > @@ -515,6 +516,8 @@ struct perf_event_attr {
>> > * truncated accordingly on 32 bit architectures.
>> > */
>> > __u64 sig_data;
>> > +
>> > + __u64 config3; /* extension of config2 */
>>
>> I need an ack from the perf core maintainers before I can take this.
>
> Peter, Arnaldo, Ingo,
>
> Can I get an ack on this please.
It appears that PMUs that don't use config{1,2} and now config3 allow
them to be whatever without any validation, whereas in reality we should
probably -EINVAL in those cases. Should something be done about that?
Regards,
--
Alex
On Mon, Nov 28, 2022 at 10:36 AM Alexander Shishkin
<[email protected]> wrote:
>
> Rob Herring <[email protected]> writes:
>
> > On Fri, Nov 18, 2022 at 10:49 AM Will Deacon <[email protected]> wrote:
> >>
> >> On Fri, Nov 04, 2022 at 10:55:07AM -0500, Rob Herring wrote:
> >> > @@ -515,6 +516,8 @@ struct perf_event_attr {
> >> > * truncated accordingly on 32 bit architectures.
> >> > */
> >> > __u64 sig_data;
> >> > +
> >> > + __u64 config3; /* extension of config2 */
> >>
> >> I need an ack from the perf core maintainers before I can take this.
> >
> > Peter, Arnaldo, Ingo,
> >
> > Can I get an ack on this please.
>
> It appears that PMUs that don't use config{1,2} and now config3 allow
> them to be whatever without any validation, whereas in reality we should
> probably -EINVAL in those cases. Should something be done about that?
Always the 3rd occurrence that gets to clean-up things. ;)
I think we'd have to add some capability flags for PMU drivers to set
to enable configN usage and then use those to validate configN is 0.
Wouldn't be too hard to do for config3 as we know there's exactly 1
user, but for 1,2 there's about 80 PMU drivers to check.
Rob
Peter, it looks like this series is blocked on the below now; what would you
prefer out of:
(a) Take this as is, and look add adding additional validation on top.
(b) Add some flag to indicate a PMU driver supports config3, and have the core
code check that, but leave the existing fields as-is for now (and hopefully
follow up with further validation later for the existing fields).
(c) Go audit all the existing drivers, add flags to indicate support for
existing fields, and have the core code check that. Atop that, add support
for config3 with the same sort of flag check.
I suspect that'd end up needing to go check more than config1/config2 given
all the filter controls and so on that drivers aren't great at checking,
and that might being fairly invasive.
(d) Something else?
I think we want to get to a point where drivers indicate what they actually
support and the core code rejects stuff drivers don't support or recognise, but
I think it'd be a little unreasonable to delay this series on cleaning up all
the existing issues.
I'm tempted to say (b) as that shouldn't introduce any regressions, should be a
relatively simple change to this series, and doesn't precluse making the rest
stricter as a follow-up. I'm happy to take a look at that (and IIUC Rob is
too).
What's your preference?
Thanks,
Mark.
On Mon, Nov 28, 2022 at 11:15:21AM -0600, Rob Herring wrote:
> On Mon, Nov 28, 2022 at 10:36 AM Alexander Shishkin
> <[email protected]> wrote:
> >
> > Rob Herring <[email protected]> writes:
> >
> > > On Fri, Nov 18, 2022 at 10:49 AM Will Deacon <[email protected]> wrote:
> > >>
> > >> On Fri, Nov 04, 2022 at 10:55:07AM -0500, Rob Herring wrote:
> > >> > @@ -515,6 +516,8 @@ struct perf_event_attr {
> > >> > * truncated accordingly on 32 bit architectures.
> > >> > */
> > >> > __u64 sig_data;
> > >> > +
> > >> > + __u64 config3; /* extension of config2 */
> > >>
> > >> I need an ack from the perf core maintainers before I can take this.
> > >
> > > Peter, Arnaldo, Ingo,
> > >
> > > Can I get an ack on this please.
> >
> > It appears that PMUs that don't use config{1,2} and now config3 allow
> > them to be whatever without any validation, whereas in reality we should
> > probably -EINVAL in those cases. Should something be done about that?
>
> Always the 3rd occurrence that gets to clean-up things. ;)
>
> I think we'd have to add some capability flags for PMU drivers to set
> to enable configN usage and then use those to validate configN is 0.
> Wouldn't be too hard to do for config3 as we know there's exactly 1
> user, but for 1,2 there's about 80 PMU drivers to check.
>
> Rob
>
On Tue, Dec 6, 2022 at 10:28 AM Mark Rutland <[email protected]> wrote:
>
> Peter, it looks like this series is blocked on the below now; what would you
> prefer out of:
>
> (a) Take this as is, and look add adding additional validation on top.
>
> (b) Add some flag to indicate a PMU driver supports config3, and have the core
> code check that, but leave the existing fields as-is for now (and hopefully
> follow up with further validation later for the existing fields).
That looks something like this:
diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
index 853f64b6c8c2..845162b152ea 100644
--- a/include/linux/perf_event.h
+++ b/include/linux/perf_event.h
@@ -286,6 +286,7 @@ struct perf_event;
#define PERF_PMU_CAP_NO_EXCLUDE 0x0080
#define PERF_PMU_CAP_AUX_OUTPUT 0x0100
#define PERF_PMU_CAP_EXTENDED_HW_TYPE 0x0200
+#define PERF_PMU_CAP_CONFIG3 0x0400
struct perf_output_handle;
diff --git a/kernel/events/core.c b/kernel/events/core.c
index aefc1e08e015..4414ae64432a 100644
--- a/kernel/events/core.c
+++ b/kernel/events/core.c
@@ -11314,6 +11314,9 @@ static int perf_try_init_event(struct pmu
*pmu, struct perf_event *event)
event_has_any_exclude_flag(event))
ret = -EINVAL;
+ if (!(pmu->capabilities & PERF_PMU_CAP_CONFIG3) &&
event->attr.config3)
+ ret = -EINVAL;
+
if (ret && event->destroy)
event->destroy(event);
}