This series fixes the USB-DP PHY devicetree binding for SC8280XP and
adds support for the new updated binding to the driver.
As the full series including the preparatory parts is over forty patches
and I've been posting this in three parts of which this is the last one.
In an effort to get all of these into 6.2, I've also submitted all three
series before waiting for the previous ones to be applied. Parts one and
two can be found here:
https://lore.kernel.org/lkml/[email protected]/
https://lore.kernel.org/lkml/[email protected]/
This last series adds a new binding for SC8280XP that drops the legacy
child node and the (incomplete) description of register subregions.
As the current bindings are both incomplete and incorrect it may be
a good idea to update also the other platforms currently supported by
this driver to the new binding scheme. The driver can support both
schemes during a transition period before removing the corresponding
code (dt parsing and clock-provider registration).
Johan
Changes in v3
- make new QMP header dual licensed (Rob)
Changes in v2:
- drop quotes from old DT schema $id and $schema (Krzysztof)
- drop clock-output-names from new binding (Krzysztof)
- add QMP clock and PHY index constants in a new header
- drop patch moving clock registration before runtime PM enable (Dmitry)
- include also the corresponding dts changes
Johan Hovold (15):
dt-bindings: phy: qcom,qmp-usb3-dp: rename current bindings
dt-bindings: phy: qcom,qmp-usb3-dp: fix sc8280xp binding
phy: qcom-qmp-combo: drop v4 reference-clock source
phy: qcom-qmp-combo: restructure PHY creation
phy: qcom-qmp-combo: generate pipe clock name
phy: qcom-qmp-combo: drop redundant clock structure
phy: qcom-qmp-combo: drop redundant clock allocation
phy: qcom-qmp-combo: add clock registration helper
phy: qcom-qmp-combo: separate clock and provider registration
phy: qcom-qmp-combo: clean up DP clock callbacks
phy: qcom-qmp-combo: rename common-register pointers
phy: qcom-qmp-combo: rename DP_PHY register pointer
phy: qcom-qmp-combo: add support for updated sc8280xp binding
arm64: dts: qcom: sc8280xp: fix primary USB-DP PHY reset
arm64: dts: qcom: sc8280xp: fix USB-DP PHY nodes
....yaml => qcom,sc7180-qmp-usb3-dp-phy.yaml} | 25 +-
.../phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml | 99 ++++
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 79 +--
drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 530 +++++++++++-------
include/dt-bindings/phy/phy-qcom-qmp.h | 20 +
5 files changed, 473 insertions(+), 280 deletions(-)
rename Documentation/devicetree/bindings/phy/{qcom,qmp-usb3-dp-phy.yaml => qcom,sc7180-qmp-usb3-dp-phy.yaml} (91%)
create mode 100644 Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
create mode 100644 include/dt-bindings/phy/phy-qcom-qmp.h
--
2.37.4
The DP_PHY registers have erroneously been referred to as "PCS"
registers since DisplayPort support was added to the QMP drivers
(including in the devicetree binding).
Rename the corresponding pointer to match the register names.
Note that the repeated "dp" in the field name is intentional and this DP
register block is called "DP_PHY" (not just "PHY").
Reviewed-by: Dmitry Baryshkov <[email protected]>
Signed-off-by: Johan Hovold <[email protected]>
---
drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 139 +++++++++++-----------
1 file changed, 70 insertions(+), 69 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
index 5777bd1f76b3..b82bd0a221d6 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
@@ -878,7 +878,7 @@ struct qmp_combo {
void __iomem *dp_serdes;
void __iomem *dp_tx;
void __iomem *dp_tx2;
- void __iomem *dp_pcs;
+ void __iomem *dp_dp_phy;
struct clk *pipe_clk;
struct clk_bulk_data *clks;
@@ -1252,20 +1252,20 @@ static void qmp_v3_dp_aux_init(struct qmp_combo *qmp)
{
writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
- qmp->dp_pcs + QSERDES_DP_PHY_PD_CTL);
+ qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
/* Turn on BIAS current for PHY/PLL */
writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
qmp->dp_serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
- writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_pcs + QSERDES_DP_PHY_PD_CTL);
+ writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
DP_PHY_PD_CTL_LANE_0_1_PWRDN |
DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
DP_PHY_PD_CTL_DP_CLAMP_EN,
- qmp->dp_pcs + QSERDES_DP_PHY_PD_CTL);
+ qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
writel(QSERDES_V3_COM_BIAS_EN |
QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
@@ -1273,22 +1273,22 @@ static void qmp_v3_dp_aux_init(struct qmp_combo *qmp)
QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
qmp->dp_serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
- writel(0x00, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG0);
- writel(0x13, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG1);
- writel(0x24, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG2);
- writel(0x00, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG3);
- writel(0x0a, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG4);
- writel(0x26, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG5);
- writel(0x0a, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG6);
- writel(0x03, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG7);
- writel(0xbb, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG8);
- writel(0x03, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG9);
+ writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0);
+ writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
+ writel(0x24, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
+ writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3);
+ writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4);
+ writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5);
+ writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6);
+ writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7);
+ writel(0xbb, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8);
+ writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9);
qmp->dp_aux_cfg = 0;
writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
PHY_AUX_REQ_ERR_MASK,
- qmp->dp_pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
+ qmp->dp_dp_phy + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
}
static int qmp_combo_configure_dp_swing(struct qmp_combo *qmp,
@@ -1372,12 +1372,12 @@ static bool qmp_combo_configure_dp_mode(struct qmp_combo *qmp)
* if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
* val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
* if (orientation == ORIENTATION_CC2)
- * writel(0x4c, qmp->dp_pcs + QSERDES_V3_DP_PHY_MODE);
+ * writel(0x4c, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_MODE);
*/
val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
- writel(val, qmp->dp_pcs + QSERDES_DP_PHY_PD_CTL);
+ writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
- writel(0x5c, qmp->dp_pcs + QSERDES_DP_PHY_MODE);
+ writel(0x5c, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE);
return reverse;
}
@@ -1390,8 +1390,8 @@ static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp)
qmp_combo_configure_dp_mode(qmp);
- writel(0x05, qmp->dp_pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
- writel(0x05, qmp->dp_pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
+ writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
+ writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
switch (dp_opts->link_rate) {
case 1620:
@@ -1414,16 +1414,16 @@ static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp)
/* Other link rates aren't supported */
return -EINVAL;
}
- writel(phy_vco_div, qmp->dp_pcs + QSERDES_V3_DP_PHY_VCO_DIV);
+ writel(phy_vco_div, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_VCO_DIV);
clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000);
clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq);
- writel(0x04, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG2);
- writel(0x01, qmp->dp_pcs + QSERDES_DP_PHY_CFG);
- writel(0x05, qmp->dp_pcs + QSERDES_DP_PHY_CFG);
- writel(0x01, qmp->dp_pcs + QSERDES_DP_PHY_CFG);
- writel(0x09, qmp->dp_pcs + QSERDES_DP_PHY_CFG);
+ writel(0x04, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
+ writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
+ writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
+ writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
+ writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
writel(0x20, qmp->dp_serdes + QSERDES_V3_COM_RESETSM_CNTRL);
@@ -1434,20 +1434,20 @@ static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp)
10000))
return -ETIMEDOUT;
- writel(0x19, qmp->dp_pcs + QSERDES_DP_PHY_CFG);
+ writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
- if (readl_poll_timeout(qmp->dp_pcs + QSERDES_V3_DP_PHY_STATUS,
+ if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V3_DP_PHY_STATUS,
status,
((status & BIT(1)) > 0),
500,
10000))
return -ETIMEDOUT;
- writel(0x18, qmp->dp_pcs + QSERDES_DP_PHY_CFG);
+ writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
udelay(2000);
- writel(0x19, qmp->dp_pcs + QSERDES_DP_PHY_CFG);
+ writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
- return readl_poll_timeout(qmp->dp_pcs + QSERDES_V3_DP_PHY_STATUS,
+ return readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V3_DP_PHY_STATUS,
status,
((status & BIT(1)) > 0),
500,
@@ -1467,7 +1467,7 @@ static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp)
qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
val = cfg1_settings[qmp->dp_aux_cfg];
- writel(val, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG1);
+ writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
return 0;
}
@@ -1476,27 +1476,27 @@ static void qmp_v4_dp_aux_init(struct qmp_combo *qmp)
{
writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
- qmp->dp_pcs + QSERDES_DP_PHY_PD_CTL);
+ qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
/* Turn on BIAS current for PHY/PLL */
writel(0x17, qmp->dp_serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
- writel(0x00, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG0);
- writel(0x13, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG1);
- writel(0xa4, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG2);
- writel(0x00, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG3);
- writel(0x0a, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG4);
- writel(0x26, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG5);
- writel(0x0a, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG6);
- writel(0x03, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG7);
- writel(0xb7, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG8);
- writel(0x03, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG9);
+ writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0);
+ writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
+ writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
+ writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3);
+ writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4);
+ writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5);
+ writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6);
+ writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7);
+ writel(0xb7, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8);
+ writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9);
qmp->dp_aux_cfg = 0;
writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
PHY_AUX_REQ_ERR_MASK,
- qmp->dp_pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
+ qmp->dp_dp_phy + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
}
static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp)
@@ -1518,15 +1518,15 @@ static int qmp_v45_configure_dp_phy(struct qmp_combo *qmp)
u32 phy_vco_div, status;
unsigned long pixel_freq;
- writel(0x0f, qmp->dp_pcs + QSERDES_V4_DP_PHY_CFG_1);
+ writel(0x0f, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_CFG_1);
qmp_combo_configure_dp_mode(qmp);
- writel(0x13, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG1);
- writel(0xa4, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG2);
+ writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
+ writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
- writel(0x05, qmp->dp_pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
- writel(0x05, qmp->dp_pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
+ writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
+ writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
switch (dp_opts->link_rate) {
case 1620:
@@ -1549,15 +1549,15 @@ static int qmp_v45_configure_dp_phy(struct qmp_combo *qmp)
/* Other link rates aren't supported */
return -EINVAL;
}
- writel(phy_vco_div, qmp->dp_pcs + QSERDES_V4_DP_PHY_VCO_DIV);
+ writel(phy_vco_div, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_VCO_DIV);
clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000);
clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq);
- writel(0x01, qmp->dp_pcs + QSERDES_DP_PHY_CFG);
- writel(0x05, qmp->dp_pcs + QSERDES_DP_PHY_CFG);
- writel(0x01, qmp->dp_pcs + QSERDES_DP_PHY_CFG);
- writel(0x09, qmp->dp_pcs + QSERDES_DP_PHY_CFG);
+ writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
+ writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
+ writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
+ writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
writel(0x20, qmp->dp_serdes + QSERDES_V4_COM_RESETSM_CNTRL);
@@ -1582,16 +1582,16 @@ static int qmp_v45_configure_dp_phy(struct qmp_combo *qmp)
10000))
return -ETIMEDOUT;
- writel(0x19, qmp->dp_pcs + QSERDES_DP_PHY_CFG);
+ writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
- if (readl_poll_timeout(qmp->dp_pcs + QSERDES_V4_DP_PHY_STATUS,
+ if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V4_DP_PHY_STATUS,
status,
((status & BIT(0)) > 0),
500,
10000))
return -ETIMEDOUT;
- if (readl_poll_timeout(qmp->dp_pcs + QSERDES_V4_DP_PHY_STATUS,
+ if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V4_DP_PHY_STATUS,
status,
((status & BIT(1)) > 0),
500,
@@ -1640,11 +1640,11 @@ static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp)
writel(drvr1_en, qmp->dp_tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
writel(bias1_en, qmp->dp_tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
- writel(0x18, qmp->dp_pcs + QSERDES_DP_PHY_CFG);
+ writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
udelay(2000);
- writel(0x19, qmp->dp_pcs + QSERDES_DP_PHY_CFG);
+ writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
- if (readl_poll_timeout(qmp->dp_pcs + QSERDES_V4_DP_PHY_STATUS,
+ if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V4_DP_PHY_STATUS,
status,
((status & BIT(1)) > 0),
500,
@@ -1697,11 +1697,11 @@ static int qmp_v5_configure_dp_phy(struct qmp_combo *qmp)
writel(drvr1_en, qmp->dp_tx2 + QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN);
writel(bias1_en, qmp->dp_tx2 + QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN);
- writel(0x18, qmp->dp_pcs + QSERDES_DP_PHY_CFG);
+ writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
udelay(2000);
- writel(0x19, qmp->dp_pcs + QSERDES_DP_PHY_CFG);
+ writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
- if (readl_poll_timeout(qmp->dp_pcs + QSERDES_V4_DP_PHY_STATUS,
+ if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V4_DP_PHY_STATUS,
status,
((status & BIT(1)) > 0),
500,
@@ -1733,7 +1733,7 @@ static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp)
qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
val = cfg1_settings[qmp->dp_aux_cfg];
- writel(val, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG1);
+ writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
return 0;
}
@@ -1906,7 +1906,7 @@ static int qmp_combo_dp_power_off(struct phy *phy)
struct qmp_combo *qmp = phy_get_drvdata(phy);
/* Assert DP PHY power down */
- writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_pcs + QSERDES_DP_PHY_PD_CTL);
+ writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
return 0;
}
@@ -2463,15 +2463,16 @@ static int qmp_combo_parse_dt_lecacy_dp(struct qmp_combo *qmp, struct device_nod
* Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2;
* tx2 -> 3; rx2 -> 4
*
- * Note that only tx/tx2 and pcs are used by the DP implementation.
+ * Note that only tx/tx2 and pcs (dp_phy) are used by the DP
+ * implementation.
*/
qmp->dp_tx = devm_of_iomap(dev, np, 0, NULL);
if (IS_ERR(qmp->dp_tx))
return PTR_ERR(qmp->dp_tx);
- qmp->dp_pcs = devm_of_iomap(dev, np, 2, NULL);
- if (IS_ERR(qmp->dp_pcs))
- return PTR_ERR(qmp->dp_pcs);
+ qmp->dp_dp_phy = devm_of_iomap(dev, np, 2, NULL);
+ if (IS_ERR(qmp->dp_dp_phy))
+ return PTR_ERR(qmp->dp_dp_phy);
qmp->dp_tx2 = devm_of_iomap(dev, np, 3, NULL);
if (IS_ERR(qmp->dp_tx2))
--
2.37.4
On 21-11-22, 09:50, Johan Hovold wrote:
> This series fixes the USB-DP PHY devicetree binding for SC8280XP and
> adds support for the new updated binding to the driver.
>
> As the full series including the preparatory parts is over forty patches
> and I've been posting this in three parts of which this is the last one.
> In an effort to get all of these into 6.2, I've also submitted all three
> series before waiting for the previous ones to be applied. Parts one and
> two can be found here:
>
> https://lore.kernel.org/lkml/[email protected]/
> https://lore.kernel.org/lkml/[email protected]/
>
> This last series adds a new binding for SC8280XP that drops the legacy
> child node and the (incomplete) description of register subregions.
>
> As the current bindings are both incomplete and incorrect it may be
> a good idea to update also the other platforms currently supported by
> this driver to the new binding scheme. The driver can support both
> schemes during a transition period before removing the corresponding
> code (dt parsing and clock-provider registration).
Applied 1-13, thanks
--
~Vinod
On Mon, 21 Nov 2022 09:50:43 +0100, Johan Hovold wrote:
> This series fixes the USB-DP PHY devicetree binding for SC8280XP and
> adds support for the new updated binding to the driver.
>
> As the full series including the preparatory parts is over forty patches
> and I've been posting this in three parts of which this is the last one.
> In an effort to get all of these into 6.2, I've also submitted all three
> series before waiting for the previous ones to be applied. Parts one and
> two can be found here:
>
> [...]
Applied, thanks!
[14/15] arm64: dts: qcom: sc8280xp: fix primary USB-DP PHY reset
commit: ee4e530bdde29a69c58656a919545251a782674e
[15/15] arm64: dts: qcom: sc8280xp: fix USB-DP PHY nodes
commit: 721c0d68c0f882b6358102b52961ff6eb601839c
Best regards,
--
Bjorn Andersson <[email protected]>