From: Aswath Govindraju <[email protected]>
Add PCIe1 RC device tree node for the single PCIe instance present on
the j721s2.
Reviewed-by: Siddharth Vadapalli <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
Signed-off-by: Vignesh Raghavendra <[email protected]>
Signed-off-by: Matt Ranostay <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 41 ++++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index 2858ba589d54..27631ef32bf5 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -841,6 +841,47 @@ serdes0: serdes@5060000 {
};
};
+ pcie1_rc: pcie@2910000 {
+ compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
+ reg = <0x00 0x02910000 0x00 0x1000>,
+ <0x00 0x02917000 0x00 0x400>,
+ <0x00 0x0d800000 0x00 0x00800000>,
+ <0x00 0x18000000 0x00 0x00001000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
+ device_type = "pci";
+ ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
+ max-link-speed = <3>;
+ num-lanes = <4>;
+ power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 276 41>;
+ clock-names = "fck";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0xff>;
+ vendor-id = <0x104c>;
+ device-id = <0xb013>;
+ msi-map = <0x0 &gic_its 0x0 0x10000>;
+ dma-coherent;
+ ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
+ <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
+ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */
+ <0 0 0 2 &pcie1_intc 0>, /* INT B */
+ <0 0 0 3 &pcie1_intc 0>, /* INT C */
+ <0 0 0 4 &pcie1_intc 0>; /* INT D */
+
+ pcie1_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 324 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
+
main_mcan0: can@2701000 {
compatible = "bosch,m_can";
reg = <0x00 0x02701000 0x00 0x200>,
--
2.38.GIT
On 11/22/22 4:16 AM, Matt Ranostay wrote:
> From: Aswath Govindraju <[email protected]>
>
> Add PCIe1 RC device tree node for the single PCIe instance present on
> the j721s2.
>
> Reviewed-by: Siddharth Vadapalli <[email protected]>
> Signed-off-by: Aswath Govindraju <[email protected]>
> Signed-off-by: Vignesh Raghavendra <[email protected]>
> Signed-off-by: Matt Ranostay <[email protected]>
> ---
> arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 41 ++++++++++++++++++++++
> 1 file changed, 41 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> index 2858ba589d54..27631ef32bf5 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> @@ -841,6 +841,47 @@ serdes0: serdes@5060000 {
> };
> };
>
> + pcie1_rc: pcie@2910000 {
NIT: Not sure we need to call this "_rc", and "1", 0 index these names for
consistency, "pcie0".
> + compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
> + reg = <0x00 0x02910000 0x00 0x1000>,
> + <0x00 0x02917000 0x00 0x400>,
> + <0x00 0x0d800000 0x00 0x00800000>,
> + <0x00 0x18000000 0x00 0x00001000>;
> + reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
> + interrupt-names = "link_state";
> + interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
> + device_type = "pci";
> + ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
> + max-link-speed = <3>;
> + num-lanes = <4>;
> + power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 276 41>;
> + clock-names = "fck";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + bus-range = <0x0 0xff>;
> + vendor-id = <0x104c>;
> + device-id = <0xb013>;
> + msi-map = <0x0 &gic_its 0x0 0x10000>;
> + dma-coherent;
> + ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
> + <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
> + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
> + #interrupt-cells = <1>;
Is this node the interrupt controller or is it the "interrupt-controller"?
Actually, what is that node? I don't see it in the binding docs..
Andrew
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */
> + <0 0 0 2 &pcie1_intc 0>, /* INT B */
> + <0 0 0 3 &pcie1_intc 0>, /* INT C */
> + <0 0 0 4 &pcie1_intc 0>; /* INT D */
> +
> + pcie1_intc: interrupt-controller {
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + interrupt-parent = <&gic500>;
> + interrupts = <GIC_SPI 324 IRQ_TYPE_EDGE_RISING>;
> + };
> + };
> +
> main_mcan0: can@2701000 {
> compatible = "bosch,m_can";
> reg = <0x00 0x02701000 0x00 0x200>,
Hello Achal,
On 17/01/23 14:53, Achal Verma wrote:
> Tue, Nov 29, 2022 at 11:53:46AM -0600, Andrew Davis wrote:
>> On 11/22/22 4:16 AM, Matt Ranostay wrote:
>>> From: Aswath Govindraju <[email protected]>
>>>
>>> Add PCIe1 RC device tree node for the single PCIe instance present on
>>> the j721s2.
>>>
>>> Reviewed-by: Siddharth Vadapalli <[email protected]>
>>> Signed-off-by: Aswath Govindraju <[email protected]>
>>> Signed-off-by: Vignesh Raghavendra <[email protected]>
>>> Signed-off-by: Matt Ranostay <[email protected]>
>>> ---
>>> arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 41 ++++++++++++++++++++++
>>> 1 file changed, 41 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
>>> index 2858ba589d54..27631ef32bf5 100644
>>> --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
>>> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
>>> @@ -841,6 +841,47 @@ serdes0: serdes@5060000 {
>>> };
>>> };
>>> + pcie1_rc: pcie@2910000 {
>>
>> NIT: Not sure we need to call this "_rc", and "1", 0 index these names for
>> consistency, "pcie0".
>
> Sure, I will name this node as "pcie0_rc" in next patch and "_rc" is because it can be used in endpoint mode too for which "pcie0_ep" node can be added in future.
The naming is based on the PCIe instance documented in the Technical Reference
Manual (TRM). For example, consider J7200 SoC which has "pcie1_rc" even though
it has no "pcie0_rc". This convention is based on the numbering used in the TRM.
Regards,
Siddharth.