From: Aswath Govindraju <[email protected]>
x1 lane PCIe slot in the common processor board is enabled and connected to
J721S2 SOM. Add PCIe DT node in common processor board to reflect the
same.
Reviewed-by: Siddharth Vadapalli <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
Signed-off-by: Vignesh Raghavendra <[email protected]>
Signed-off-by: Matt Ranostay <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
index 0503e690cfaf..561d70cdee9b 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
@@ -374,6 +374,13 @@ flash@0{
};
};
+&pcie1_rc {
+ reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
+ phys = <&serdes0_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <1>;
+};
+
&mcu_mcan0 {
status = "okay";
pinctrl-names = "default";
--
2.38.GIT