Unlike the old design that the register setting of the TACH should based
on the configure of the PWM. In ast26xx, the dependency between pwm and
tach controller is eliminated and becomes a separate hardware block. One
is used to provide pwm output and another is used to monitor the frequency
of the input. Therefore, this patch serials implements them by writing the
two driver "pwm-aspeed-ast2600.c" and "tach-aspeed-ast2600.c". The former
is following the pwm subsystem which can apply the existed driver to
controller the fan(pwm-fan.c), beeper(pwm-beeper.c) and so on. The latter
is following the sysfs interface of hwmon to creat the node for fan
monitor.
Changes since v3:
- pwm
- Remove unnecessary include header
- Fix warning Prefer "GPL" over "GPL v2"
- tach:
- Remove the paremeter min_rpm and max_rpm and return the tach value
directly without any polling or delay.
- Fix warning Prefer "GPL" over "GPL v2"
- dt-binding:
- Replace underscore in node names with dashes
- Split per subsystem
Changes since v2:
- pwm:
- Use devm_* api to simplify the error cleanup
- Fix the multi-line alignment problem
- tach:
- Add tach-aspeed-ast2600 to index.rst
- Fix the multi-line alignment problem
- Remove the tach enable/disable when read the rpm
- Fix some coding format issue
Changes since v1:
- tach:
- Add the document tach-aspeed-ast2600.rst
- Use devm_* api to simplify the error cleanup.
- Change hwmon register api to devm_hwmon_device_register_with_info
Billy Tsai (5):
dt-bindings: mfd: Add aspeed pwm-tach binding
dt-bindings: pwm: Add bindings for aspeed pwm controller
dt-bindings: hwmon: Add bindings for aspeed tach controller
pwm: Add Aspeed ast2600 PWM support
hwmon: Add Aspeed ast2600 TACH support
.../bindings/hwmon/aspeed,ast2600-tach.yaml | 36 ++
.../bindings/mfd/aspeed,ast2600-pwm-tach.yaml | 73 ++++
.../bindings/pwm/aspeed,ast2600-pwm.yaml | 54 +++
Documentation/hwmon/index.rst | 1 +
Documentation/hwmon/tach-aspeed-ast2600.rst | 24 ++
drivers/hwmon/Kconfig | 9 +
drivers/hwmon/Makefile | 1 +
drivers/hwmon/tach-aspeed-ast2600.c | 399 ++++++++++++++++++
drivers/pwm/Kconfig | 10 +
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-aspeed-ast2600.c | 318 ++++++++++++++
11 files changed, 926 insertions(+)
create mode 100644 Documentation/devicetree/bindings/hwmon/aspeed,ast2600-tach.yaml
create mode 100644 Documentation/devicetree/bindings/mfd/aspeed,ast2600-pwm-tach.yaml
create mode 100644 Documentation/devicetree/bindings/pwm/aspeed,ast2600-pwm.yaml
create mode 100644 Documentation/hwmon/tach-aspeed-ast2600.rst
create mode 100644 drivers/hwmon/tach-aspeed-ast2600.c
create mode 100644 drivers/pwm/pwm-aspeed-ast2600.c
--
2.25.1
Add the support of PWM controller which can be found at aspeed ast2600
soc. The pwm supoorts up to 16 channels and it's part function of
multi-function device "pwm-tach controller".
Signed-off-by: Billy Tsai <[email protected]>
Reviewed-by: Uwe Kleine-König <[email protected]>
Reported-by: kernel test robot <[email protected]>
---
drivers/pwm/Kconfig | 10 +
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-aspeed-ast2600.c | 318 +++++++++++++++++++++++++++++++
3 files changed, 329 insertions(+)
create mode 100644 drivers/pwm/pwm-aspeed-ast2600.c
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 60d13a949bc5..54915185d918 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -51,6 +51,16 @@ config PWM_AB8500
To compile this driver as a module, choose M here: the module
will be called pwm-ab8500.
+config PWM_ASPEED_AST2600
+ tristate "Aspeed ast2600 PWM support"
+ depends on ARCH_ASPEED || COMPILE_TEST
+ depends on HAVE_CLK && HAS_IOMEM
+ help
+ This driver provides support for Aspeed ast2600 PWM controllers.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-aspeed-ast2600.
+
config PWM_ATMEL
tristate "Atmel PWM support"
depends on ARCH_AT91 || COMPILE_TEST
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 7bf1a29f02b8..5169c34056e6 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -2,6 +2,7 @@
obj-$(CONFIG_PWM) += core.o
obj-$(CONFIG_PWM_SYSFS) += sysfs.o
obj-$(CONFIG_PWM_AB8500) += pwm-ab8500.o
+obj-$(CONFIG_PWM_ASPEED_AST2600) += pwm-aspeed-ast2600.o
obj-$(CONFIG_PWM_ATMEL) += pwm-atmel.o
obj-$(CONFIG_PWM_ATMEL_HLCDC_PWM) += pwm-atmel-hlcdc.o
obj-$(CONFIG_PWM_ATMEL_TCB) += pwm-atmel-tcb.o
diff --git a/drivers/pwm/pwm-aspeed-ast2600.c b/drivers/pwm/pwm-aspeed-ast2600.c
new file mode 100644
index 000000000000..2c22aff18624
--- /dev/null
+++ b/drivers/pwm/pwm-aspeed-ast2600.c
@@ -0,0 +1,318 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2021 Aspeed Technology Inc.
+ *
+ * PWM controller driver for Aspeed ast2600 SoCs.
+ * This drivers doesn't support earlier version of the IP.
+ *
+ * The hardware operates in time quantities of length
+ * Q := (DIV_L + 1) << DIV_H / input-clk
+ * The length of a PWM period is (DUTY_CYCLE_PERIOD + 1) * Q.
+ * The maximal value for DUTY_CYCLE_PERIOD is used here to provide
+ * a fine grained selection for the duty cycle.
+ *
+ * This driver uses DUTY_CYCLE_RISING_POINT = 0, so from the start of a
+ * period the output is active until DUTY_CYCLE_FALLING_POINT * Q. Note
+ * that if DUTY_CYCLE_RISING_POINT = DUTY_CYCLE_FALLING_POINT the output is
+ * always active.
+ *
+ * Register usage:
+ * PIN_ENABLE: When it is unset the pwm controller will emit inactive level to the external.
+ * Use to determine whether the PWM channel is enabled or disabled
+ * CLK_ENABLE: When it is unset the pwm controller will assert the duty counter reset and
+ * emit inactive level to the PIN_ENABLE mux after that the driver can still change the pwm period
+ * and duty and the value will apply when CLK_ENABLE be set again.
+ * Use to determine whether duty_cycle bigger than 0.
+ * PWM_ASPEED_CTRL_INVERSE: When it is toggled the output value will inverse immediately.
+ * PWM_ASPEED_DUTY_CYCLE_FALLING_POINT/PWM_ASPEED_DUTY_CYCLE_RISING_POINT: When these two
+ * values are equal it means the duty cycle = 100%.
+ *
+ * The glitch may generate at:
+ * - Enabled changing when the duty_cycle bigger than 0% and less than 100%.
+ * - Polarity changing when the duty_cycle bigger than 0% and less than 100%.
+ *
+ * Limitations:
+ * - When changing both duty cycle and period, we cannot prevent in
+ * software that the output might produce a period with mixed
+ * settings.
+ * - Disabling the PWM doesn't complete the current period.
+ *
+ * Improvements:
+ * - When only changing one of duty cycle or period, our pwm controller will not
+ * generate the glitch, the configure will change at next cycle of pwm.
+ * This improvement can disable/enable through PWM_ASPEED_CTRL_DUTY_SYNC_DISABLE.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/math64.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/pwm.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/sysfs.h>
+
+/* The channel number of Aspeed pwm controller */
+#define PWM_ASPEED_NR_PWMS 16
+/* PWM Control Register */
+#define PWM_ASPEED_CTRL(ch) ((ch) * 0x10 + 0x00)
+#define PWM_ASPEED_CTRL_LOAD_SEL_RISING_AS_WDT BIT(19)
+#define PWM_ASPEED_CTRL_DUTY_LOAD_AS_WDT_ENABLE BIT(18)
+#define PWM_ASPEED_CTRL_DUTY_SYNC_DISABLE BIT(17)
+#define PWM_ASPEED_CTRL_CLK_ENABLE BIT(16)
+#define PWM_ASPEED_CTRL_LEVEL_OUTPUT BIT(15)
+#define PWM_ASPEED_CTRL_INVERSE BIT(14)
+#define PWM_ASPEED_CTRL_OPEN_DRAIN_ENABLE BIT(13)
+#define PWM_ASPEED_CTRL_PIN_ENABLE BIT(12)
+#define PWM_ASPEED_CTRL_CLK_DIV_H GENMASK(11, 8)
+#define PWM_ASPEED_CTRL_CLK_DIV_L GENMASK(7, 0)
+
+/* PWM Duty Cycle Register */
+#define PWM_ASPEED_DUTY_CYCLE(ch) ((ch) * 0x10 + 0x04)
+#define PWM_ASPEED_DUTY_CYCLE_PERIOD GENMASK(31, 24)
+#define PWM_ASPEED_DUTY_CYCLE_POINT_AS_WDT GENMASK(23, 16)
+#define PWM_ASPEED_DUTY_CYCLE_FALLING_POINT GENMASK(15, 8)
+#define PWM_ASPEED_DUTY_CYCLE_RISING_POINT GENMASK(7, 0)
+
+/* PWM fixed value */
+#define PWM_ASPEED_FIXED_PERIOD FIELD_MAX(PWM_ASPEED_DUTY_CYCLE_PERIOD)
+
+struct aspeed_pwm_data {
+ struct pwm_chip chip;
+ struct clk *clk;
+ struct regmap *regmap;
+ struct reset_control *reset;
+};
+
+static inline struct aspeed_pwm_data *
+aspeed_pwm_chip_to_data(struct pwm_chip *chip)
+{
+ return container_of(chip, struct aspeed_pwm_data, chip);
+}
+
+static void aspeed_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
+ struct pwm_state *state)
+{
+ struct device *dev = chip->dev;
+ struct aspeed_pwm_data *priv = aspeed_pwm_chip_to_data(chip);
+ u32 hwpwm = pwm->hwpwm;
+ bool polarity, pin_en, clk_en;
+ u32 duty_pt, val;
+ unsigned long rate;
+ u64 div_h, div_l, duty_cycle_period, dividend;
+
+ regmap_read(priv->regmap, PWM_ASPEED_CTRL(hwpwm), &val);
+ polarity = FIELD_GET(PWM_ASPEED_CTRL_INVERSE, val);
+ pin_en = FIELD_GET(PWM_ASPEED_CTRL_PIN_ENABLE, val);
+ clk_en = FIELD_GET(PWM_ASPEED_CTRL_CLK_ENABLE, val);
+ div_h = FIELD_GET(PWM_ASPEED_CTRL_CLK_DIV_H, val);
+ div_l = FIELD_GET(PWM_ASPEED_CTRL_CLK_DIV_L, val);
+ regmap_read(priv->regmap, PWM_ASPEED_DUTY_CYCLE(hwpwm), &val);
+ duty_pt = FIELD_GET(PWM_ASPEED_DUTY_CYCLE_FALLING_POINT, val);
+ duty_cycle_period = FIELD_GET(PWM_ASPEED_DUTY_CYCLE_PERIOD, val);
+
+ rate = clk_get_rate(priv->clk);
+
+ /*
+ * This multiplication doesn't overflow, the upper bound is
+ * 1000000000 * 256 * 256 << 15 = 0x1dcd650000000000
+ */
+ dividend = (u64)NSEC_PER_SEC * (div_l + 1) * (duty_cycle_period + 1)
+ << div_h;
+ state->period = DIV_ROUND_UP_ULL(dividend, rate);
+
+ if (clk_en && duty_pt) {
+ dividend = (u64)NSEC_PER_SEC * (div_l + 1) * duty_pt
+ << div_h;
+ state->duty_cycle = DIV_ROUND_UP_ULL(dividend, rate);
+ } else {
+ state->duty_cycle = clk_en ? state->period : 0;
+ }
+ state->polarity = polarity ? PWM_POLARITY_INVERSED : PWM_POLARITY_NORMAL;
+ state->enabled = pin_en;
+ dev_dbg(dev, "get period: %lldns, duty_cycle: %lldns", state->period,
+ state->duty_cycle);
+}
+
+static int aspeed_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+ const struct pwm_state *state)
+{
+ struct device *dev = chip->dev;
+ struct aspeed_pwm_data *priv = aspeed_pwm_chip_to_data(chip);
+ u32 hwpwm = pwm->hwpwm, duty_pt;
+ unsigned long rate;
+ u64 div_h, div_l, divisor, expect_period;
+ bool clk_en;
+
+ rate = clk_get_rate(priv->clk);
+ expect_period = min(div64_u64(ULLONG_MAX, (u64)rate), state->period);
+ dev_dbg(dev, "expect period: %lldns, duty_cycle: %lldns", expect_period,
+ state->duty_cycle);
+ /*
+ * Pick the smallest value for div_h so that div_l can be the biggest
+ * which results in a finer resolution near the target period value.
+ */
+ divisor = (u64)NSEC_PER_SEC * (PWM_ASPEED_FIXED_PERIOD + 1) *
+ (FIELD_MAX(PWM_ASPEED_CTRL_CLK_DIV_L) + 1);
+ div_h = order_base_2(DIV64_U64_ROUND_UP(rate * expect_period, divisor));
+ if (div_h > 0xf)
+ div_h = 0xf;
+
+ divisor = ((u64)NSEC_PER_SEC * (PWM_ASPEED_FIXED_PERIOD + 1)) << div_h;
+ div_l = div64_u64(rate * expect_period, divisor);
+
+ if (div_l == 0)
+ return -ERANGE;
+
+ div_l -= 1;
+
+ if (div_l > 255)
+ div_l = 255;
+
+ dev_dbg(dev, "clk source: %ld div_h %lld, div_l : %lld\n", rate, div_h,
+ div_l);
+ /* duty_pt = duty_cycle * (PERIOD + 1) / period */
+ duty_pt = div64_u64(state->duty_cycle * rate,
+ (u64)NSEC_PER_SEC * (div_l + 1) << div_h);
+ dev_dbg(dev, "duty_cycle = %lld, duty_pt = %d\n", state->duty_cycle,
+ duty_pt);
+
+ /*
+ * Fixed DUTY_CYCLE_PERIOD to its max value to get a
+ * fine-grained resolution for duty_cycle at the expense of a
+ * coarser period resolution.
+ */
+ regmap_update_bits(priv->regmap, PWM_ASPEED_DUTY_CYCLE(hwpwm),
+ PWM_ASPEED_DUTY_CYCLE_PERIOD,
+ FIELD_PREP(PWM_ASPEED_DUTY_CYCLE_PERIOD,
+ PWM_ASPEED_FIXED_PERIOD));
+ if (duty_pt == 0) {
+ /* emit inactive level and assert the duty counter reset */
+ clk_en = 0;
+ } else {
+ clk_en = 1;
+ if (duty_pt >= (PWM_ASPEED_FIXED_PERIOD + 1))
+ duty_pt = 0;
+ regmap_update_bits(priv->regmap, PWM_ASPEED_DUTY_CYCLE(hwpwm),
+ PWM_ASPEED_DUTY_CYCLE_RISING_POINT |
+ PWM_ASPEED_DUTY_CYCLE_FALLING_POINT,
+ FIELD_PREP(PWM_ASPEED_DUTY_CYCLE_FALLING_POINT, duty_pt));
+ }
+
+ regmap_update_bits(priv->regmap, PWM_ASPEED_CTRL(hwpwm),
+ PWM_ASPEED_CTRL_CLK_DIV_H | PWM_ASPEED_CTRL_CLK_DIV_L |
+ PWM_ASPEED_CTRL_PIN_ENABLE | PWM_ASPEED_CTRL_CLK_ENABLE |
+ PWM_ASPEED_CTRL_INVERSE,
+ FIELD_PREP(PWM_ASPEED_CTRL_CLK_DIV_H, div_h) |
+ FIELD_PREP(PWM_ASPEED_CTRL_CLK_DIV_L, div_l) |
+ FIELD_PREP(PWM_ASPEED_CTRL_PIN_ENABLE, state->enabled) |
+ FIELD_PREP(PWM_ASPEED_CTRL_CLK_ENABLE, clk_en) |
+ FIELD_PREP(PWM_ASPEED_CTRL_INVERSE, state->polarity));
+ return 0;
+}
+
+static const struct pwm_ops aspeed_pwm_ops = {
+ .apply = aspeed_pwm_apply,
+ .get_state = aspeed_pwm_get_state,
+ .owner = THIS_MODULE,
+};
+
+static void aspeed_pwm_reset_assert(void *data)
+{
+ struct reset_control *rst = data;
+
+ reset_control_assert(rst);
+}
+
+static void aspeed_pwm_chip_remove(void *data)
+{
+ struct pwm_chip *chip = data;
+
+ pwmchip_remove(chip);
+}
+
+static int aspeed_pwm_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ int ret;
+ struct aspeed_pwm_data *priv;
+ struct device_node *np;
+ struct platform_device *parent_dev;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ np = pdev->dev.parent->of_node;
+ if (!of_device_is_compatible(np, "aspeed,ast2600-pwm-tach"))
+ return dev_err_probe(dev, -ENODEV,
+ "Unsupported pwm device binding\n");
+
+ priv->regmap = syscon_node_to_regmap(np);
+ if (IS_ERR(priv->regmap))
+ return dev_err_probe(dev, PTR_ERR(priv->regmap),
+ "Couldn't get regmap\n");
+
+ parent_dev = of_find_device_by_node(np);
+ priv->clk = devm_clk_get_enabled(&parent_dev->dev, NULL);
+ if (IS_ERR(priv->clk))
+ return dev_err_probe(dev, PTR_ERR(priv->clk),
+ "Couldn't get clock\n");
+
+ priv->reset = devm_reset_control_get_shared(&parent_dev->dev, NULL);
+ if (IS_ERR(priv->reset))
+ return dev_err_probe(dev, PTR_ERR(priv->reset),
+ "Couldn't get reset control\n");
+
+ ret = reset_control_deassert(priv->reset);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "Couldn't deassert reset control\n");
+
+ ret = devm_add_action_or_reset(dev, aspeed_pwm_reset_assert,
+ priv->reset);
+ if (ret)
+ return ret;
+
+ priv->chip.dev = dev;
+ priv->chip.ops = &aspeed_pwm_ops;
+ priv->chip.npwm = PWM_ASPEED_NR_PWMS;
+
+ ret = pwmchip_add(&priv->chip);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "Failed to add PWM chip\n");
+ ret = devm_add_action_or_reset(dev, aspeed_pwm_chip_remove,
+ &priv->chip);
+ if (ret)
+ return ret;
+ return 0;
+}
+
+static const struct of_device_id of_pwm_match_table[] = {
+ {
+ .compatible = "aspeed,ast2600-pwm",
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, of_pwm_match_table);
+
+static struct platform_driver aspeed_pwm_driver = {
+ .probe = aspeed_pwm_probe,
+ .driver = {
+ .name = "aspeed-pwm",
+ .of_match_table = of_pwm_match_table,
+ },
+};
+
+module_platform_driver(aspeed_pwm_driver);
+
+MODULE_AUTHOR("Billy Tsai <[email protected]>");
+MODULE_DESCRIPTION("Aspeed ast2600 PWM device driver");
+MODULE_LICENSE("GPL");
--
2.25.1
Add the support of Tachometer which can use to monitor the frequency of
the input. The tach supports up to 16 channels and it's part function of
multi-function device "pwm-tach controller".
Signed-off-by: Billy Tsai <[email protected]>
Reported-by: kernel test robot <[email protected]>
---
Documentation/hwmon/index.rst | 1 +
Documentation/hwmon/tach-aspeed-ast2600.rst | 24 ++
drivers/hwmon/Kconfig | 9 +
drivers/hwmon/Makefile | 1 +
drivers/hwmon/tach-aspeed-ast2600.c | 399 ++++++++++++++++++++
5 files changed, 434 insertions(+)
create mode 100644 Documentation/hwmon/tach-aspeed-ast2600.rst
create mode 100644 drivers/hwmon/tach-aspeed-ast2600.c
diff --git a/Documentation/hwmon/index.rst b/Documentation/hwmon/index.rst
index c1d11cf13eef..8aed4c42ca89 100644
--- a/Documentation/hwmon/index.rst
+++ b/Documentation/hwmon/index.rst
@@ -193,6 +193,7 @@ Hardware Monitoring Kernel Drivers
sparx5-temp
stpddc60
sy7636a-hwmon
+ tach-aspeed-ast2600
tc654
tc74
thmc50
diff --git a/Documentation/hwmon/tach-aspeed-ast2600.rst b/Documentation/hwmon/tach-aspeed-ast2600.rst
new file mode 100644
index 000000000000..4f9501b783a1
--- /dev/null
+++ b/Documentation/hwmon/tach-aspeed-ast2600.rst
@@ -0,0 +1,24 @@
+Kernel driver tach-aspeed-ast2600
+==============================
+
+Supported chips:
+ ASPEED AST2600
+
+Authors:
+ <[email protected]>
+
+Description:
+------------
+This driver implements support for ASPEED AST2600 Fan Tacho controller.
+The controller supports up to 16 tachometer inputs.
+
+The driver provides the following sensor accesses in sysfs:
+=============== ======= =====================================================
+fanX_input ro provide current fan rotation value in RPM as reported
+ by the fan to the device.
+fanX_div rw Fan divisor: Supported value are power of 4 (1, 4, 16
+ 64, ... 4194304)
+ The larger divisor, the less rpm accuracy and the less
+ affected by fan signal glitch.
+fanX_pulses rw Fan pulses per resolution.
+=============== ======= ======================================================
diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index 7ac3daaf59ce..3196087a7b3e 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -403,6 +403,15 @@ config SENSORS_ASPEED
This driver can also be built as a module. If so, the module
will be called aspeed_pwm_tacho.
+config SENSORS_TACH_ASPEED_AST2600
+ tristate "ASPEED ast2600 Tachometer support"
+ select REGMAP
+ help
+ This driver provides support for Aspeed ast2600 Tachometer.
+
+ To compile this driver as a module, choose M here: the module
+ will be called tach-aspeed-ast2600.
+
config SENSORS_ATXP1
tristate "Attansic ATXP1 VID controller"
depends on I2C
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index 11d076cad8a2..50a139c7c4ca 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -53,6 +53,7 @@ obj-$(CONFIG_SENSORS_ARM_SCMI) += scmi-hwmon.o
obj-$(CONFIG_SENSORS_ARM_SCPI) += scpi-hwmon.o
obj-$(CONFIG_SENSORS_AS370) += as370-hwmon.o
obj-$(CONFIG_SENSORS_ASC7621) += asc7621.o
+obj-$(CONFIG_SENSORS_TACH_ASPEED_AST2600) += tach-aspeed-ast2600.o
obj-$(CONFIG_SENSORS_ASPEED) += aspeed-pwm-tacho.o
obj-$(CONFIG_SENSORS_ATXP1) += atxp1.o
obj-$(CONFIG_SENSORS_AXI_FAN_CONTROL) += axi-fan-control.o
diff --git a/drivers/hwmon/tach-aspeed-ast2600.c b/drivers/hwmon/tach-aspeed-ast2600.c
new file mode 100644
index 000000000000..2b8dd5eeb6ec
--- /dev/null
+++ b/drivers/hwmon/tach-aspeed-ast2600.c
@@ -0,0 +1,399 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) ASPEED Technology Inc.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/hwmon.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/sysfs.h>
+
+/* The channel number of Aspeed tach controller */
+#define TACH_ASPEED_NR_TACHS 16
+/* TACH Control Register */
+#define TACH_ASPEED_CTRL(ch) (((ch) * 0x10) + 0x08)
+#define TACH_ASPEED_IER BIT(31)
+#define TACH_ASPEED_INVERS_LIMIT BIT(30)
+#define TACH_ASPEED_LOOPBACK BIT(29)
+#define TACH_ASPEED_ENABLE BIT(28)
+#define TACH_ASPEED_DEBOUNCE_MASK GENMASK(27, 26)
+#define TACH_ASPEED_DEBOUNCE_BIT 26
+#define TACH_ASPEED_IO_EDGE_MASK GENMASK(25, 24)
+#define TACH_ASPEED_IO_EDGE_BIT 24
+#define TACH_ASPEED_CLK_DIV_T_MASK GENMASK(23, 20)
+#define TACH_ASPEED_CLK_DIV_BIT 20
+#define TACH_ASPEED_THRESHOLD_MASK GENMASK(19, 0)
+/* [27:26] */
+#define DEBOUNCE_3_CLK 0x00
+#define DEBOUNCE_2_CLK 0x01
+#define DEBOUNCE_1_CLK 0x02
+#define DEBOUNCE_0_CLK 0x03
+/* [25:24] */
+#define F2F_EDGES 0x00
+#define R2R_EDGES 0x01
+#define BOTH_EDGES 0x02
+/* [23:20] */
+/* divisor = 4 to the nth power, n = register value */
+#define DEFAULT_TACH_DIV 1024
+#define DIV_TO_REG(divisor) (ilog2(divisor) >> 1)
+
+/* TACH Status Register */
+#define TACH_ASPEED_STS(ch) (((ch) * 0x10) + 0x0C)
+
+/*PWM_TACH_STS */
+#define TACH_ASPEED_ISR BIT(31)
+#define TACH_ASPEED_PWM_OUT BIT(25)
+#define TACH_ASPEED_PWM_OEN BIT(24)
+#define TACH_ASPEED_DEB_INPUT BIT(23)
+#define TACH_ASPEED_RAW_INPUT BIT(22)
+#define TACH_ASPEED_VALUE_UPDATE BIT(21)
+#define TACH_ASPEED_FULL_MEASUREMENT BIT(20)
+#define TACH_ASPEED_VALUE_MASK GENMASK(19, 0)
+/**********************************************************
+ * Software setting
+ *********************************************************/
+#define DEFAULT_FAN_PULSE_PR 2
+struct aspeed_tach_channel_params {
+ int limited_inverse;
+ u16 threshold;
+ u8 tach_edge;
+ u8 tach_debounce;
+ u8 pulse_pr;
+ u32 divisor;
+ u32 sample_period; /* unit is us */
+ u32 polling_period; /* unit is us */
+};
+
+struct aspeed_tach_data {
+ struct device *dev;
+ struct regmap *regmap;
+ struct clk *clk;
+ struct reset_control *reset;
+ bool tach_present[TACH_ASPEED_NR_TACHS];
+ struct aspeed_tach_channel_params *tach_channel;
+};
+
+static void aspeed_tach_ch_enable(struct aspeed_tach_data *priv, u8 tach_ch,
+ bool enable)
+{
+ if (enable)
+ regmap_set_bits(priv->regmap, TACH_ASPEED_CTRL(tach_ch),
+ TACH_ASPEED_ENABLE);
+ else
+ regmap_clear_bits(priv->regmap, TACH_ASPEED_CTRL(tach_ch),
+ TACH_ASPEED_ENABLE);
+}
+
+static u64 aspeed_tach_val_to_rpm(struct aspeed_tach_data *priv, u8 fan_tach_ch,
+ u32 tach_val)
+{
+ unsigned long clk_source;
+ u64 rpm;
+ u32 tach_div;
+
+ /*
+ * We need the mode to determine if the tach_val is double (from
+ * counting both edges).
+ */
+ if (priv->tach_channel[fan_tach_ch].tach_edge == BOTH_EDGES)
+ tach_val <<= 1;
+
+ tach_div = tach_val * (priv->tach_channel[fan_tach_ch].divisor) *
+ (priv->tach_channel[fan_tach_ch].pulse_pr);
+
+ clk_source = clk_get_rate(priv->clk);
+ dev_dbg(priv->dev, "clk %ld, tach_val %d , tach_div %d\n", clk_source,
+ tach_val, tach_div);
+
+ rpm = (u64)clk_source * 60;
+ do_div(rpm, tach_div);
+
+ return rpm;
+}
+
+static int aspeed_get_fan_tach_ch_rpm(struct aspeed_tach_data *priv,
+ u8 fan_tach_ch)
+{
+ u32 val;
+ u64 rpm;
+ int ret;
+
+ ret = regmap_read(priv->regmap, TACH_ASPEED_STS(fan_tach_ch), &val);
+
+ if (ret)
+ return ret;
+
+ if (!(val & TACH_ASPEED_FULL_MEASUREMENT))
+ return 0;
+ rpm = aspeed_tach_val_to_rpm(priv, fan_tach_ch,
+ val & TACH_ASPEED_VALUE_MASK);
+
+ return rpm;
+}
+
+static int aspeed_tach_hwmon_read(struct device *dev,
+ enum hwmon_sensor_types type, u32 attr,
+ int channel, long *val)
+{
+ struct aspeed_tach_data *priv = dev_get_drvdata(dev);
+ u32 reg_val;
+ int ret;
+
+ switch (attr) {
+ case hwmon_fan_input:
+ ret = aspeed_get_fan_tach_ch_rpm(priv, channel);
+ if (ret < 0)
+ return ret;
+ *val = ret;
+ break;
+ case hwmon_fan_div:
+ regmap_read(priv->regmap, TACH_ASPEED_CTRL(channel), ®_val);
+ reg_val = FIELD_GET(TACH_ASPEED_CLK_DIV_T_MASK, reg_val);
+ *val = BIT(reg_val << 1);
+ break;
+ case hwmon_fan_pulses:
+ *val = priv->tach_channel[channel].pulse_pr;
+ break;
+ default:
+ return -EOPNOTSUPP;
+ }
+ return 0;
+}
+
+static int aspeed_tach_hwmon_write(struct device *dev,
+ enum hwmon_sensor_types type, u32 attr,
+ int channel, long val)
+{
+ struct aspeed_tach_data *priv = dev_get_drvdata(dev);
+
+ switch (attr) {
+ case hwmon_fan_div:
+ if (!(is_power_of_2(val) && !(ilog2(val) % 2))) {
+ dev_err(dev,
+ "fan_div value %ld not supported. Only support power of 4\n",
+ val);
+ return -EINVAL;
+ }
+ priv->tach_channel[channel].divisor = val;
+ regmap_write_bits(priv->regmap, TACH_ASPEED_CTRL(channel),
+ TACH_ASPEED_CLK_DIV_T_MASK,
+ DIV_TO_REG(priv->tach_channel[channel].divisor)
+ << TACH_ASPEED_CLK_DIV_BIT);
+ break;
+ case hwmon_fan_pulses:
+ priv->tach_channel[channel].pulse_pr = val;
+ break;
+ default:
+ return -EOPNOTSUPP;
+ }
+
+ return 0;
+}
+
+static umode_t aspeed_tach_dev_is_visible(const void *drvdata,
+ enum hwmon_sensor_types type,
+ u32 attr, int channel)
+{
+ const struct aspeed_tach_data *priv = drvdata;
+
+ if (!priv->tach_present[channel])
+ return 0;
+ switch (attr) {
+ case hwmon_fan_input:
+ return 0444;
+ case hwmon_fan_div:
+ case hwmon_fan_pulses:
+ return 0644;
+ }
+ return 0;
+}
+
+static const struct hwmon_ops aspeed_tach_ops = {
+ .is_visible = aspeed_tach_dev_is_visible,
+ .read = aspeed_tach_hwmon_read,
+ .write = aspeed_tach_hwmon_write,
+};
+
+static const struct hwmon_channel_info *aspeed_tach_info[] = {
+ HWMON_CHANNEL_INFO(fan, HWMON_F_INPUT | HWMON_F_DIV | HWMON_F_PULSES,
+ HWMON_F_INPUT | HWMON_F_DIV | HWMON_F_PULSES,
+ HWMON_F_INPUT | HWMON_F_DIV | HWMON_F_PULSES,
+ HWMON_F_INPUT | HWMON_F_DIV | HWMON_F_PULSES,
+ HWMON_F_INPUT | HWMON_F_DIV | HWMON_F_PULSES,
+ HWMON_F_INPUT | HWMON_F_DIV | HWMON_F_PULSES,
+ HWMON_F_INPUT | HWMON_F_DIV | HWMON_F_PULSES,
+ HWMON_F_INPUT | HWMON_F_DIV | HWMON_F_PULSES,
+ HWMON_F_INPUT | HWMON_F_DIV | HWMON_F_PULSES,
+ HWMON_F_INPUT | HWMON_F_DIV | HWMON_F_PULSES,
+ HWMON_F_INPUT | HWMON_F_DIV | HWMON_F_PULSES,
+ HWMON_F_INPUT | HWMON_F_DIV | HWMON_F_PULSES,
+ HWMON_F_INPUT | HWMON_F_DIV | HWMON_F_PULSES,
+ HWMON_F_INPUT | HWMON_F_DIV | HWMON_F_PULSES,
+ HWMON_F_INPUT | HWMON_F_DIV | HWMON_F_PULSES,
+ HWMON_F_INPUT | HWMON_F_DIV | HWMON_F_PULSES),
+ NULL
+};
+
+static const struct hwmon_chip_info aspeed_tach_chip_info = {
+ .ops = &aspeed_tach_ops,
+ .info = aspeed_tach_info,
+};
+
+static void aspeed_create_fan_tach_channel(struct aspeed_tach_data *priv,
+ u32 tach_ch)
+{
+ priv->tach_present[tach_ch] = true;
+ priv->tach_channel[tach_ch].limited_inverse = 0;
+ regmap_write_bits(priv->regmap, TACH_ASPEED_CTRL(tach_ch),
+ TACH_ASPEED_INVERS_LIMIT,
+ priv->tach_channel[tach_ch].limited_inverse ?
+ TACH_ASPEED_INVERS_LIMIT :
+ 0);
+
+ priv->tach_channel[tach_ch].tach_debounce = DEBOUNCE_3_CLK;
+ regmap_write_bits(priv->regmap, TACH_ASPEED_CTRL(tach_ch),
+ TACH_ASPEED_DEBOUNCE_MASK,
+ priv->tach_channel[tach_ch].tach_debounce
+ << TACH_ASPEED_DEBOUNCE_BIT);
+
+ priv->tach_channel[tach_ch].tach_edge = F2F_EDGES;
+ regmap_write_bits(priv->regmap, TACH_ASPEED_CTRL(tach_ch),
+ TACH_ASPEED_IO_EDGE_MASK,
+ priv->tach_channel[tach_ch].tach_edge
+ << TACH_ASPEED_IO_EDGE_BIT);
+
+ priv->tach_channel[tach_ch].divisor = DEFAULT_TACH_DIV;
+ regmap_write_bits(priv->regmap, TACH_ASPEED_CTRL(tach_ch),
+ TACH_ASPEED_CLK_DIV_T_MASK,
+ DIV_TO_REG(priv->tach_channel[tach_ch].divisor)
+ << TACH_ASPEED_CLK_DIV_BIT);
+
+ priv->tach_channel[tach_ch].threshold = 0;
+ regmap_write_bits(priv->regmap, TACH_ASPEED_CTRL(tach_ch),
+ TACH_ASPEED_THRESHOLD_MASK,
+ priv->tach_channel[tach_ch].threshold);
+
+ priv->tach_channel[tach_ch].pulse_pr = DEFAULT_FAN_PULSE_PR;
+
+ aspeed_tach_ch_enable(priv, tach_ch, true);
+}
+
+static int aspeed_tach_create_fan(struct device *dev, struct device_node *child,
+ struct aspeed_tach_data *priv)
+{
+ u32 tach_channel;
+ int ret;
+
+ ret = of_property_read_u32(child, "reg", &tach_channel);
+ if (ret)
+ return ret;
+
+ aspeed_create_fan_tach_channel(priv, tach_channel);
+
+ return 0;
+}
+
+static void aspeed_tach_reset_assert(void *data)
+{
+ struct reset_control *rst = data;
+
+ reset_control_assert(rst);
+}
+
+static int aspeed_tach_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np, *child;
+ struct aspeed_tach_data *priv;
+ struct device *hwmon;
+ struct platform_device *parent_dev;
+ int ret;
+
+ np = dev->parent->of_node;
+ if (!of_device_is_compatible(np, "aspeed,ast2600-pwm-tach"))
+ return dev_err_probe(dev, -ENODEV,
+ "Unsupported tach device binding\n");
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+ priv->dev = &pdev->dev;
+ priv->tach_channel =
+ devm_kcalloc(dev, TACH_ASPEED_NR_TACHS,
+ sizeof(*priv->tach_channel), GFP_KERNEL);
+ if (!priv->tach_channel)
+ return -ENOMEM;
+
+ priv->regmap = syscon_node_to_regmap(np);
+ if (IS_ERR(priv->regmap))
+ return dev_err_probe(dev, PTR_ERR(priv->regmap),
+ "Couldn't get regmap\n");
+ parent_dev = of_find_device_by_node(np);
+ priv->clk = devm_clk_get_enabled(&parent_dev->dev, NULL);
+ if (IS_ERR(priv->clk))
+ return dev_err_probe(dev, PTR_ERR(priv->clk),
+ "Couldn't get clock\n");
+
+ priv->reset = devm_reset_control_get_shared(&parent_dev->dev, NULL);
+ if (IS_ERR(priv->reset))
+ return dev_err_probe(dev, PTR_ERR(priv->reset),
+ "Couldn't get reset control\n");
+
+ ret = reset_control_deassert(priv->reset);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "Couldn't deassert reset control\n");
+
+ ret = devm_add_action_or_reset(dev, aspeed_tach_reset_assert,
+ priv->reset);
+ if (ret)
+ return ret;
+
+ for_each_child_of_node(dev->of_node, child) {
+ ret = aspeed_tach_create_fan(dev, child, priv);
+ if (ret) {
+ of_node_put(child);
+ return ret;
+ }
+ }
+
+ hwmon = devm_hwmon_device_register_with_info(dev, "aspeed_tach", priv,
+ &aspeed_tach_chip_info, NULL);
+ ret = PTR_ERR_OR_ZERO(hwmon);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "Failed to register hwmon device\n");
+ return 0;
+}
+
+static const struct of_device_id of_stach_match_table[] = {
+ {
+ .compatible = "aspeed,ast2600-tach",
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, of_stach_match_table);
+
+static struct platform_driver aspeed_tach_driver = {
+ .probe = aspeed_tach_probe,
+ .driver = {
+ .name = "aspeed_tach",
+ .of_match_table = of_stach_match_table,
+ },
+};
+
+module_platform_driver(aspeed_tach_driver);
+
+MODULE_AUTHOR("Billy Tsai <[email protected]>");
+MODULE_DESCRIPTION("Aspeed ast2600 TACH device driver");
+MODULE_LICENSE("GPL");
--
2.25.1
On Wed, Nov 23, 2022 at 02:16:34PM +0800, Billy Tsai wrote:
> Add the support of PWM controller which can be found at aspeed ast2600
> soc. The pwm supoorts up to 16 channels and it's part function of
> multi-function device "pwm-tach controller".
>
> Signed-off-by: Billy Tsai <[email protected]>
> Reviewed-by: Uwe Kleine-König <[email protected]>
> Reported-by: kernel test robot <[email protected]>
Why do you add Reported-by from kernel test robot? I guess the bot
reported issues on previous version of this patch series, then you fix
them, right?
--
An old man doll... just what I always wanted! - Clara
On Wed, Nov 23, 2022 at 02:16:35PM +0800, Billy Tsai wrote:
> diff --git a/Documentation/hwmon/tach-aspeed-ast2600.rst b/Documentation/hwmon/tach-aspeed-ast2600.rst
> new file mode 100644
> index 000000000000..4f9501b783a1
> --- /dev/null
> +++ b/Documentation/hwmon/tach-aspeed-ast2600.rst
> @@ -0,0 +1,24 @@
> +Kernel driver tach-aspeed-ast2600
> +==============================
> +
> +Supported chips:
> + ASPEED AST2600
> +
> +Authors:
> + <[email protected]>
> +
> +Description:
> +------------
> +This driver implements support for ASPEED AST2600 Fan Tacho controller.
> +The controller supports up to 16 tachometer inputs.
> +
> +The driver provides the following sensor accesses in sysfs:
> +=============== ======= =====================================================
> +fanX_input ro provide current fan rotation value in RPM as reported
> + by the fan to the device.
> +fanX_div rw Fan divisor: Supported value are power of 4 (1, 4, 16
> + 64, ... 4194304)
> + The larger divisor, the less rpm accuracy and the less
> + affected by fan signal glitch.
> +fanX_pulses rw Fan pulses per resolution.
> +=============== ======= ======================================================
I found htmldocs warnings:
Documentation/hwmon/tach-aspeed-ast2600.rst:2: WARNING: Title underline too short.
Kernel driver tach-aspeed-ast2600
==============================
Documentation/hwmon/tach-aspeed-ast2600.rst:18: WARNING: Unexpected indentation.
Documentation/hwmon/tach-aspeed-ast2600.rst:19: WARNING: Block quote ends without a blank line; unexpected unindent.
Documentation/hwmon/tach-aspeed-ast2600.rst:23: WARNING: Definition list ends without a blank line; unexpected unindent.
I have applied the fixup:
---- >8 ----
diff --git a/Documentation/hwmon/tach-aspeed-ast2600.rst b/Documentation/hwmon/tach-aspeed-ast2600.rst
index 4f9501b783a11b..8faa00f6ad47c2 100644
--- a/Documentation/hwmon/tach-aspeed-ast2600.rst
+++ b/Documentation/hwmon/tach-aspeed-ast2600.rst
@@ -1,5 +1,5 @@
Kernel driver tach-aspeed-ast2600
-==============================
+=================================
Supported chips:
ASPEED AST2600
@@ -13,7 +13,8 @@ This driver implements support for ASPEED AST2600 Fan Tacho controller.
The controller supports up to 16 tachometer inputs.
The driver provides the following sensor accesses in sysfs:
-=============== ======= =====================================================
+
+=============== ======= ======================================================
fanX_input ro provide current fan rotation value in RPM as reported
by the fan to the device.
fanX_div rw Fan divisor: Supported value are power of 4 (1, 4, 16
Thanks.
--
An old man doll... just what I always wanted! - Clara
On 11/22/22 22:16, Billy Tsai wrote:
> Add the support of Tachometer which can use to monitor the frequency of
> the input. The tach supports up to 16 channels and it's part function of
> multi-function device "pwm-tach controller".
>
> Signed-off-by: Billy Tsai <[email protected]>
> Reported-by: kernel test robot <[email protected]>
The above Reported-by: tag does not make sense for new drivers. Please drop.
Also, PATCH in subject is missing.
> ---
> Documentation/hwmon/index.rst | 1 +
> Documentation/hwmon/tach-aspeed-ast2600.rst | 24 ++
> drivers/hwmon/Kconfig | 9 +
> drivers/hwmon/Makefile | 1 +
> drivers/hwmon/tach-aspeed-ast2600.c | 399 ++++++++++++++++++++
> 5 files changed, 434 insertions(+)
> create mode 100644 Documentation/hwmon/tach-aspeed-ast2600.rst
> create mode 100644 drivers/hwmon/tach-aspeed-ast2600.c
>
> diff --git a/Documentation/hwmon/index.rst b/Documentation/hwmon/index.rst
> index c1d11cf13eef..8aed4c42ca89 100644
> --- a/Documentation/hwmon/index.rst
> +++ b/Documentation/hwmon/index.rst
> @@ -193,6 +193,7 @@ Hardware Monitoring Kernel Drivers
> sparx5-temp
> stpddc60
> sy7636a-hwmon
> + tach-aspeed-ast2600
> tc654
> tc74
> thmc50
> diff --git a/Documentation/hwmon/tach-aspeed-ast2600.rst b/Documentation/hwmon/tach-aspeed-ast2600.rst
> new file mode 100644
> index 000000000000..4f9501b783a1
> --- /dev/null
> +++ b/Documentation/hwmon/tach-aspeed-ast2600.rst
> @@ -0,0 +1,24 @@
> +Kernel driver tach-aspeed-ast2600
> +==============================
> +
> +Supported chips:
> + ASPEED AST2600
> +
> +Authors:
> + <[email protected]>
> +
> +Description:
> +------------
> +This driver implements support for ASPEED AST2600 Fan Tacho controller.
> +The controller supports up to 16 tachometer inputs.
> +
> +The driver provides the following sensor accesses in sysfs:
> +=============== ======= =====================================================
> +fanX_input ro provide current fan rotation value in RPM as reported
> + by the fan to the device.
> +fanX_div rw Fan divisor: Supported value are power of 4 (1, 4, 16
> + 64, ... 4194304)
The code doesn't support 1.
> + The larger divisor, the less rpm accuracy and the less
> + affected by fan signal glitch.
> +fanX_pulses rw Fan pulses per resolution.
> +=============== ======= ======================================================
> diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
> index 7ac3daaf59ce..3196087a7b3e 100644
> --- a/drivers/hwmon/Kconfig
> +++ b/drivers/hwmon/Kconfig
> @@ -403,6 +403,15 @@ config SENSORS_ASPEED
> This driver can also be built as a module. If so, the module
> will be called aspeed_pwm_tacho.
>
> +config SENSORS_TACH_ASPEED_AST2600
> + tristate "ASPEED ast2600 Tachometer support"
> + select REGMAP
> + help
> + This driver provides support for Aspeed ast2600 Tachometer.
> +
> + To compile this driver as a module, choose M here: the module
> + will be called tach-aspeed-ast2600.
> +
> config SENSORS_ATXP1
> tristate "Attansic ATXP1 VID controller"
> depends on I2C
> diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
> index 11d076cad8a2..50a139c7c4ca 100644
> --- a/drivers/hwmon/Makefile
> +++ b/drivers/hwmon/Makefile
> @@ -53,6 +53,7 @@ obj-$(CONFIG_SENSORS_ARM_SCMI) += scmi-hwmon.o
> obj-$(CONFIG_SENSORS_ARM_SCPI) += scpi-hwmon.o
> obj-$(CONFIG_SENSORS_AS370) += as370-hwmon.o
> obj-$(CONFIG_SENSORS_ASC7621) += asc7621.o
> +obj-$(CONFIG_SENSORS_TACH_ASPEED_AST2600) += tach-aspeed-ast2600.o
> obj-$(CONFIG_SENSORS_ASPEED) += aspeed-pwm-tacho.o
> obj-$(CONFIG_SENSORS_ATXP1) += atxp1.o
> obj-$(CONFIG_SENSORS_AXI_FAN_CONTROL) += axi-fan-control.o
> diff --git a/drivers/hwmon/tach-aspeed-ast2600.c b/drivers/hwmon/tach-aspeed-ast2600.c
> new file mode 100644
> index 000000000000..2b8dd5eeb6ec
> --- /dev/null
> +++ b/drivers/hwmon/tach-aspeed-ast2600.c
> @@ -0,0 +1,399 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * Copyright (C) ASPEED Technology Inc.
> + */
> +
> +#include <linux/bitfield.h>
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/errno.h>
> +#include <linux/hwmon.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/reset.h>
> +#include <linux/sysfs.h>
> +
> +/* The channel number of Aspeed tach controller */
> +#define TACH_ASPEED_NR_TACHS 16
> +/* TACH Control Register */
> +#define TACH_ASPEED_CTRL(ch) (((ch) * 0x10) + 0x08)
> +#define TACH_ASPEED_IER BIT(31)
> +#define TACH_ASPEED_INVERS_LIMIT BIT(30)
> +#define TACH_ASPEED_LOOPBACK BIT(29)
> +#define TACH_ASPEED_ENABLE BIT(28)
> +#define TACH_ASPEED_DEBOUNCE_MASK GENMASK(27, 26)
> +#define TACH_ASPEED_DEBOUNCE_BIT 26
> +#define TACH_ASPEED_IO_EDGE_MASK GENMASK(25, 24)
> +#define TACH_ASPEED_IO_EDGE_BIT 24
> +#define TACH_ASPEED_CLK_DIV_T_MASK GENMASK(23, 20)
> +#define TACH_ASPEED_CLK_DIV_BIT 20
> +#define TACH_ASPEED_THRESHOLD_MASK GENMASK(19, 0)
> +/* [27:26] */
> +#define DEBOUNCE_3_CLK 0x00
> +#define DEBOUNCE_2_CLK 0x01
> +#define DEBOUNCE_1_CLK 0x02
> +#define DEBOUNCE_0_CLK 0x03
> +/* [25:24] */
> +#define F2F_EDGES 0x00
> +#define R2R_EDGES 0x01
> +#define BOTH_EDGES 0x02
> +/* [23:20] */
> +/* divisor = 4 to the nth power, n = register value */
> +#define DEFAULT_TACH_DIV 1024
> +#define DIV_TO_REG(divisor) (ilog2(divisor) >> 1)
> +
> +/* TACH Status Register */
> +#define TACH_ASPEED_STS(ch) (((ch) * 0x10) + 0x0C)
> +
> +/*PWM_TACH_STS */
> +#define TACH_ASPEED_ISR BIT(31)
> +#define TACH_ASPEED_PWM_OUT BIT(25)
> +#define TACH_ASPEED_PWM_OEN BIT(24)
> +#define TACH_ASPEED_DEB_INPUT BIT(23)
> +#define TACH_ASPEED_RAW_INPUT BIT(22)
> +#define TACH_ASPEED_VALUE_UPDATE BIT(21)
> +#define TACH_ASPEED_FULL_MEASUREMENT BIT(20)
> +#define TACH_ASPEED_VALUE_MASK GENMASK(19, 0)
> +/**********************************************************
> + * Software setting
> + *********************************************************/
> +#define DEFAULT_FAN_PULSE_PR 2
> +struct aspeed_tach_channel_params {
> + int limited_inverse;
> + u16 threshold;
> + u8 tach_edge;
> + u8 tach_debounce;
> + u8 pulse_pr;
> + u32 divisor;
> + u32 sample_period; /* unit is us */
> + u32 polling_period; /* unit is us */
> +};
> +
> +struct aspeed_tach_data {
> + struct device *dev;
> + struct regmap *regmap;
> + struct clk *clk;
> + struct reset_control *reset;
> + bool tach_present[TACH_ASPEED_NR_TACHS];
> + struct aspeed_tach_channel_params *tach_channel;
> +};
> +
> +static void aspeed_tach_ch_enable(struct aspeed_tach_data *priv, u8 tach_ch,
> + bool enable)
> +{
> + if (enable)
> + regmap_set_bits(priv->regmap, TACH_ASPEED_CTRL(tach_ch),
> + TACH_ASPEED_ENABLE);
> + else
> + regmap_clear_bits(priv->regmap, TACH_ASPEED_CTRL(tach_ch),
> + TACH_ASPEED_ENABLE);
> +}
> +
> +static u64 aspeed_tach_val_to_rpm(struct aspeed_tach_data *priv, u8 fan_tach_ch,
> + u32 tach_val)
> +{
> + unsigned long clk_source;
> + u64 rpm;
> + u32 tach_div;
> +
> + /*
> + * We need the mode to determine if the tach_val is double (from
> + * counting both edges).
> + */
> + if (priv->tach_channel[fan_tach_ch].tach_edge == BOTH_EDGES)
> + tach_val <<= 1;
> +
> + tach_div = tach_val * (priv->tach_channel[fan_tach_ch].divisor) *
> + (priv->tach_channel[fan_tach_ch].pulse_pr);
> +
> + clk_source = clk_get_rate(priv->clk);
Unless the clock rate can change (which is unlikely, I would suggest
to read it once during probe and re-use the value instead of reading it
repeatedly.
> + dev_dbg(priv->dev, "clk %ld, tach_val %d , tach_div %d\n", clk_source,
> + tach_val, tach_div);
> +
> + rpm = (u64)clk_source * 60;
> + do_div(rpm, tach_div);
> +
> + return rpm;
> +}
> +
> +static int aspeed_get_fan_tach_ch_rpm(struct aspeed_tach_data *priv,
> + u8 fan_tach_ch)
> +{
> + u32 val;
> + u64 rpm;
> + int ret;
> +
> + ret = regmap_read(priv->regmap, TACH_ASPEED_STS(fan_tach_ch), &val);
> +
Please drop this empty line.
The existence of a status register makes me wonder what is in there.
Does the controller report any errors ? If so, it might be worthwile
adding attribute(s) for it.
> + if (ret)
> + return ret;
> +
> + if (!(val & TACH_ASPEED_FULL_MEASUREMENT))
> + return 0;
> + rpm = aspeed_tach_val_to_rpm(priv, fan_tach_ch,
> + val & TACH_ASPEED_VALUE_MASK);
> +
> + return rpm;
> +}
> +
> +static int aspeed_tach_hwmon_read(struct device *dev,
> + enum hwmon_sensor_types type, u32 attr,
> + int channel, long *val)
> +{
> + struct aspeed_tach_data *priv = dev_get_drvdata(dev);
> + u32 reg_val;
> + int ret;
> +
> + switch (attr) {
> + case hwmon_fan_input:
> + ret = aspeed_get_fan_tach_ch_rpm(priv, channel);
> + if (ret < 0)
> + return ret;
> + *val = ret;
> + break;
> + case hwmon_fan_div:
> + regmap_read(priv->regmap, TACH_ASPEED_CTRL(channel), ®_val);
> + reg_val = FIELD_GET(TACH_ASPEED_CLK_DIV_T_MASK, reg_val);
> + *val = BIT(reg_val << 1);
> + break;
> + case hwmon_fan_pulses:
> + *val = priv->tach_channel[channel].pulse_pr;
> + break;
> + default:
> + return -EOPNOTSUPP;
> + }
> + return 0;
> +}
> +
> +static int aspeed_tach_hwmon_write(struct device *dev,
> + enum hwmon_sensor_types type, u32 attr,
> + int channel, long val)
> +{
> + struct aspeed_tach_data *priv = dev_get_drvdata(dev);
> +
> + switch (attr) {
> + case hwmon_fan_div:
> + if (!(is_power_of_2(val) && !(ilog2(val) % 2))) {
> + dev_err(dev,
> + "fan_div value %ld not supported. Only support power of 4\n",
> + val);
Please refrain from error messages here. This only clogs the log as
result of user input.
The arithmetic is confusing.
if (!is_power_of_2(val) || (ilog2(val) % 2)))
would be much less confusing and easier to understand.
> + return -EINVAL;
> + }
There should be a range check. The above accepts a divisor value larger than 1024.
> + priv->tach_channel[channel].divisor = val;
> + regmap_write_bits(priv->regmap, TACH_ASPEED_CTRL(channel),
> + TACH_ASPEED_CLK_DIV_T_MASK,
> + DIV_TO_REG(priv->tach_channel[channel].divisor)
> + << TACH_ASPEED_CLK_DIV_BIT);
> + break;
> + case hwmon_fan_pulses:
> + priv->tach_channel[channel].pulse_pr = val;
> + break;
> + default:
> + return -EOPNOTSUPP;
> + }
> +
> + return 0;
> +}
> +
> +static umode_t aspeed_tach_dev_is_visible(const void *drvdata,
> + enum hwmon_sensor_types type,
> + u32 attr, int channel)
> +{
> + const struct aspeed_tach_data *priv = drvdata;
> +
> + if (!priv->tach_present[channel])
> + return 0;
> + switch (attr) {
> + case hwmon_fan_input:
> + return 0444;
> + case hwmon_fan_div:
> + case hwmon_fan_pulses:
> + return 0644;
> + }
> + return 0;
> +}
> +
> +static const struct hwmon_ops aspeed_tach_ops = {
> + .is_visible = aspeed_tach_dev_is_visible,
> + .read = aspeed_tach_hwmon_read,
> + .write = aspeed_tach_hwmon_write,
> +};
> +
> +static const struct hwmon_channel_info *aspeed_tach_info[] = {
> + HWMON_CHANNEL_INFO(fan, HWMON_F_INPUT | HWMON_F_DIV | HWMON_F_PULSES,
> + HWMON_F_INPUT | HWMON_F_DIV | HWMON_F_PULSES,
> + HWMON_F_INPUT | HWMON_F_DIV | HWMON_F_PULSES,
> + HWMON_F_INPUT | HWMON_F_DIV | HWMON_F_PULSES,
> + HWMON_F_INPUT | HWMON_F_DIV | HWMON_F_PULSES,
> + HWMON_F_INPUT | HWMON_F_DIV | HWMON_F_PULSES,
> + HWMON_F_INPUT | HWMON_F_DIV | HWMON_F_PULSES,
> + HWMON_F_INPUT | HWMON_F_DIV | HWMON_F_PULSES,
> + HWMON_F_INPUT | HWMON_F_DIV | HWMON_F_PULSES,
> + HWMON_F_INPUT | HWMON_F_DIV | HWMON_F_PULSES,
> + HWMON_F_INPUT | HWMON_F_DIV | HWMON_F_PULSES,
> + HWMON_F_INPUT | HWMON_F_DIV | HWMON_F_PULSES,
> + HWMON_F_INPUT | HWMON_F_DIV | HWMON_F_PULSES,
> + HWMON_F_INPUT | HWMON_F_DIV | HWMON_F_PULSES,
> + HWMON_F_INPUT | HWMON_F_DIV | HWMON_F_PULSES,
> + HWMON_F_INPUT | HWMON_F_DIV | HWMON_F_PULSES),
> + NULL
> +};
> +
> +static const struct hwmon_chip_info aspeed_tach_chip_info = {
> + .ops = &aspeed_tach_ops,
> + .info = aspeed_tach_info,
> +};
> +
> +static void aspeed_create_fan_tach_channel(struct aspeed_tach_data *priv,
> + u32 tach_ch)
> +{
> + priv->tach_present[tach_ch] = true;
> + priv->tach_channel[tach_ch].limited_inverse = 0;
> + regmap_write_bits(priv->regmap, TACH_ASPEED_CTRL(tach_ch),
> + TACH_ASPEED_INVERS_LIMIT,
> + priv->tach_channel[tach_ch].limited_inverse ?
> + TACH_ASPEED_INVERS_LIMIT :
> + 0);
> +
What is the purpose of the above code ? limited_inverse is always 0.
> + priv->tach_channel[tach_ch].tach_debounce = DEBOUNCE_3_CLK;
> + regmap_write_bits(priv->regmap, TACH_ASPEED_CTRL(tach_ch),
> + TACH_ASPEED_DEBOUNCE_MASK,
> + priv->tach_channel[tach_ch].tach_debounce
> + << TACH_ASPEED_DEBOUNCE_BIT);
> +
> + priv->tach_channel[tach_ch].tach_edge = F2F_EDGES;
> + regmap_write_bits(priv->regmap, TACH_ASPEED_CTRL(tach_ch),
> + TACH_ASPEED_IO_EDGE_MASK,
> + priv->tach_channel[tach_ch].tach_edge
> + << TACH_ASPEED_IO_EDGE_BIT);
> +
limited_inverse, tach_debounce, and tach_edge are constants.
There is no need to keep constants as per-channel variables.
> + priv->tach_channel[tach_ch].divisor = DEFAULT_TACH_DIV;
> + regmap_write_bits(priv->regmap, TACH_ASPEED_CTRL(tach_ch),
> + TACH_ASPEED_CLK_DIV_T_MASK,
> + DIV_TO_REG(priv->tach_channel[tach_ch].divisor)
> + << TACH_ASPEED_CLK_DIV_BIT);
> +
> + priv->tach_channel[tach_ch].threshold = 0;
> + regmap_write_bits(priv->regmap, TACH_ASPEED_CTRL(tach_ch),
> + TACH_ASPEED_THRESHOLD_MASK,
> + priv->tach_channel[tach_ch].threshold);
> +
The above applies to threshold as well.
> + priv->tach_channel[tach_ch].pulse_pr = DEFAULT_FAN_PULSE_PR;
> +
> + aspeed_tach_ch_enable(priv, tach_ch, true);
> +}
> +
I kind of can understand that there are no devicetree properties given the
discussion around it. It is still unfortunate since being involved in that
discussion might help ensure that a generic property such as fan divisor value
ends up being supported in the upcoming generic properties.
> +static int aspeed_tach_create_fan(struct device *dev, struct device_node *child,
> + struct aspeed_tach_data *priv)
> +{
> + u32 tach_channel;
> + int ret;
> +
> + ret = of_property_read_u32(child, "reg", &tach_channel);
> + if (ret)
> + return ret;
> +
> + aspeed_create_fan_tach_channel(priv, tach_channel);
> +
> + return 0;
> +}
> +
> +static void aspeed_tach_reset_assert(void *data)
> +{
> + struct reset_control *rst = data;
> +
> + reset_control_assert(rst);
> +}
> +
> +static int aspeed_tach_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *np, *child;
> + struct aspeed_tach_data *priv;
> + struct device *hwmon;
> + struct platform_device *parent_dev;
> + int ret;
> +
> + np = dev->parent->of_node;
> + if (!of_device_is_compatible(np, "aspeed,ast2600-pwm-tach"))
> + return dev_err_probe(dev, -ENODEV,
> + "Unsupported tach device binding\n");
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> + priv->dev = &pdev->dev;
> + priv->tach_channel =
> + devm_kcalloc(dev, TACH_ASPEED_NR_TACHS,
> + sizeof(*priv->tach_channel), GFP_KERNEL);
> + if (!priv->tach_channel)
> + return -ENOMEM;
Why not allocate tach_channel as array within aspeed_tach_data ?
> +
> + priv->regmap = syscon_node_to_regmap(np);
> + if (IS_ERR(priv->regmap))
> + return dev_err_probe(dev, PTR_ERR(priv->regmap),
> + "Couldn't get regmap\n");
> + parent_dev = of_find_device_by_node(np);
Isn't that the same as dev->parent ?
> + priv->clk = devm_clk_get_enabled(&parent_dev->dev, NULL);
> + if (IS_ERR(priv->clk))
> + return dev_err_probe(dev, PTR_ERR(priv->clk),
> + "Couldn't get clock\n");
> +
> + priv->reset = devm_reset_control_get_shared(&parent_dev->dev, NULL);
> + if (IS_ERR(priv->reset))
> + return dev_err_probe(dev, PTR_ERR(priv->reset),
> + "Couldn't get reset control\n");
> +
> + ret = reset_control_deassert(priv->reset);
> + if (ret)
> + return dev_err_probe(dev, ret,
> + "Couldn't deassert reset control\n");
> +
> + ret = devm_add_action_or_reset(dev, aspeed_tach_reset_assert,
> + priv->reset);
> + if (ret)
> + return ret;
> +
> + for_each_child_of_node(dev->of_node, child) {
> + ret = aspeed_tach_create_fan(dev, child, priv);
> + if (ret) {
> + of_node_put(child);
> + return ret;
> + }
> + }
> +
> + hwmon = devm_hwmon_device_register_with_info(dev, "aspeed_tach", priv,
> + &aspeed_tach_chip_info, NULL);
> + ret = PTR_ERR_OR_ZERO(hwmon);
> + if (ret)
> + return dev_err_probe(dev, ret,
> + "Failed to register hwmon device\n");
> + return 0;
Why not return the error ? Either it is an error or it isn't. If it is
not an error, dev_err_probe() is not appropriate. If it is, the error
should be returned. Either case, if this is on purpose, it needs an
explanation.
> +}
> +
> +static const struct of_device_id of_stach_match_table[] = {
> + {
> + .compatible = "aspeed,ast2600-tach",
> + },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, of_stach_match_table);
> +
> +static struct platform_driver aspeed_tach_driver = {
> + .probe = aspeed_tach_probe,
> + .driver = {
> + .name = "aspeed_tach",
> + .of_match_table = of_stach_match_table,
> + },
> +};
> +
> +module_platform_driver(aspeed_tach_driver);
> +
> +MODULE_AUTHOR("Billy Tsai <[email protected]>");
> +MODULE_DESCRIPTION("Aspeed ast2600 TACH device driver");
> +MODULE_LICENSE("GPL");
On 2022/11/23, 11:45 PM, "Guenter Roeck" <[email protected] on behalf of [email protected]> wrote:
On 11/22/22 22:16, Billy Tsai wrote:
> > +The driver provides the following sensor accesses in sysfs:
> > +=============== ======= =====================================================
> > +fanX_input ro provide current fan rotation value in RPM as reported
> > + by the fan to the device.
> > +fanX_div rw Fan divisor: Supported value are power of 4 (1, 4, 16
> > + 64, ... 4194304)
> The code doesn't support 1.
The code can support 1.
> The existence of a status register makes me wonder what is in there.
> Does the controller report any errors ? If so, it might be worthwile
> adding attribute(s) for it.
> > + if (ret)
> > + return ret;
> > +
> > + if (!(val & TACH_ASPEED_FULL_MEASUREMENT))
> > + return 0;
> > + rpm = aspeed_tach_val_to_rpm(priv, fan_tach_ch,
> > + val & TACH_ASPEED_VALUE_MASK);
> > +
> > + return rpm;
The status register is the TACH_ASPEED_FULL_MEASUREMENT which is used to indicate that
the controller doesn't detect the change in tach pin for a long time.
> > +static void aspeed_create_fan_tach_channel(struct aspeed_tach_data *priv,
> > + u32 tach_ch)
> > +{
> > + priv->tach_present[tach_ch] = true;
> > + priv->tach_channel[tach_ch].limited_inverse = 0;
> > + regmap_write_bits(priv->regmap, TACH_ASPEED_CTRL(tach_ch),
> > + TACH_ASPEED_INVERS_LIMIT,
> > + priv->tach_channel[tach_ch].limited_inverse ?
> > + TACH_ASPEED_INVERS_LIMIT :
> > + 0);
> > +
> What is the purpose of the above code ? limited_inverse is always 0.
> > + priv->tach_channel[tach_ch].tach_debounce = DEBOUNCE_3_CLK;
> > + regmap_write_bits(priv->regmap, TACH_ASPEED_CTRL(tach_ch),
> > + TACH_ASPEED_DEBOUNCE_MASK,
> > + priv->tach_channel[tach_ch].tach_debounce
> > + << TACH_ASPEED_DEBOUNCE_BIT);
> > +
> > + priv->tach_channel[tach_ch].tach_edge = F2F_EDGES;
> > + regmap_write_bits(priv->regmap, TACH_ASPEED_CTRL(tach_ch),
> > + TACH_ASPEED_IO_EDGE_MASK,
> > + priv->tach_channel[tach_ch].tach_edge
> > + << TACH_ASPEED_IO_EDGE_BIT);
> > +
> limited_inverse, tach_debounce, and tach_edge are constants.
> There is no need to keep constants as per-channel variables.
> > + priv->tach_channel[tach_ch].divisor = DEFAULT_TACH_DIV;
> > + regmap_write_bits(priv->regmap, TACH_ASPEED_CTRL(tach_ch),
> > + TACH_ASPEED_CLK_DIV_T_MASK,
> > + DIV_TO_REG(priv->tach_channel[tach_ch].divisor)
> > + << TACH_ASPEED_CLK_DIV_BIT);
> > +
> > + priv->tach_channel[tach_ch].threshold = 0;
> > + regmap_write_bits(priv->regmap, TACH_ASPEED_CTRL(tach_ch),
> > + TACH_ASPEED_THRESHOLD_MASK,
> > + priv->tach_channel[tach_ch].threshold);
> > +
> The above applies to threshold as well.
The above code is used to retain the adjustable feature of the controller.
I will remove them until I add the dts property to support them.
> > + }
> > +
> > + hwmon = devm_hwmon_device_register_with_info(dev, "aspeed_tach", priv,
> > + &aspeed_tach_chip_info, NULL);
> > + ret = PTR_ERR_OR_ZERO(hwmon);
> > + if (ret)
> > + return dev_err_probe(dev, ret,
> > + "Failed to register hwmon device\n");
> > + return 0;
> Why not return the error ? Either it is an error or it isn't. If it is
> not an error, dev_err_probe() is not appropriate. If it is, the error
> should be returned. Either case, if this is on purpose, it needs an
> explanation.
I have return the return value of the dev_err_probe. Did I miss someting?
Thanks
Best Regards,
Billy Tsai
On 11/28/22 23:08, Billy Tsai wrote:
> On 2022/11/23, 11:45 PM, "Guenter Roeck" <[email protected] on behalf of [email protected]> wrote:
>
> On 11/22/22 22:16, Billy Tsai wrote:
> > > +The driver provides the following sensor accesses in sysfs:
> > > +=============== ======= =====================================================
> > > +fanX_input ro provide current fan rotation value in RPM as reported
> > > + by the fan to the device.
> > > +fanX_div rw Fan divisor: Supported value are power of 4 (1, 4, 16
> > > + 64, ... 4194304)
>
> > The code doesn't support 1.
>
> The code can support 1.
>
Sorry, leftover from when I misread the code and thought it didn't.
>
> > The existence of a status register makes me wonder what is in there.
> > Does the controller report any errors ? If so, it might be worthwile
> > adding attribute(s) for it.
>
> > > + if (ret)
> > > + return ret;
> > > +
> > > + if (!(val & TACH_ASPEED_FULL_MEASUREMENT))
> > > + return 0;
> > > + rpm = aspeed_tach_val_to_rpm(priv, fan_tach_ch,
> > > + val & TACH_ASPEED_VALUE_MASK);
> > > +
> > > + return rpm;
>
> The status register is the TACH_ASPEED_FULL_MEASUREMENT which is used to indicate that
> the controller doesn't detect the change in tach pin for a long time.
>
> > > +static void aspeed_create_fan_tach_channel(struct aspeed_tach_data *priv,
> > > + u32 tach_ch)
> > > +{
> > > + priv->tach_present[tach_ch] = true;
> > > + priv->tach_channel[tach_ch].limited_inverse = 0;
> > > + regmap_write_bits(priv->regmap, TACH_ASPEED_CTRL(tach_ch),
> > > + TACH_ASPEED_INVERS_LIMIT,
> > > + priv->tach_channel[tach_ch].limited_inverse ?
> > > + TACH_ASPEED_INVERS_LIMIT :
> > > + 0);
> > > +
> > What is the purpose of the above code ? limited_inverse is always 0.
>
> > > + priv->tach_channel[tach_ch].tach_debounce = DEBOUNCE_3_CLK;
> > > + regmap_write_bits(priv->regmap, TACH_ASPEED_CTRL(tach_ch),
> > > + TACH_ASPEED_DEBOUNCE_MASK,
> > > + priv->tach_channel[tach_ch].tach_debounce
> > > + << TACH_ASPEED_DEBOUNCE_BIT);
> > > +
> > > + priv->tach_channel[tach_ch].tach_edge = F2F_EDGES;
> > > + regmap_write_bits(priv->regmap, TACH_ASPEED_CTRL(tach_ch),
> > > + TACH_ASPEED_IO_EDGE_MASK,
> > > + priv->tach_channel[tach_ch].tach_edge
> > > + << TACH_ASPEED_IO_EDGE_BIT);
> > > +
>
> > limited_inverse, tach_debounce, and tach_edge are constants.
> > There is no need to keep constants as per-channel variables.
>
> > > + priv->tach_channel[tach_ch].divisor = DEFAULT_TACH_DIV;
> > > + regmap_write_bits(priv->regmap, TACH_ASPEED_CTRL(tach_ch),
> > > + TACH_ASPEED_CLK_DIV_T_MASK,
> > > + DIV_TO_REG(priv->tach_channel[tach_ch].divisor)
> > > + << TACH_ASPEED_CLK_DIV_BIT);
> > > +
> > > + priv->tach_channel[tach_ch].threshold = 0;
> > > + regmap_write_bits(priv->regmap, TACH_ASPEED_CTRL(tach_ch),
> > > + TACH_ASPEED_THRESHOLD_MASK,
> > > + priv->tach_channel[tach_ch].threshold);
> > > +
>
> > The above applies to threshold as well.
>
> The above code is used to retain the adjustable feature of the controller.
> I will remove them until I add the dts property to support them.
>
> > > + }
> > > +
> > > + hwmon = devm_hwmon_device_register_with_info(dev, "aspeed_tach", priv,
> > > + &aspeed_tach_chip_info, NULL);
> > > + ret = PTR_ERR_OR_ZERO(hwmon);
> > > + if (ret)
> > > + return dev_err_probe(dev, ret,
> > > + "Failed to register hwmon device\n");
> > > + return 0;
>
> > Why not return the error ? Either it is an error or it isn't. If it is
> > not an error, dev_err_probe() is not appropriate. If it is, the error
> > should be returned. Either case, if this is on purpose, it needs an
> > explanation.
>
> I have return the return value of the dev_err_probe. Did I miss someting?
>
No, me not having enough coffee when reviewing the code. Sorry for the noise.
Thanks,
Guenter
Hello Billy,
I wonder if you address the feedback you got for this series. I think
there are no big issues left, are there?
There is only one patch left open in the PWM patchwork (i.e. the patch
implementing the driver that already has my Reviewed-by tag). I'll
discard that one, too, as "changes requested" and hope you will send a
v5.
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | https://www.pengutronix.de/ |
Hi Uwe,
On 2023/1/18, 5:48 AM, "Uwe Kleine-König" <[email protected] <mailto:[email protected]>> wrote:
> Hello Billy,
> I wonder if you address the feedback you got for this series. I think
> there are no big issues left, are there?
Thanks for your help. Yes, there is no issue with the PWM driver at the
moment. The remaining task of this series is dt-binding and I am waiting
the feedback from reviewer.
> There is only one patch left open in the PWM patchwork (i.e. the patch
> implementing the driver that already has my Reviewed-by tag). I'll
> discard that one, too, as "changes requested" and hope you will send a
> v5.
I will send a v5 when the issue about the dt-binding is resloved.
Thanks again for your help!
Best Regards,
Billy Tsai
> From: Billy Tsai <[email protected]>
> Sent: Wednesday, November 23, 2022 2:17 PM
> To: [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]
> Cc: kernel test robot <[email protected]>
> Subject: [v4 4/5] pwm: Add Aspeed ast2600 PWM support
>
> Add the support of PWM controller which can be found at aspeed ast2600 soc.
> The pwm supoorts up to 16 channels and it's part function of multi-function
> device "pwm-tach controller".
>
> Signed-off-by: Billy Tsai <[email protected]>
> Reviewed-by: Uwe Kleine-König <[email protected]>
> Reported-by: kernel test robot <[email protected]>
> ---
> drivers/pwm/Kconfig | 10 +
> drivers/pwm/Makefile | 1 +
> drivers/pwm/pwm-aspeed-ast2600.c | 318
> +++++++++++++++++++++++++++++++
> 3 files changed, 329 insertions(+)
> create mode 100644 drivers/pwm/pwm-aspeed-ast2600.c
>
> diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index
> 60d13a949bc5..54915185d918 100644
> --- a/drivers/pwm/Kconfig
> +++ b/drivers/pwm/Kconfig
> @@ -51,6 +51,16 @@ config PWM_AB8500
> To compile this driver as a module, choose M here: the module
> will be called pwm-ab8500.
>
> +config PWM_ASPEED_AST2600
> + tristate "Aspeed ast2600 PWM support"
> + depends on ARCH_ASPEED || COMPILE_TEST
> + depends on HAVE_CLK && HAS_IOMEM
> + help
> + This driver provides support for Aspeed ast2600 PWM controllers.
> +
> + To compile this driver as a module, choose M here: the module
> + will be called pwm-aspeed-ast2600.
> +
> config PWM_ATMEL
> tristate "Atmel PWM support"
> depends on ARCH_AT91 || COMPILE_TEST
> diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index
> 7bf1a29f02b8..5169c34056e6 100644
> --- a/drivers/pwm/Makefile
> +++ b/drivers/pwm/Makefile
> @@ -2,6 +2,7 @@
> obj-$(CONFIG_PWM) += core.o
> obj-$(CONFIG_PWM_SYSFS) += sysfs.o
> obj-$(CONFIG_PWM_AB8500) += pwm-ab8500.o
> +obj-$(CONFIG_PWM_ASPEED_AST2600) += pwm-aspeed-ast2600.o
> obj-$(CONFIG_PWM_ATMEL) += pwm-atmel.o
> obj-$(CONFIG_PWM_ATMEL_HLCDC_PWM) += pwm-atmel-hlcdc.o
> obj-$(CONFIG_PWM_ATMEL_TCB) += pwm-atmel-tcb.o
> diff --git a/drivers/pwm/pwm-aspeed-ast2600.c
> b/drivers/pwm/pwm-aspeed-ast2600.c
> new file mode 100644
> index 000000000000..2c22aff18624
> --- /dev/null
> +++ b/drivers/pwm/pwm-aspeed-ast2600.c
> @@ -0,0 +1,318 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * Copyright (C) 2021 Aspeed Technology Inc.
> + *
> + * PWM controller driver for Aspeed ast2600 SoCs.
> + * This drivers doesn't support earlier version of the IP.
> + *
> + * The hardware operates in time quantities of length
> + * Q := (DIV_L + 1) << DIV_H / input-clk
> + * The length of a PWM period is (DUTY_CYCLE_PERIOD + 1) * Q.
> + * The maximal value for DUTY_CYCLE_PERIOD is used here to provide
> + * a fine grained selection for the duty cycle.
> + *
> + * This driver uses DUTY_CYCLE_RISING_POINT = 0, so from the start of a
> + * period the output is active until DUTY_CYCLE_FALLING_POINT * Q. Note
> + * that if DUTY_CYCLE_RISING_POINT = DUTY_CYCLE_FALLING_POINT the
> +output is
> + * always active.
> + *
> + * Register usage:
> + * PIN_ENABLE: When it is unset the pwm controller will emit inactive level to
> the external.
> + * Use to determine whether the PWM channel is enabled or disabled
> + * CLK_ENABLE: When it is unset the pwm controller will assert the duty
> +counter reset and
> + * emit inactive level to the PIN_ENABLE mux after that the driver can
> +still change the pwm period
> + * and duty and the value will apply when CLK_ENABLE be set again.
> + * Use to determine whether duty_cycle bigger than 0.
> + * PWM_ASPEED_CTRL_INVERSE: When it is toggled the output value will
> inverse immediately.
> + *
> +PWM_ASPEED_DUTY_CYCLE_FALLING_POINT/PWM_ASPEED_DUTY_CYCLE_R
> ISING_POINT:
> +When these two
> + * values are equal it means the duty cycle = 100%.
> + *
> + * The glitch may generate at:
> + * - Enabled changing when the duty_cycle bigger than 0% and less than
> 100%.
> + * - Polarity changing when the duty_cycle bigger than 0% and less than
> 100%.
> + *
> + * Limitations:
> + * - When changing both duty cycle and period, we cannot prevent in
> + * software that the output might produce a period with mixed
> + * settings.
> + * - Disabling the PWM doesn't complete the current period.
> + *
> + * Improvements:
> + * - When only changing one of duty cycle or period, our pwm controller will
> not
> + * generate the glitch, the configure will change at next cycle of pwm.
> + * This improvement can disable/enable through
> PWM_ASPEED_CTRL_DUTY_SYNC_DISABLE.
> + */
> +
> +#include <linux/bitfield.h>
> +#include <linux/clk.h>
> +#include <linux/errno.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/math64.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/of_platform.h>
> +#include <linux/platform_device.h>
> +#include <linux/pwm.h>
> +#include <linux/regmap.h>
> +#include <linux/reset.h>
> +#include <linux/sysfs.h>
> +
> +/* The channel number of Aspeed pwm controller */
> +#define PWM_ASPEED_NR_PWMS 16
> +/* PWM Control Register */
> +#define PWM_ASPEED_CTRL(ch) ((ch) * 0x10 + 0x00)
> +#define PWM_ASPEED_CTRL_LOAD_SEL_RISING_AS_WDT BIT(19)
> +#define PWM_ASPEED_CTRL_DUTY_LOAD_AS_WDT_ENABLE BIT(18)
> +#define PWM_ASPEED_CTRL_DUTY_SYNC_DISABLE BIT(17)
> +#define PWM_ASPEED_CTRL_CLK_ENABLE BIT(16)
> +#define PWM_ASPEED_CTRL_LEVEL_OUTPUT BIT(15)
> +#define PWM_ASPEED_CTRL_INVERSE BIT(14)
> +#define PWM_ASPEED_CTRL_OPEN_DRAIN_ENABLE BIT(13)
> +#define PWM_ASPEED_CTRL_PIN_ENABLE BIT(12)
> +#define PWM_ASPEED_CTRL_CLK_DIV_H GENMASK(11, 8)
> +#define PWM_ASPEED_CTRL_CLK_DIV_L GENMASK(7, 0)
> +
> +/* PWM Duty Cycle Register */
> +#define PWM_ASPEED_DUTY_CYCLE(ch) ((ch) * 0x10 + 0x04)
> +#define PWM_ASPEED_DUTY_CYCLE_PERIOD GENMASK(31, 24)
> +#define PWM_ASPEED_DUTY_CYCLE_POINT_AS_WDT GENMASK(23, 16)
> +#define PWM_ASPEED_DUTY_CYCLE_FALLING_POINT GENMASK(15, 8)
> +#define PWM_ASPEED_DUTY_CYCLE_RISING_POINT GENMASK(7, 0)
> +
> +/* PWM fixed value */
> +#define PWM_ASPEED_FIXED_PERIOD
> FIELD_MAX(PWM_ASPEED_DUTY_CYCLE_PERIOD)
> +
> +struct aspeed_pwm_data {
> + struct pwm_chip chip;
> + struct clk *clk;
> + struct regmap *regmap;
> + struct reset_control *reset;
> +};
> +
> +static inline struct aspeed_pwm_data *
> +aspeed_pwm_chip_to_data(struct pwm_chip *chip) {
> + return container_of(chip, struct aspeed_pwm_data, chip); }
> +
> +static void aspeed_pwm_get_state(struct pwm_chip *chip, struct
void should be change to int
> pwm_device *pwm,
> + struct pwm_state *state)
> +{
> + struct device *dev = chip->dev;
> + struct aspeed_pwm_data *priv = aspeed_pwm_chip_to_data(chip);
> + u32 hwpwm = pwm->hwpwm;
> + bool polarity, pin_en, clk_en;
> + u32 duty_pt, val;
> + unsigned long rate;
> + u64 div_h, div_l, duty_cycle_period, dividend;
> +
> + regmap_read(priv->regmap, PWM_ASPEED_CTRL(hwpwm), &val);
> + polarity = FIELD_GET(PWM_ASPEED_CTRL_INVERSE, val);
> + pin_en = FIELD_GET(PWM_ASPEED_CTRL_PIN_ENABLE, val);
> + clk_en = FIELD_GET(PWM_ASPEED_CTRL_CLK_ENABLE, val);
> + div_h = FIELD_GET(PWM_ASPEED_CTRL_CLK_DIV_H, val);
> + div_l = FIELD_GET(PWM_ASPEED_CTRL_CLK_DIV_L, val);
> + regmap_read(priv->regmap, PWM_ASPEED_DUTY_CYCLE(hwpwm), &val);
> + duty_pt = FIELD_GET(PWM_ASPEED_DUTY_CYCLE_FALLING_POINT, val);
> + duty_cycle_period = FIELD_GET(PWM_ASPEED_DUTY_CYCLE_PERIOD,
> val);
> +
> + rate = clk_get_rate(priv->clk);
> +
> + /*
> + * This multiplication doesn't overflow, the upper bound is
> + * 1000000000 * 256 * 256 << 15 = 0x1dcd650000000000
> + */
> + dividend = (u64)NSEC_PER_SEC * (div_l + 1) * (duty_cycle_period + 1)
> + << div_h;
> + state->period = DIV_ROUND_UP_ULL(dividend, rate);
> +
> + if (clk_en && duty_pt) {
> + dividend = (u64)NSEC_PER_SEC * (div_l + 1) * duty_pt
> + << div_h;
> + state->duty_cycle = DIV_ROUND_UP_ULL(dividend, rate);
> + } else {
> + state->duty_cycle = clk_en ? state->period : 0;
> + }
> + state->polarity = polarity ? PWM_POLARITY_INVERSED :
> PWM_POLARITY_NORMAL;
> + state->enabled = pin_en;
> + dev_dbg(dev, "get period: %lldns, duty_cycle: %lldns", state->period,
> + state->duty_cycle);
Add return 0 here.
> +}
> +
> +static int aspeed_pwm_apply(struct pwm_chip *chip, struct pwm_device
> *pwm,
> + const struct pwm_state *state)
> +{
> + struct device *dev = chip->dev;
> + struct aspeed_pwm_data *priv = aspeed_pwm_chip_to_data(chip);
> + u32 hwpwm = pwm->hwpwm, duty_pt;
> + unsigned long rate;
> + u64 div_h, div_l, divisor, expect_period;
> + bool clk_en;
> +
> + rate = clk_get_rate(priv->clk);
> + expect_period = min(div64_u64(ULLONG_MAX, (u64)rate),
> state->period);
> + dev_dbg(dev, "expect period: %lldns, duty_cycle: %lldns", expect_period,
> + state->duty_cycle);
> + /*
> + * Pick the smallest value for div_h so that div_l can be the biggest
> + * which results in a finer resolution near the target period value.
> + */
> + divisor = (u64)NSEC_PER_SEC * (PWM_ASPEED_FIXED_PERIOD + 1) *
> + (FIELD_MAX(PWM_ASPEED_CTRL_CLK_DIV_L) + 1);
> + div_h = order_base_2(DIV64_U64_ROUND_UP(rate * expect_period,
> divisor));
> + if (div_h > 0xf)
> + div_h = 0xf;
> +
> + divisor = ((u64)NSEC_PER_SEC * (PWM_ASPEED_FIXED_PERIOD + 1)) <<
> div_h;
> + div_l = div64_u64(rate * expect_period, divisor);
> +
> + if (div_l == 0)
> + return -ERANGE;
> +
> + div_l -= 1;
> +
> + if (div_l > 255)
> + div_l = 255;
> +
> + dev_dbg(dev, "clk source: %ld div_h %lld, div_l : %lld\n", rate, div_h,
> + div_l);
> + /* duty_pt = duty_cycle * (PERIOD + 1) / period */
> + duty_pt = div64_u64(state->duty_cycle * rate,
> + (u64)NSEC_PER_SEC * (div_l + 1) << div_h);
> + dev_dbg(dev, "duty_cycle = %lld, duty_pt = %d\n", state->duty_cycle,
> + duty_pt);
> +
> + /*
> + * Fixed DUTY_CYCLE_PERIOD to its max value to get a
> + * fine-grained resolution for duty_cycle at the expense of a
> + * coarser period resolution.
> + */
> + regmap_update_bits(priv->regmap,
> PWM_ASPEED_DUTY_CYCLE(hwpwm),
> + PWM_ASPEED_DUTY_CYCLE_PERIOD,
> + FIELD_PREP(PWM_ASPEED_DUTY_CYCLE_PERIOD,
> + PWM_ASPEED_FIXED_PERIOD));
> + if (duty_pt == 0) {
> + /* emit inactive level and assert the duty counter reset */
> + clk_en = 0;
> + } else {
> + clk_en = 1;
> + if (duty_pt >= (PWM_ASPEED_FIXED_PERIOD + 1))
> + duty_pt = 0;
> + regmap_update_bits(priv->regmap,
> PWM_ASPEED_DUTY_CYCLE(hwpwm),
> + PWM_ASPEED_DUTY_CYCLE_RISING_POINT |
> + PWM_ASPEED_DUTY_CYCLE_FALLING_POINT,
> +
> FIELD_PREP(PWM_ASPEED_DUTY_CYCLE_FALLING_POINT, duty_pt));
> + }
> +
> + regmap_update_bits(priv->regmap, PWM_ASPEED_CTRL(hwpwm),
> + PWM_ASPEED_CTRL_CLK_DIV_H |
> PWM_ASPEED_CTRL_CLK_DIV_L |
> + PWM_ASPEED_CTRL_PIN_ENABLE |
> PWM_ASPEED_CTRL_CLK_ENABLE |
> + PWM_ASPEED_CTRL_INVERSE,
> + FIELD_PREP(PWM_ASPEED_CTRL_CLK_DIV_H, div_h) |
> + FIELD_PREP(PWM_ASPEED_CTRL_CLK_DIV_L, div_l) |
> + FIELD_PREP(PWM_ASPEED_CTRL_PIN_ENABLE,
> state->enabled) |
> + FIELD_PREP(PWM_ASPEED_CTRL_CLK_ENABLE, clk_en)
> |
> + FIELD_PREP(PWM_ASPEED_CTRL_INVERSE,
> state->polarity));
> + return 0;
> +}
> +
> +static const struct pwm_ops aspeed_pwm_ops = {
> + .apply = aspeed_pwm_apply,
> + .get_state = aspeed_pwm_get_state,
We got compile error because the get_state is int but return type of
aspeed_pwm_get_state is void.
We found that the get_state had been change from void to int.
Refer to linux/include/linux/pwm.h
https://github.com/torvalds/linux/commit/6c452cff79f8bf1c0146fda598d32061cfd25443
Therefore, we think the return type of aspeed_pwm_get_state should be change to int.
Could you help to revise this patch?
> + .owner = THIS_MODULE,
> +};
> +
> +static void aspeed_pwm_reset_assert(void *data) {
> + struct reset_control *rst = data;
> +
> + reset_control_assert(rst);
> +}
> +
> +static void aspeed_pwm_chip_remove(void *data) {
> + struct pwm_chip *chip = data;
> +
> + pwmchip_remove(chip);
> +}
> +
> +static int aspeed_pwm_probe(struct platform_device *pdev) {
> + struct device *dev = &pdev->dev;
> + int ret;
> + struct aspeed_pwm_data *priv;
> + struct device_node *np;
> + struct platform_device *parent_dev;
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + np = pdev->dev.parent->of_node;
> + if (!of_device_is_compatible(np, "aspeed,ast2600-pwm-tach"))
> + return dev_err_probe(dev, -ENODEV,
> + "Unsupported pwm device binding\n");
> +
> + priv->regmap = syscon_node_to_regmap(np);
> + if (IS_ERR(priv->regmap))
> + return dev_err_probe(dev, PTR_ERR(priv->regmap),
> + "Couldn't get regmap\n");
> +
> + parent_dev = of_find_device_by_node(np);
> + priv->clk = devm_clk_get_enabled(&parent_dev->dev, NULL);
> + if (IS_ERR(priv->clk))
> + return dev_err_probe(dev, PTR_ERR(priv->clk),
> + "Couldn't get clock\n");
> +
> + priv->reset = devm_reset_control_get_shared(&parent_dev->dev, NULL);
> + if (IS_ERR(priv->reset))
> + return dev_err_probe(dev, PTR_ERR(priv->reset),
> + "Couldn't get reset control\n");
> +
> + ret = reset_control_deassert(priv->reset);
> + if (ret)
> + return dev_err_probe(dev, ret,
> + "Couldn't deassert reset control\n");
> +
> + ret = devm_add_action_or_reset(dev, aspeed_pwm_reset_assert,
> + priv->reset);
> + if (ret)
> + return ret;
> +
> + priv->chip.dev = dev;
> + priv->chip.ops = &aspeed_pwm_ops;
> + priv->chip.npwm = PWM_ASPEED_NR_PWMS;
> +
> + ret = pwmchip_add(&priv->chip);
> + if (ret < 0)
> + return dev_err_probe(dev, ret, "Failed to add PWM chip\n");
> + ret = devm_add_action_or_reset(dev, aspeed_pwm_chip_remove,
> + &priv->chip);
> + if (ret)
> + return ret;
> + return 0;
> +}
> +
> +static const struct of_device_id of_pwm_match_table[] = {
> + {
> + .compatible = "aspeed,ast2600-pwm",
> + },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, of_pwm_match_table);
> +
> +static struct platform_driver aspeed_pwm_driver = {
> + .probe = aspeed_pwm_probe,
> + .driver = {
> + .name = "aspeed-pwm",
> + .of_match_table = of_pwm_match_table,
> + },
> +};
> +
> +module_platform_driver(aspeed_pwm_driver);
> +
> +MODULE_AUTHOR("Billy Tsai <[email protected]>");
> +MODULE_DESCRIPTION("Aspeed ast2600 PWM device driver");
> +MODULE_LICENSE("GPL");
> --
> 2.25.1