Hello,
Here I want to introduce a new patch series, which aims to support GMAC
functions on S32 SoCs, such as S32G2. This series is originally from NXP's
implementation on CodeAurora[1] and it will be required by upstream kernel
to configure platform settings at the DWMAC glue layer before activating
the DWMAC core on different S32G boards. In this patchset I also introduce
more register fields needed by S32 SoCs, such as higher CSR clock ranges
and cache coherency settings. For more information please see NXP's
GMACSUBSYS Reference Manual[2].
Currently, the whole architecture relies on FDTs offered by ATF[3] on
CodeAurora to keep the flexibility of handling multiple S32 platforms since
now S32 clks can be triggered via the ARM SCMI clock protocol and clk IDs/
settings can vary according to different board designs. To ensure that the
driver can work properly, the dt-binding schemas in this patchset is still
required as a reference.
Thanks,
Chester
Changes in v2:
- Fix schema issues.
- Add minItems to clocks & clock-names.
- Replace all sgmii/SGMII terms with pcs/PCS.
- clock-names: tx_sgmii -> tx_pcs, rx_sgmii -> rx_pcs
- Adjust error handlings while calling devm_clk_get().
- Remove redundant dev_info messages.
- Remove unnecessary if conditions.
- Fix the copyright format suggested by NXP.
[1] https://source.codeaurora.org/external/autobsps32/linux/tree/drivers/net/ethernet/stmicro/stmmac?h=bsp34.0-5.10.120-rt
[2] https://www.nxp.com/webapp/Download?colCode=GMACSUBSYSRM
[3] https://source.codeaurora.org/external/autobsps32/arm-trusted-firmware/tag/?h=bsp34.0-2.5
Chester Lin (5):
dt-bindings: net: snps, dwmac: add NXP S32CC support
dt-bindings: net: add schema for NXP S32CC dwmac glue driver
net: stmmac: Add CSR clock 500Mhz/800Mhz support
net: stmmac: Add AXI4 ACE control support
net: stmmac: Add NXP S32 SoC family support
.../bindings/net/nxp,s32cc-dwmac.yaml | 135 ++++++++
.../devicetree/bindings/net/snps,dwmac.yaml | 5 +-
drivers/net/ethernet/stmicro/stmmac/Kconfig | 13 +
drivers/net/ethernet/stmicro/stmmac/Makefile | 1 +
drivers/net/ethernet/stmicro/stmmac/common.h | 2 +
.../net/ethernet/stmicro/stmmac/dwmac-s32cc.c | 304 ++++++++++++++++++
.../net/ethernet/stmicro/stmmac/dwmac4_dma.c | 10 +
.../net/ethernet/stmicro/stmmac/dwmac4_dma.h | 4 +-
drivers/net/ethernet/stmicro/stmmac/hwif.h | 5 +
.../net/ethernet/stmicro/stmmac/stmmac_main.c | 7 +
include/linux/stmmac.h | 9 +
11 files changed, 492 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/net/nxp,s32cc-dwmac.yaml
create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-s32cc.c
--
2.37.3
Add a new compatible string for NXP S32CC DWMAC glue driver. The maxItems
of clock and clock-names need be increased because S32CC has up to 11
clocks for its DWMAC.
Signed-off-by: Chester Lin <[email protected]>
---
No change in v2.
Documentation/devicetree/bindings/net/snps,dwmac.yaml | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml
index 13b984076af5..c174d173591e 100644
--- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml
+++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml
@@ -65,6 +65,7 @@ properties:
- ingenic,x2000-mac
- loongson,ls2k-dwmac
- loongson,ls7a-dwmac
+ - nxp,s32cc-dwmac
- renesas,r9a06g032-gmac
- renesas,rzn1-gmac
- rockchip,px30-gmac
@@ -110,7 +111,7 @@ properties:
clocks:
minItems: 1
- maxItems: 8
+ maxItems: 11
additionalItems: true
items:
- description: GMAC main clock
@@ -122,7 +123,7 @@ properties:
clock-names:
minItems: 1
- maxItems: 8
+ maxItems: 11
additionalItems: true
contains:
enum:
--
2.37.3
Add additional 500Mhz/800Mhz CSR clock ranges since NXP S32CC DWMAC can
support higher frequencies.
Signed-off-by: Jan Petrous <[email protected]>
Signed-off-by: Chester Lin <[email protected]>
---
No change in v2.
drivers/net/ethernet/stmicro/stmmac/common.h | 2 ++
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 4 ++++
include/linux/stmmac.h | 2 ++
3 files changed, 8 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h
index 6b5d96bced47..5b7e8cc70439 100644
--- a/drivers/net/ethernet/stmicro/stmmac/common.h
+++ b/drivers/net/ethernet/stmicro/stmmac/common.h
@@ -222,6 +222,8 @@ struct stmmac_safety_stats {
#define CSR_F_150M 150000000
#define CSR_F_250M 250000000
#define CSR_F_300M 300000000
+#define CSR_F_500M 500000000
+#define CSR_F_800M 800000000
#define MAC_CSR_H_FRQ_MASK 0x20
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 6b43da78cdf0..ff0b32c9e748 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -323,6 +323,10 @@ static void stmmac_clk_csr_set(struct stmmac_priv *priv)
priv->clk_csr = STMMAC_CSR_150_250M;
else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M))
priv->clk_csr = STMMAC_CSR_250_300M;
+ else if ((clk_rate >= CSR_F_300M) && (clk_rate < CSR_F_500M))
+ priv->clk_csr = STMMAC_CSR_300_500M;
+ else if ((clk_rate >= CSR_F_500M) && (clk_rate < CSR_F_800M))
+ priv->clk_csr = STMMAC_CSR_500_800M;
}
if (priv->plat->has_sun8i) {
diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
index fb2e88614f5d..307980c808f7 100644
--- a/include/linux/stmmac.h
+++ b/include/linux/stmmac.h
@@ -34,6 +34,8 @@
#define STMMAC_CSR_35_60M 0x3 /* MDC = clk_scr_i/26 */
#define STMMAC_CSR_150_250M 0x4 /* MDC = clk_scr_i/102 */
#define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/122 */
+#define STMMAC_CSR_300_500M 0x6 /* MDC = clk_scr_i/204 */
+#define STMMAC_CSR_500_800M 0x7 /* MDC = clk_scr_i/324 */
/* MTL algorithms identifiers */
#define MTL_TX_ALGORITHM_WRR 0x0
--
2.37.3
Hi Chester,
Am 28.11.22 um 06:49 schrieb Chester Lin:
> Add a new compatible string for NXP S32CC DWMAC glue driver. The maxItems
> of clock and clock-names need be increased because S32CC has up to 11
> clocks for its DWMAC.
>
> Signed-off-by: Chester Lin <[email protected]>
> ---
>
> No change in v2.
>
> Documentation/devicetree/bindings/net/snps,dwmac.yaml | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml
> index 13b984076af5..c174d173591e 100644
> --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml
> +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml
> @@ -65,6 +65,7 @@ properties:
> - ingenic,x2000-mac
> - loongson,ls2k-dwmac
> - loongson,ls7a-dwmac
> + - nxp,s32cc-dwmac
As we had discussed offline, please change this to nxp,s32g2-dwmac.
S32G3 and S32R45 can then reuse it if they don't require changes; there
is no difference here to how i.MX family or other vendors inherit IP
across SoC models, so Rob's rules apply equally.
Also affects the following patches.
Thanks,
Andreas
> - renesas,r9a06g032-gmac
> - renesas,rzn1-gmac
> - rockchip,px30-gmac
[snip]
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