Those pixel formats are used in Synaptics's VideoSmart series SoCs,
likes VS640, VS680. I just disclose the pixel formats used in the video
codecs and display pipeline this time. Actually any device connected to
the MTR module could support those tiling and compressed pixel formats.
https://synaptics.com/products/multimedia-solutions
Changelog:
v5:
Moving back the document and rewriting the description.
v4:
Removed the patches for V4L2, V4L2 would use the drm_fourcc.h .
Moving the documents to the mesa project.
v3:
There was a mistake in format macro.
Correcting the description of 64L4 variant modifiers.
v2:
The DRM modifiers in the first draft is too simple, it can't tell
the tiles in group attribute in memory layout.
Removing the v4l2 fourcc. Adding a document for the future v4l2 extended
fmt.
v1:
first draft of DRM modifiers
Try to put basic tile formats into v4l2 fourcc
Hsia-Jun(Randy) Li (1):
drm/fourcc: Add Synaptics VideoSmart tiled modifiers
Randy Li (1):
Documentation/gpu: Add Synaptics tiling formats documentation
Documentation/gpu/drivers.rst | 1 +
Documentation/gpu/synaptics.rst | 104 ++++++++++++++++++++++++++++++++
include/uapi/drm/drm_fourcc.h | 76 +++++++++++++++++++++++
3 files changed, 181 insertions(+)
create mode 100644 Documentation/gpu/synaptics.rst
--
2.37.3
From: Randy Li <[email protected]>
Signed-off-by: Randy Li <[email protected]>
Signed-off-by: Hsia-Jun(Randy) Li <[email protected]>
---
Documentation/gpu/drivers.rst | 1 +
Documentation/gpu/synaptics.rst | 104 ++++++++++++++++++++++++++++++++
2 files changed, 105 insertions(+)
create mode 100644 Documentation/gpu/synaptics.rst
diff --git a/Documentation/gpu/drivers.rst b/Documentation/gpu/drivers.rst
index 3a52f48215a3..7e820c93d994 100644
--- a/Documentation/gpu/drivers.rst
+++ b/Documentation/gpu/drivers.rst
@@ -18,6 +18,7 @@ GPU Driver Documentation
xen-front
afbc
komeda-kms
+ synaptics
.. only:: subproject and html
diff --git a/Documentation/gpu/synaptics.rst b/Documentation/gpu/synaptics.rst
new file mode 100644
index 000000000000..b0564d2fe3ce
--- /dev/null
+++ b/Documentation/gpu/synaptics.rst
@@ -0,0 +1,104 @@
+.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
+
+================
+Synaptics Tiling
+================
+
+The tiling pixel formats in Synpatics Video Smart platform have
+many variants. Tiles could form the group of tiles(GOT), pixels
+within a group rectangle are stored into tile.
+There are two parameters which consist a modifier described
+the (nearest) width and height pixels in a group.
+
+Meanwhile, the tile in a group may not follow dimension
+layout, tile could form a small group of tiles, then that (sub)group
+of tiles would form a bigger group. We won't describe the dimension
+layout inside the group of tiles here. The layout of the group
+of tiles is fixed with the group width and height parameters
+in the same generation of the platform.
+
+Compression
+===========
+The proprietary lossless image compression protocol in Synaptics
+could minimizes the amount of data transferred (less memory bandwidth
+consumption) between devices. It would usually apply to the tiling
+pixel format.
+
+Each component would request an extra page aligned length buffer
+for storing the compression meta data. Also a 32 bytes parameters
+set would come with a compression meta data buffer.
+
+The component here corresponds to a signal type (i.e. Luma, Chroma).
+They could be encoded into one or multiple metadata planes, but
+their compression parameters would still be individual.
+
+Pixel format modifiers
+======================
+Addition alignment requirement for stride and size of a memory plane
+could apply beyond what has been mentioned below. Remember always
+negotiating with all the devices in pipeline before allocation.
+
+.. raw:: latex
+
+ \small
+
+.. tabularcolumns:: |p{5.8cm}|p{1.2cm}|p{10.3cm}|
+
+.. cssclass:: longtable
+
+.. flat-table:: Synpatics Image Format Modifiers
+ :header-rows: 1
+ :stub-columns: 0
+ :widths: 3 1 8
+
+ * - Identifier
+ - Fourcc
+ - Details
+ * .. _DRM-FORMAT-MOD-SYNA-V4H1
+
+ - ``DRM_FORMAT_MOD_SYNA_V4H1``
+ - ``DRM_FORMAT_NV12``
+ - The plain uncompressed 8 bits tile format. It sounds similar to
+ Intel's Y-tile. but it won't take any pixel from the next X direction
+ in a tile group. The line stride and image height must be aligned to
+ a multiple of 16. The height of chrominance plane would plus 8.
+ * .. _DRM-FORMAT-MOD-SYNA-V4H3P8
+
+ - ``DRM_FORMAT_MOD_SYNA_V4H3P8``
+ - ``DRM_FORMAT_NV15``
+ - The plain uncompressed 10 bits tile format. It stores pixel in 2D
+ 3x4 tiles with a 8bits padding to each of tile. Then a tile is in a
+ 128 bits cache line.
+ * .. _DRM-FORMAT-MOD-SYNA-V4H1-64L4-COMPRESSED
+
+ - ``DRM_FORMAT_MOD_SYNA_V4H1_64L4_COMPRESSED``
+ - ``DRM_FORMAT_NV12``
+ - Group of tiles and compressed variant of ``DRM_FORMAT_MOD_SYNA_V4H1``.
+ A group of tiles would contain 64x4 pixels, where a tile has 1x4
+ pixel.
+ * .. _DRM-FORMAT-MOD-SYNA-V4H3P8-64L4-COMPRESSED
+
+ - ``DRM_FORMAT_MOD_SYNA_V4H3P8_64L4_COMPRESSED``
+ - ``DRM_FORMAT_NV15``
+ - Group of tiles and compressed variant of ``DRM_FORMAT_MOD_SYNA_V4H3P8``.
+ A group of tiles would contains 48x4 pixels, where a tile has 3x4 pixels
+ and a 8 bits padding in the end of a tile. A group of tiles would
+ be 256 bytes.
+ * .. _DRM-FORMAT-MOD-SYNA-V4H1-128L128-COMPRESSED
+
+ - ``DRM_FORMAT_MOD_SYNA_V4H1_128L128_COMPRESSED``
+ - ``DRM_FORMAT_NV12``
+ - Group of tiles and compressed variant of ``DRM_FORMAT_MOD_SYNA_V4H1``.
+ A group of tiles would contain 128x32 pixels, where a tile has 1x4 pixel.
+ * .. _DRM-FORMAT-MOD-SYNA-V4H3P8-128L128-COMPRESSED
+
+ - ``DRM_FORMAT_MOD_SYNA_V4H3P8_128L128_COMPRESSED``
+ - ``DRM_FORMAT_NV15``
+ - Group of tiles and compressed variant of ``DRM_FORMAT_MOD_SYNA_V4H3P8``.
+ A group of tiles would contains 96x128 pixels, where a tile has 3x4 pixels
+ and a 8 bits padding in the end of a tile. A group of tiles would
+ be 16 KiB.
+
+.. raw:: latex
+
+ \normalsize
--
2.37.3
Hi Hsia-Jun,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-misc/drm-misc-next]
[also build test WARNING on drm/drm-next drm-exynos/exynos-drm-next drm-intel/for-linux-next drm-intel/for-linux-next-fixes drm-tip/drm-tip linus/master v6.1-rc7 next-20221130]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Hsia-Jun-Li/Add-pixel-formats-used-in-Synatpics-SoC/20221130-172411
base: git://anongit.freedesktop.org/drm/drm-misc drm-misc-next
patch link: https://lore.kernel.org/r/20221130092149.102788-3-randy.li%40synaptics.com
patch subject: [PATCH v5 2/2] Documentation/gpu: Add Synaptics tiling formats documentation
reproduce:
# https://github.com/intel-lab-lkp/linux/commit/7f84f8d9c98d589eb7283261c18f3702e69e236d
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Hsia-Jun-Li/Add-pixel-formats-used-in-Synatpics-SoC/20221130-172411
git checkout 7f84f8d9c98d589eb7283261c18f3702e69e236d
make menuconfig
# enable CONFIG_COMPILE_TEST, CONFIG_WARN_MISSING_DOCUMENTS, CONFIG_WARN_ABI_ERRORS
make htmldocs
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <[email protected]>
All warnings (new ones prefixed by >>):
>> Documentation/gpu/synaptics.rst:57: WARNING: malformed hyperlink target.
vim +57 Documentation/gpu/synaptics.rst
48
49 .. flat-table:: Synpatics Image Format Modifiers
50 :header-rows: 1
51 :stub-columns: 0
52 :widths: 3 1 8
53
54 * - Identifier
55 - Fourcc
56 - Details
> 57 * .. _DRM-FORMAT-MOD-SYNA-V4H1
58
59 - ``DRM_FORMAT_MOD_SYNA_V4H1``
60 - ``DRM_FORMAT_NV12``
61 - The plain uncompressed 8 bits tile format. It sounds similar to
62 Intel's Y-tile. but it won't take any pixel from the next X direction
63 in a tile group. The line stride and image height must be aligned to
64 a multiple of 16. The height of chrominance plane would plus 8.
65 * .. _DRM-FORMAT-MOD-SYNA-V4H3P8
66
67 - ``DRM_FORMAT_MOD_SYNA_V4H3P8``
68 - ``DRM_FORMAT_NV15``
69 - The plain uncompressed 10 bits tile format. It stores pixel in 2D
70 3x4 tiles with a 8bits padding to each of tile. Then a tile is in a
71 128 bits cache line.
72 * .. _DRM-FORMAT-MOD-SYNA-V4H1-64L4-COMPRESSED
73
74 - ``DRM_FORMAT_MOD_SYNA_V4H1_64L4_COMPRESSED``
75 - ``DRM_FORMAT_NV12``
76 - Group of tiles and compressed variant of ``DRM_FORMAT_MOD_SYNA_V4H1``.
77 A group of tiles would contain 64x4 pixels, where a tile has 1x4
78 pixel.
79 * .. _DRM-FORMAT-MOD-SYNA-V4H3P8-64L4-COMPRESSED
80
81 - ``DRM_FORMAT_MOD_SYNA_V4H3P8_64L4_COMPRESSED``
82 - ``DRM_FORMAT_NV15``
83 - Group of tiles and compressed variant of ``DRM_FORMAT_MOD_SYNA_V4H3P8``.
84 A group of tiles would contains 48x4 pixels, where a tile has 3x4 pixels
85 and a 8 bits padding in the end of a tile. A group of tiles would
86 be 256 bytes.
87 * .. _DRM-FORMAT-MOD-SYNA-V4H1-128L128-COMPRESSED
88
89 - ``DRM_FORMAT_MOD_SYNA_V4H1_128L128_COMPRESSED``
90 - ``DRM_FORMAT_NV12``
91 - Group of tiles and compressed variant of ``DRM_FORMAT_MOD_SYNA_V4H1``.
92 A group of tiles would contain 128x32 pixels, where a tile has 1x4 pixel.
93 * .. _DRM-FORMAT-MOD-SYNA-V4H3P8-128L128-COMPRESSED
94
95 - ``DRM_FORMAT_MOD_SYNA_V4H3P8_128L128_COMPRESSED``
96 - ``DRM_FORMAT_NV15``
97 - Group of tiles and compressed variant of ``DRM_FORMAT_MOD_SYNA_V4H3P8``.
98 A group of tiles would contains 96x128 pixels, where a tile has 3x4 pixels
99 and a 8 bits padding in the end of a tile. A group of tiles would
100 be 16 KiB.
101
--
0-DAY CI Kernel Test Service
https://01.org/lkp