This patch series adds bunch of new nodes
also it fixes some small nitpicks in yamls and adds compatible.
Changes since v1
================
1. Changed title for mdss yaml patch
2. Added missing dmas to spi0
3. Wired freq domains to CPUs
4. Added R-b/Ack tags
5. Reworded smmu dts patch
Adam Skladowski (12):
dt-bindings: display: msm: Rename mdss node name in example
dt-bindings: thermal: tsens: Add SM6115 compatible
arm64: dts: qcom: sm6115: Add cpufreq-hw support
arm64: dts: qcom: sm6115: Add TSENS node
arm64: dts: qcom: sm6115: Add PRNG node
arm64: dts: qcom: sm6115: Add rpm-stats node
arm64: dts: qcom: sm6115: Add dispcc node
arm64: dts: qcom: sm6115: Add mdss/dpu node
arm64: dts: qcom: sm6115: Add GPI DMA
arm64: dts: qcom: sm6115: Add i2c/spi nodes
arm64: dts: qcom: sm6115: Add WCN node.
arm64: dts: qcom: sm6115: Add smmu fallback to qcom generic compatible
.../display/msm/qcom,qcm2290-mdss.yaml | 2 +-
.../display/msm/qcom,sm6115-mdss.yaml | 2 +-
.../bindings/thermal/qcom-tsens.yaml | 1 +
arch/arm64/boot/dts/qcom/sm6115.dtsi | 573 +++++++++++++++++-
4 files changed, 575 insertions(+), 3 deletions(-)
--
2.25.1
Add GPI DMA node which will be wired to i2c/spi/uart.
Signed-off-by: Adam Skladowski <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
---
arch/arm64/boot/dts/qcom/sm6115.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
index c476b5ecb62b..b30a5485671d 100644
--- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
@@ -681,6 +681,26 @@ ufs_mem_phy_lanes: phy@4807400 {
};
};
+ gpi_dma0: dma-controller@4a00000 {
+ compatible = "qcom,sm6115-gpi-dma", "qcom,sm6350-gpi-dma";
+ reg = <0x04a00000 0x60000>;
+ interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <10>;
+ dma-channel-mask = <0xf>;
+ iommus = <&apps_smmu 0xf6 0x0>;
+ #dma-cells = <3>;
+ status = "disabled";
+ };
+
usb_1: usb@4ef8800 {
compatible = "qcom,sm6115-dwc3", "qcom,dwc3";
reg = <0x04ef8800 0x400>;
--
2.25.1
Follow other YAMLs and replace mdss name into display-subystem.
Signed-off-by: Adam Skladowski <[email protected]>
---
.../devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml | 2 +-
.../devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml
index d6f043a4b08d..4795e13c7b59 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml
@@ -72,7 +72,7 @@ examples:
#include <dt-bindings/interconnect/qcom,qcm2290.h>
#include <dt-bindings/power/qcom-rpmpd.h>
- mdss@5e00000 {
+ display-subsystem@5e00000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "qcom,qcm2290-mdss";
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml
index a86d7f53fa84..886858ef6700 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml
@@ -62,7 +62,7 @@ examples:
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
- mdss@5e00000 {
+ display-subsystem@5e00000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "qcom,sm6115-mdss";
--
2.25.1
Add rpm stats node.
Signed-off-by: Adam Skladowski <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
---
arch/arm64/boot/dts/qcom/sm6115.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
index 6f4c36f3da40..d0928f19965f 100644
--- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
@@ -546,6 +546,11 @@ rpm_msg_ram: sram@45f0000 {
reg = <0x045f0000 0x7000>;
};
+ sram@4690000 {
+ compatible = "qcom,rpm-stats";
+ reg = <0x04690000 0x10000>;
+ };
+
sdhc_1: mmc@4744000 {
compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5";
reg = <0x04744000 0x1000>, <0x04745000 0x1000>, <0x04748000 0x8000>;
--
2.25.1
Add a node for the PRNG to enable hw-accelerated pseudo-random number
generation.
Signed-off-by: Adam Skladowski <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
---
arch/arm64/boot/dts/qcom/sm6115.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
index a2ac06f4693b..6f4c36f3da40 100644
--- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
@@ -505,6 +505,13 @@ qusb2_hstx_trim: hstx-trim@25b {
};
};
+ rng: rng@1b53000 {
+ compatible = "qcom,prng-ee";
+ reg = <0x01b53000 0x1000>;
+ clocks = <&gcc GCC_PRNG_AHB_CLK>;
+ clock-names = "core";
+ };
+
spmi_bus: spmi@1c40000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x01c40000 0x1100>,
--
2.25.1
Add display clock controller to allow controlling display related clocks.
Signed-off-by: Adam Skladowski <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
---
arch/arm64/boot/dts/qcom/sm6115.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
index d0928f19965f..6e0699649257 100644
--- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
@@ -4,6 +4,7 @@
*/
#include <dt-bindings/clock/qcom,gcc-sm6115.h>
+#include <dt-bindings/clock/qcom,sm6115-dispcc.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -725,6 +726,19 @@ usb_1_dwc3: usb@4e00000 {
};
};
+ dispcc: clock-controller@5f00000 {
+ compatible = "qcom,sm6115-dispcc";
+ reg = <0x05f00000 0x20000>;
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
+ <&sleep_clk>,
+ <&dsi0_phy 0>,
+ <&dsi0_phy 1>,
+ <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
apps_smmu: iommu@c600000 {
compatible = "qcom,sm6115-smmu-500", "arm,mmu-500";
reg = <0x0c600000 0x80000>;
--
2.25.1
Document compatible for tsens on Qualcomm SM6115 platform
according to downstream dts it ship v2.4 of IP
Signed-off-by: Adam Skladowski <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
---
Documentation/devicetree/bindings/thermal/qcom-tsens.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
index 038d81338fcf..c41fcf404117 100644
--- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
+++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
@@ -53,6 +53,7 @@ properties:
- qcom,sc8280xp-tsens
- qcom,sdm630-tsens
- qcom,sdm845-tsens
+ - qcom,sm6115-tsens
- qcom,sm6350-tsens
- qcom,sm8150-tsens
- qcom,sm8250-tsens
--
2.25.1
Add nodes required for TSENS block using the common qcom,tsens-v2 binding.
Signed-off-by: Adam Skladowski <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
---
arch/arm64/boot/dts/qcom/sm6115.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
index 2a55087b103e..a2ac06f4693b 100644
--- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
@@ -523,6 +523,17 @@ spmi_bus: spmi@1c40000 {
#interrupt-cells = <4>;
};
+ tsens0: thermal-sensor@4410000 {
+ compatible = "qcom,sm6115-tsens", "qcom,tsens-v2";
+ reg = <0x04411000 0x1ff>, /* TM */
+ <0x04410000 0x8>; /* SROT */
+ #qcom,sensors = <16>;
+ interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow", "critical";
+ #thermal-sensor-cells = <1>;
+ };
+
rpm_msg_ram: sram@45f0000 {
compatible = "qcom,rpm-msg-ram";
reg = <0x045f0000 0x7000>;
--
2.25.1
Add WCN node to allow using wifi module.
Signed-off-by: Adam Skladowski <[email protected]>
---
arch/arm64/boot/dts/qcom/sm6115.dtsi | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
index e676b9d117e3..38b903592a57 100644
--- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
@@ -1305,6 +1305,28 @@ apps_smmu: iommu@c600000 {
<GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
};
+ wifi: wifi@c800000 {
+ compatible = "qcom,wcn3990-wifi";
+ reg = <0x0c800000 0x800000>;
+ reg-names = "membase";
+ memory-region = <&wlan_msa_mem>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&apps_smmu 0x1a0 0x1>;
+ qcom,msa-fixed-perm;
+ status = "disabled";
+ };
+
apcs_glb: mailbox@f111000 {
compatible = "qcom,sm6115-apcs-hmss-global";
reg = <0x0f111000 0x1000>;
--
2.25.1
Add I2C/SPI nodes for SM6115.
Signed-off-by: Adam Skladowski <[email protected]>
---
arch/arm64/boot/dts/qcom/sm6115.dtsi | 290 +++++++++++++++++++++++++++
1 file changed, 290 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
index b30a5485671d..e676b9d117e3 100644
--- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/clock/qcom,gcc-sm6115.h>
#include <dt-bindings/clock/qcom,sm6115-dispcc.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
@@ -365,6 +366,90 @@ tlmm: pinctrl@500000 {
interrupt-controller;
#interrupt-cells = <2>;
+ qup_i2c0_default: qup-i2c0-default-state {
+ pins = "gpio0", "gpio1";
+ function = "qup0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c1_default: qup-i2c1-default-state {
+ pins = "gpio4", "gpio5";
+ function = "qup1";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c2_default: qup-i2c2-default-state {
+ pins = "gpio6", "gpio7";
+ function = "qup2";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c3_default: qup-i2c3-default-state {
+ pins = "gpio8", "gpio9";
+ function = "qup3";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c4_default: qup-i2c4-default-state {
+ pins = "gpio12", "gpio13";
+ function = "qup4";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c5_default: qup-i2c5-default-state {
+ pins = "gpio14", "gpio15";
+ function = "qup5";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi0_default: qup-spi0-default-state {
+ pins = "gpio0", "gpio1","gpio2", "gpio3";
+ function = "qup0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi1_default: qup-spi1-default-state {
+ pins = "gpio4", "gpio5", "gpio69", "gpio70";
+ function = "qup1";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi2_default: qup-spi2-default-state {
+ pins = "gpio6", "gpio7", "gpio71", "gpio80";
+ function = "qup2";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi3_default: qup-spi3-default-state {
+ pins = "gpio8", "gpio9", "gpio10", "gpio11";
+ function = "qup3";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi4_default: qup-spi4-default-state {
+ pins = "gpio12", "gpio13", "gpio96", "gpio97";
+ function = "qup4";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi5_default: qup-spi5-default-state {
+ pins = "gpio14", "gpio15", "gpio16", "gpio17";
+ function = "qup5";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
sdc1_state_on: sdc1-on-state {
clk-pins {
pins = "sdc1_clk";
@@ -701,6 +786,211 @@ gpi_dma0: dma-controller@4a00000 {
status = "disabled";
};
+ qupv3_id_0: geniqup@4ac0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x04ac0000 0x2000>;
+ clock-names = "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ iommus = <&apps_smmu 0xe3 0x0>;
+ ranges;
+ status = "disabled";
+
+ i2c0: i2c@4a80000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x04a80000 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c0_default>;
+ interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 0 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi0: spi@4a80000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x04a80000 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi0_default>;
+ interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 0 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@4a84000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x04a84000 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c1_default>;
+ interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 1 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi1: spi@4a84000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x04a84000 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi1_default>;
+ interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 1 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@4a88000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x04a88000 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c2_default>;
+ interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 2 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi2: spi@4a88000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x04a88000 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi2_default>;
+ interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 2 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@4a8c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x04a8c000 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c3_default>;
+ interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 3 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi3: spi@4a8c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x04a8c000 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi3_default>;
+ interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 3 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@4a90000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x04a90000 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c4_default>;
+ interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 4 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi4: spi@4a90000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x04a90000 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi4_default>;
+ interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 4 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@4a94000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x04a94000 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c5_default>;
+ interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 5 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi5: spi@4a94000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x04a94000 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi5_default>;
+ interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 5 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
usb_1: usb@4ef8800 {
compatible = "qcom,sm6115-dwc3", "qcom,dwc3";
reg = <0x04ef8800 0x400>;
--
2.25.1
On 30/11/2022 21:09, Adam Skladowski wrote:
> Add WCN node to allow using wifi module.
>
A nit: Drop full stop from commit subject.
Best regards,
Krzysztof
On 30/11/2022 21:09, Adam Skladowski wrote:
> Follow other YAMLs and replace mdss name into display-subystem.
>
> Signed-off-by: Adam Skladowski <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On Wed, 30 Nov 2022 21:09:40 +0100, Adam Skladowski wrote:
> Document compatible for tsens on Qualcomm SM6115 platform
> according to downstream dts it ship v2.4 of IP
>
> Signed-off-by: Adam Skladowski <[email protected]>
> Acked-by: Krzysztof Kozlowski <[email protected]>
> ---
> Documentation/devicetree/bindings/thermal/qcom-tsens.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Since Daniel is out, applied, thanks!
On 30/11/2022 22:09, Adam Skladowski wrote:
> Follow other YAMLs and replace mdss name into display-subystem.
>
> Signed-off-by: Adam Skladowski <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
We will pick this into msm-fixes during the next cycle.
> ---
> .../devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml | 2 +-
> .../devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml
> index d6f043a4b08d..4795e13c7b59 100644
> --- a/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml
> +++ b/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml
> @@ -72,7 +72,7 @@ examples:
> #include <dt-bindings/interconnect/qcom,qcm2290.h>
> #include <dt-bindings/power/qcom-rpmpd.h>
>
> - mdss@5e00000 {
> + display-subsystem@5e00000 {
> #address-cells = <1>;
> #size-cells = <1>;
> compatible = "qcom,qcm2290-mdss";
> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml
> index a86d7f53fa84..886858ef6700 100644
> --- a/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml
> +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml
> @@ -62,7 +62,7 @@ examples:
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/power/qcom-rpmpd.h>
>
> - mdss@5e00000 {
> + display-subsystem@5e00000 {
> #address-cells = <1>;
> #size-cells = <1>;
> compatible = "qcom,sm6115-mdss";
--
With best wishes
Dmitry
On 30.11.2022 21:09, Adam Skladowski wrote:
> Add I2C/SPI nodes for SM6115.
>
> Signed-off-by: Adam Skladowski <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
> arch/arm64/boot/dts/qcom/sm6115.dtsi | 290 +++++++++++++++++++++++++++
> 1 file changed, 290 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
> index b30a5485671d..e676b9d117e3 100644
> --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
> @@ -6,6 +6,7 @@
> #include <dt-bindings/clock/qcom,gcc-sm6115.h>
> #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
> #include <dt-bindings/clock/qcom,rpmcc.h>
> +#include <dt-bindings/dma/qcom-gpi.h>
> #include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/power/qcom-rpmpd.h>
> @@ -365,6 +366,90 @@ tlmm: pinctrl@500000 {
> interrupt-controller;
> #interrupt-cells = <2>;
>
> + qup_i2c0_default: qup-i2c0-default-state {
> + pins = "gpio0", "gpio1";
> + function = "qup0";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + qup_i2c1_default: qup-i2c1-default-state {
> + pins = "gpio4", "gpio5";
> + function = "qup1";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + qup_i2c2_default: qup-i2c2-default-state {
> + pins = "gpio6", "gpio7";
> + function = "qup2";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + qup_i2c3_default: qup-i2c3-default-state {
> + pins = "gpio8", "gpio9";
> + function = "qup3";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + qup_i2c4_default: qup-i2c4-default-state {
> + pins = "gpio12", "gpio13";
> + function = "qup4";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + qup_i2c5_default: qup-i2c5-default-state {
> + pins = "gpio14", "gpio15";
> + function = "qup5";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + qup_spi0_default: qup-spi0-default-state {
> + pins = "gpio0", "gpio1","gpio2", "gpio3";
> + function = "qup0";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + qup_spi1_default: qup-spi1-default-state {
> + pins = "gpio4", "gpio5", "gpio69", "gpio70";
> + function = "qup1";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + qup_spi2_default: qup-spi2-default-state {
> + pins = "gpio6", "gpio7", "gpio71", "gpio80";
> + function = "qup2";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + qup_spi3_default: qup-spi3-default-state {
> + pins = "gpio8", "gpio9", "gpio10", "gpio11";
> + function = "qup3";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + qup_spi4_default: qup-spi4-default-state {
> + pins = "gpio12", "gpio13", "gpio96", "gpio97";
> + function = "qup4";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + qup_spi5_default: qup-spi5-default-state {
> + pins = "gpio14", "gpio15", "gpio16", "gpio17";
> + function = "qup5";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> sdc1_state_on: sdc1-on-state {
> clk-pins {
> pins = "sdc1_clk";
> @@ -701,6 +786,211 @@ gpi_dma0: dma-controller@4a00000 {
> status = "disabled";
> };
>
> + qupv3_id_0: geniqup@4ac0000 {
> + compatible = "qcom,geni-se-qup";
> + reg = <0x04ac0000 0x2000>;
> + clock-names = "m-ahb", "s-ahb";
> + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
> + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + iommus = <&apps_smmu 0xe3 0x0>;
> + ranges;
> + status = "disabled";
> +
> + i2c0: i2c@4a80000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0x04a80000 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c0_default>;
> + interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
> + <&gpi_dma0 1 0 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + spi0: spi@4a80000 {
> + compatible = "qcom,geni-spi";
> + reg = <0x04a80000 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_spi0_default>;
> + interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
> + <&gpi_dma0 1 0 QCOM_GPI_SPI>;
> + dma-names = "tx", "rx";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c1: i2c@4a84000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0x04a84000 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c1_default>;
> + interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
> + <&gpi_dma0 1 1 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + spi1: spi@4a84000 {
> + compatible = "qcom,geni-spi";
> + reg = <0x04a84000 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_spi1_default>;
> + interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
> + <&gpi_dma0 1 1 QCOM_GPI_SPI>;
> + dma-names = "tx", "rx";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c2: i2c@4a88000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0x04a88000 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c2_default>;
> + interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
> + <&gpi_dma0 1 2 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + spi2: spi@4a88000 {
> + compatible = "qcom,geni-spi";
> + reg = <0x04a88000 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_spi2_default>;
> + interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
> + <&gpi_dma0 1 2 QCOM_GPI_SPI>;
> + dma-names = "tx", "rx";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c3: i2c@4a8c000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0x04a8c000 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c3_default>;
> + interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
> + <&gpi_dma0 1 3 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + spi3: spi@4a8c000 {
> + compatible = "qcom,geni-spi";
> + reg = <0x04a8c000 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_spi3_default>;
> + interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
> + <&gpi_dma0 1 3 QCOM_GPI_SPI>;
> + dma-names = "tx", "rx";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c4: i2c@4a90000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0x04a90000 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c4_default>;
> + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
> + <&gpi_dma0 1 4 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + spi4: spi@4a90000 {
> + compatible = "qcom,geni-spi";
> + reg = <0x04a90000 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_spi4_default>;
> + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
> + <&gpi_dma0 1 4 QCOM_GPI_SPI>;
> + dma-names = "tx", "rx";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c5: i2c@4a94000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0x04a94000 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c5_default>;
> + interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
> + <&gpi_dma0 1 5 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + spi5: spi@4a94000 {
> + compatible = "qcom,geni-spi";
> + reg = <0x04a94000 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_spi5_default>;
> + interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
> + <&gpi_dma0 1 5 QCOM_GPI_SPI>;
> + dma-names = "tx", "rx";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> + };
> +
> usb_1: usb@4ef8800 {
> compatible = "qcom,sm6115-dwc3", "qcom,dwc3";
> reg = <0x04ef8800 0x400>;
On Thu, Dec 01, 2022 at 11:38:16AM +0100, Krzysztof Kozlowski wrote:
> On 30/11/2022 21:09, Adam Skladowski wrote:
> > Add WCN node to allow using wifi module.
> >
>
> A nit: Drop full stop from commit subject.
>
Done. Thanks for pointing it out :)
Regards,
Bjorn
> Best regards,
> Krzysztof
>
On Wed, 30 Nov 2022 21:09:38 +0100, Adam Skladowski wrote:
> This patch series adds bunch of new nodes
> also it fixes some small nitpicks in yamls and adds compatible.
>
> Changes since v1
> ================
> 1. Changed title for mdss yaml patch
> 2. Added missing dmas to spi0
> 3. Wired freq domains to CPUs
> 4. Added R-b/Ack tags
> 5. Reworded smmu dts patch
>
> [...]
Applied, thanks!
[03/12] arm64: dts: qcom: sm6115: Add cpufreq-hw support
commit: aff96846c63ed3e3ed7d5212ea636a422d9694a3
[04/12] arm64: dts: qcom: sm6115: Add TSENS node
commit: 7b74cba6b13f4bbe1f15e3417f386ed1907ab0ef
[05/12] arm64: dts: qcom: sm6115: Add PRNG node
commit: fc676b15c065b8d4c750bbaab9914f24829a7a13
[06/12] arm64: dts: qcom: sm6115: Add rpm-stats node
commit: d18c0077963ae2b6d232f6f3f25fb1ceb875ce7f
[07/12] arm64: dts: qcom: sm6115: Add dispcc node
commit: 884f95411ba4030ca44436217c6d8df4a960c555
[08/12] arm64: dts: qcom: sm6115: Add mdss/dpu node
commit: 705e50427d8148211ffd05922bfa6a2520781338
[09/12] arm64: dts: qcom: sm6115: Add GPI DMA
commit: 1586c5793511d7fb389139ab7aa5dae9118666ad
[10/12] arm64: dts: qcom: sm6115: Add i2c/spi nodes
commit: 323647d32e83fae7f1a81b40e12ca6b0b63e880c
[11/12] arm64: dts: qcom: sm6115: Add WCN node.
commit: 245bb9a37c16dc324be60764aa2597aa4704a8e3
[12/12] arm64: dts: qcom: sm6115: Add smmu fallback to qcom generic compatible
commit: 58a9e83605478e931139b574e43d453851de3a26
Best regards,
--
Bjorn Andersson <[email protected]>
On 12/1/2022 11:54 AM, Dmitry Baryshkov wrote:
> On 30/11/2022 22:09, Adam Skladowski wrote:
>> Follow other YAMLs and replace mdss name into display-subystem.
>>
>> Signed-off-by: Adam Skladowski <[email protected]>
>
> Reviewed-by: Dmitry Baryshkov <[email protected]>
Going to add two fixes tags here as we are touching two chipsets:
Fixes: b93bdff44a85 ("dt-bindings: display/msm: add support for SM6115")
Fixes: 06097b13ef97 ("dt-bindings: display/msm: split dpu-qcm2290 into
DPU and MDSS parts")
Reviewed-by: Abhinav Kumar <[email protected]>
>
> We will pick this into msm-fixes during the next cycle.
Yes, we can with the above fixes tags but first, can you please send a
MR from msm-next-lumag to msm-next? So that I can send a MR for fixes to
msm-next.
ATM, they are out of sync.
>
>> ---
>> .../devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml | 2 +-
>> .../devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml | 2 +-
>> 2 files changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git
>> a/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml
>> b/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml
>> index d6f043a4b08d..4795e13c7b59 100644
>> ---
>> a/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml
>> +++
>> b/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml
>> @@ -72,7 +72,7 @@ examples:
>> #include <dt-bindings/interconnect/qcom,qcm2290.h>
>> #include <dt-bindings/power/qcom-rpmpd.h>
>> - mdss@5e00000 {
>> + display-subsystem@5e00000 {
>> #address-cells = <1>;
>> #size-cells = <1>;
>> compatible = "qcom,qcm2290-mdss";
>> diff --git
>> a/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml
>> b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml
>> index a86d7f53fa84..886858ef6700 100644
>> --- a/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml
>> +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml
>> @@ -62,7 +62,7 @@ examples:
>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>> #include <dt-bindings/power/qcom-rpmpd.h>
>> - mdss@5e00000 {
>> + display-subsystem@5e00000 {
>> #address-cells = <1>;
>> #size-cells = <1>;
>> compatible = "qcom,sm6115-mdss";
>
On 13 December 2022 23:53:48 EET, Abhinav Kumar <[email protected]> wrote:
>
>
>On 12/1/2022 11:54 AM, Dmitry Baryshkov wrote:
>> On 30/11/2022 22:09, Adam Skladowski wrote:
>>> Follow other YAMLs and replace mdss name into display-subystem.
>>>
>>> Signed-off-by: Adam Skladowski <[email protected]>
>>
>> Reviewed-by: Dmitry Baryshkov <[email protected]>
>
>Going to add two fixes tags here as we are touching two chipsets:
>
>Fixes: b93bdff44a85 ("dt-bindings: display/msm: add support for SM6115")
>Fixes: 06097b13ef97 ("dt-bindings: display/msm: split dpu-qcm2290 into DPU and MDSS parts")
Note, your tag gif wrapped, so patchwork will pick it up incorrectly.
>
>Reviewed-by: Abhinav Kumar <[email protected]>
>
>>
>> We will pick this into msm-fixes during the next cycle.
>
>Yes, we can with the above fixes tags but first, can you please send a MR from msm-next-lumag to msm-next? So that I can send a MR for fixes to msm-next.
This would create an additional merge commit in msm-next for no particular reason. You can branch -fixes from rc1, or from the msm-next-lumag and then send MR to msm-next.
>
>ATM, they are out of sync.
>
>
>>
>>> ---
>>> .../devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml | 2 +-
>>> .../devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml | 2 +-
>>> 2 files changed, 2 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml
>>> index d6f043a4b08d..4795e13c7b59 100644
>>> --- a/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml
>>> +++ b/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml
>>> @@ -72,7 +72,7 @@ examples:
>>> #include <dt-bindings/interconnect/qcom,qcm2290.h>
>>> #include <dt-bindings/power/qcom-rpmpd.h>
>>> - mdss@5e00000 {
>>> + display-subsystem@5e00000 {
>>> #address-cells = <1>;
>>> #size-cells = <1>;
>>> compatible = "qcom,qcm2290-mdss";
>>> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml
>>> index a86d7f53fa84..886858ef6700 100644
>>> --- a/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml
>>> +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml
>>> @@ -62,7 +62,7 @@ examples:
>>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>>> #include <dt-bindings/power/qcom-rpmpd.h>
>>> - mdss@5e00000 {
>>> + display-subsystem@5e00000 {
>>> #address-cells = <1>;
>>> #size-cells = <1>;
>>> compatible = "qcom,sm6115-mdss";
>>
--
With best wishes
Dmitry
On 12/13/2022 2:11 PM, Dmitry Baryshkov wrote:
>
>
> On 13 December 2022 23:53:48 EET, Abhinav Kumar <[email protected]> wrote:
>>
>>
>> On 12/1/2022 11:54 AM, Dmitry Baryshkov wrote:
>>> On 30/11/2022 22:09, Adam Skladowski wrote:
>>>> Follow other YAMLs and replace mdss name into display-subystem.
>>>>
>>>> Signed-off-by: Adam Skladowski <[email protected]>
>>>
>>> Reviewed-by: Dmitry Baryshkov <[email protected]>
>>
>> Going to add two fixes tags here as we are touching two chipsets:
>>
>> Fixes: b93bdff44a85 ("dt-bindings: display/msm: add support for SM6115")
>> Fixes: 06097b13ef97 ("dt-bindings: display/msm: split dpu-qcm2290 into DPU and MDSS parts")
>
> Note, your tag gif wrapped, so patchwork will pick it up incorrectly.
Yes, this is a mail client issue. Am aware of it , will fix it up when i
apply it.
>
>>
>> Reviewed-by: Abhinav Kumar <[email protected]>
>>
>>>
>>> We will pick this into msm-fixes during the next cycle.
>>
>> Yes, we can with the above fixes tags but first, can you please send a MR from msm-next-lumag to msm-next? So that I can send a MR for fixes to msm-next.
>
> This would create an additional merge commit in msm-next for no particular reason. You can branch -fixes from rc1, or from the msm-next-lumag and then send MR to msm-next.
So msm-next would need to be updated then to rc1 to accept that MR. Rob?
>
>>
>> ATM, they are out of sync.
>>
>>
>>>
>>>> ---
>>>> .../devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml | 2 +-
>>>> .../devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml | 2 +-
>>>> 2 files changed, 2 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml
>>>> index d6f043a4b08d..4795e13c7b59 100644
>>>> --- a/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml
>>>> +++ b/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml
>>>> @@ -72,7 +72,7 @@ examples:
>>>> #include <dt-bindings/interconnect/qcom,qcm2290.h>
>>>> #include <dt-bindings/power/qcom-rpmpd.h>
>>>> - mdss@5e00000 {
>>>> + display-subsystem@5e00000 {
>>>> #address-cells = <1>;
>>>> #size-cells = <1>;
>>>> compatible = "qcom,qcm2290-mdss";
>>>> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml
>>>> index a86d7f53fa84..886858ef6700 100644
>>>> --- a/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml
>>>> +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml
>>>> @@ -62,7 +62,7 @@ examples:
>>>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>>>> #include <dt-bindings/power/qcom-rpmpd.h>
>>>> - mdss@5e00000 {
>>>> + display-subsystem@5e00000 {
>>>> #address-cells = <1>;
>>>> #size-cells = <1>;
>>>> compatible = "qcom,sm6115-mdss";
>>>
>
14 декабря 2022 г. 00:11:58 GMT+02:00, Dmitry Baryshkov <[email protected]> пишет:
>
>
>On 13 December 2022 23:53:48 EET, Abhinav Kumar <[email protected]> wrote:
>>
>>
>>On 12/1/2022 11:54 AM, Dmitry Baryshkov wrote:
>>> On 30/11/2022 22:09, Adam Skladowski wrote:
>>
>>>
>>> We will pick this into msm-fixes during the next cycle.
>>
>>Yes, we can with the above fixes tags but first, can you please send a MR from msm-next-lumag to msm-next? So that I can send a MR for fixes to msm-next.
>
>This would create an additional merge commit in msm-next for no particular reason. You can branch -fixes from rc1, or from the msm-next-lumag and then send MR to msm-next.
Another option would be to base msm-fixes on drm-next directly.
>
>>
>>ATM, they are out of sync.
>>
>>