In the latest JEDEC standard (JESD216F), there are now bitfields in the
4 byte address instruction table for 1S-1S-8S and 1S-8S-8S modes
This patchset adds support for checking the 4BAIT for these modes,
along with additional NO_SFDP_FLAGS to support enabling these new modes
v2: Move page program commands into sfdp.c instead of core.c,
as this appears to conform more closely with spi-nor paradigm.
Page program buswidth appears to be automatically determined, so let's
follow suit and do the same.
Nathan Barrett-Morrison (3):
mtd: spi-nor: Extend SFDP 4byte address instruction lookup table with
new octal modes as per JEDEC JESD216F
mtd: spi-nor: Add additional octal-mode flags to be checked during
SFDP
mtd: spi-nor: Add support for IS25LX256 operating in 1S-1S-8S octal
read mode
drivers/mtd/spi-nor/core.c | 7 +++++++
drivers/mtd/spi-nor/core.h | 5 +++--
drivers/mtd/spi-nor/issi.c | 2 ++
drivers/mtd/spi-nor/sfdp.c | 13 +++++++++++++
4 files changed, 25 insertions(+), 2 deletions(-)
--
2.30.2
This adds some support for searching a chips SFDP table for:
read commands: 1S-8S-8S
program commands: 1S-1S-8S, 1S-8S-8S
Signed-off-by: Nathan Barrett-Morrison <[email protected]>
---
drivers/mtd/spi-nor/core.c | 7 +++++++
drivers/mtd/spi-nor/core.h | 5 +++--
drivers/mtd/spi-nor/sfdp.c | 8 ++++++++
3 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index bee8fc4c9f07..4c1a877e736f 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -2359,6 +2359,13 @@ static void spi_nor_no_sfdp_init_params(struct spi_nor *nor)
SNOR_PROTO_1_1_8);
}
+ if (no_sfdp_flags & SPI_NOR_OCTAL_READ_1_8_8) {
+ params->hwcaps.mask |= SNOR_HWCAPS_READ_1_8_8;
+ spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_8_8],
+ 0, 16, SPINOR_OP_READ_1_8_8,
+ SNOR_PROTO_1_8_8);
+ }
+
if (no_sfdp_flags & SPI_NOR_OCTAL_DTR_READ) {
params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR;
spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_8_8_8_DTR],
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index 85b0cf254e97..7bc1cde049b7 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -514,8 +514,9 @@ struct flash_info {
#define SPI_NOR_DUAL_READ BIT(3)
#define SPI_NOR_QUAD_READ BIT(4)
#define SPI_NOR_OCTAL_READ BIT(5)
-#define SPI_NOR_OCTAL_DTR_READ BIT(6)
-#define SPI_NOR_OCTAL_DTR_PP BIT(7)
+#define SPI_NOR_OCTAL_READ_1_8_8 BIT(6)
+#define SPI_NOR_OCTAL_DTR_READ BIT(7)
+#define SPI_NOR_OCTAL_DTR_PP BIT(8)
u8 fixup_flags;
#define SPI_NOR_4B_OPCODES BIT(0)
diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c
index e4e87815ba94..e1b7547bf81e 100644
--- a/drivers/mtd/spi-nor/sfdp.c
+++ b/drivers/mtd/spi-nor/sfdp.c
@@ -1089,6 +1089,14 @@ static int spi_nor_parse_4bait(struct spi_nor *nor,
spi_nor_set_pp_settings(¶ms_pp[SNOR_CMD_PP_1_4_4],
SPINOR_OP_PP_1_4_4_4B,
SNOR_PROTO_1_4_4);
+ if (pp_hwcaps & SNOR_HWCAPS_PP_1_1_8)
+ spi_nor_set_pp_settings(¶ms_pp[SNOR_CMD_PP_1_1_8],
+ SPINOR_OP_PP_1_1_8_4B,
+ SNOR_PROTO_1_1_8);
+ if (pp_hwcaps & SNOR_HWCAPS_PP_1_8_8)
+ spi_nor_set_pp_settings(¶ms_pp[SNOR_CMD_PP_1_8_8],
+ SPINOR_OP_PP_1_8_8_4B,
+ SNOR_PROTO_1_8_8);
for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) {
if (erase_mask & BIT(i))
--
2.30.2
This adds the IS25LX256 chip into the ISSI flash_info parts table
Signed-off-by: Nathan Barrett-Morrison <[email protected]>
---
drivers/mtd/spi-nor/issi.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mtd/spi-nor/issi.c b/drivers/mtd/spi-nor/issi.c
index 89a66a19d754..f00f1e621d84 100644
--- a/drivers/mtd/spi-nor/issi.c
+++ b/drivers/mtd/spi-nor/issi.c
@@ -74,6 +74,8 @@ static const struct flash_info issi_nor_parts[] = {
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
.fixups = &is25lp256_fixups },
+ { "is25lx256", INFO(0x9d5a19, 0, 128 * 1024, 256)
+ NO_SFDP_FLAGS(SECT_4K | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_READ) },
/* PMC */
{ "pm25lv512", INFO(0, 0, 32 * 1024, 2)
--
2.30.2