mt8195 and mt8192 have different clock numbers, separate 'clock-names'
according to compatible name.
Signed-off-by: Yunfei Dong <[email protected]>
---
compared with v3:
- rewrite clock-names according to different platforms.
Reference series:
[1]: v5 of this series is presend by Allen-KH Cheng.
message-id: [email protected]
---
.../media/mediatek,vcodec-subdev-decoder.yaml | 41 ++++++++++++++++---
1 file changed, 35 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
index 7c5b4a91c59b..a08b2c814f40 100644
--- a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
@@ -110,15 +110,12 @@ patternProperties:
Refer to bindings/iommu/mediatek,iommu.yaml.
clocks:
+ minItems: 1
maxItems: 5
clock-names:
- items:
- - const: sel
- - const: soc-vdec
- - const: soc-lat
- - const: vdec
- - const: top
+ minItems: 1
+ maxItems: 5
assigned-clocks:
maxItems: 1
@@ -159,6 +156,38 @@ then:
required:
- interrupts
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - mediatek,mt8192-vcodec-dec
+ then:
+ properties:
+ clock-names:
+ items:
+ - const: sel
+ - const: soc-vdec
+ - const: soc-lat
+ - const: vdec
+ - const: top
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - mediatek,mt8195-vcodec-dec
+ then:
+ properties:
+ clock-names:
+ items:
+ - const: sel
+ - const: vdec
+ - const: lat
+ - const: top
+
additionalProperties: false
examples:
--
2.18.0
Add video decoder node to mt8195 device tree.
Signed-off-by: Yunfei Dong <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 70 ++++++++++++++++++++++++
1 file changed, 70 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 905d1a90b406..6829aa0dcf4c 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1874,6 +1874,76 @@
power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
};
+ video-codec@18000000 {
+ compatible = "mediatek,mt8195-vcodec-dec";
+ mediatek,scp = <&scp>;
+ iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0 0x18000000 0 0x1000>,
+ <0 0x18004000 0 0x1000>;
+ ranges = <0 0 0 0x18000000 0 0x26000>;
+
+ video-codec@2000 {
+ compatible = "mediatek,mtk-vcodec-lat-soc";
+ reg = <0 0x2000 0 0x800>;
+ iommus = <&iommu_vpp M4U_PORT_L23_VDEC_UFO_ENC_EXT>,
+ <&iommu_vpp M4U_PORT_L23_VDEC_RDMA_EXT>;
+ clocks = <&topckgen CLK_TOP_VDEC>,
+ <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
+ <&vdecsys_soc CLK_VDEC_SOC_LAT>,
+ <&topckgen CLK_TOP_UNIVPLL_D4>;
+ clock-names = "sel", "vdec", "lat", "top";
+ assigned-clocks = <&topckgen CLK_TOP_VDEC>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
+ };
+
+ video-codec@10000 {
+ compatible = "mediatek,mtk-vcodec-lat";
+ reg = <0 0x10000 0 0x800>;
+ interrupts = <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD_EXT>,
+ <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD2_EXT>,
+ <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_AVC_MC_EXT>,
+ <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_PRED_RD_EXT>,
+ <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_TILE_EXT>,
+ <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_WDMA_EXT>;
+ clocks = <&topckgen CLK_TOP_VDEC>,
+ <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
+ <&vdecsys_soc CLK_VDEC_SOC_LAT>,
+ <&topckgen CLK_TOP_UNIVPLL_D4>;
+ clock-names = "sel", "vdec", "lat", "top";
+ assigned-clocks = <&topckgen CLK_TOP_VDEC>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
+ };
+
+ video-codec@25000 {
+ compatible = "mediatek,mtk-vcodec-core";
+ reg = <0 0x25000 0 0x1000>; /* VDEC_CORE_MISC */
+ interrupts = <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>,
+ <&iommu_vdo M4U_PORT_L21_VDEC_UFO_EXT>,
+ <&iommu_vdo M4U_PORT_L21_VDEC_PP_EXT>,
+ <&iommu_vdo M4U_PORT_L21_VDEC_PRED_RD_EXT>,
+ <&iommu_vdo M4U_PORT_L21_VDEC_PRED_WR_EXT>,
+ <&iommu_vdo M4U_PORT_L21_VDEC_PPWRAP_EXT>,
+ <&iommu_vdo M4U_PORT_L21_VDEC_TILE_EXT>,
+ <&iommu_vdo M4U_PORT_L21_VDEC_VLD_EXT>,
+ <&iommu_vdo M4U_PORT_L21_VDEC_VLD2_EXT>,
+ <&iommu_vdo M4U_PORT_L21_VDEC_AVC_MV_EXT>;
+ clocks = <&topckgen CLK_TOP_VDEC>,
+ <&vdecsys CLK_VDEC_VDEC>,
+ <&vdecsys CLK_VDEC_LAT>,
+ <&topckgen CLK_TOP_UNIVPLL_D4>;
+ clock-names = "sel", "vdec", "lat", "top";
+ assigned-clocks = <&topckgen CLK_TOP_VDEC>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
+ };
+ };
+
larb24: larb@1800d000 {
compatible = "mediatek,mt8195-smi-larb";
reg = <0 0x1800d000 0 0x1000>;
--
2.18.0
Need to add racing control register base in device node for mt8195 support
inner racing mode. Changing the max reg value from 1 to 2.
Adding the description for VDEC_SYS and VDEC_MISC.
Signed-off-by: Yunfei Dong <[email protected]>
Acked-by: Rob Herring <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
---
.../bindings/media/mediatek,vcodec-subdev-decoder.yaml | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
index a08b2c814f40..fffed7f515ae 100644
--- a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
@@ -61,7 +61,10 @@ properties:
- mediatek,mt8195-vcodec-dec
reg:
- maxItems: 1
+ minItems: 1
+ items:
+ - description: VDEC_SYS register space
+ - description: VDEC_RACING_CTRL register space
iommus:
minItems: 1
@@ -98,6 +101,7 @@ patternProperties:
reg:
maxItems: 1
+ description: VDEC_MISC register space
interrupts:
maxItems: 1
--
2.18.0
On Fri, Dec 02, 2022 at 11:44:48AM +0800, Yunfei Dong wrote:
> mt8195 and mt8192 have different clock numbers, separate 'clock-names'
> according to compatible name.
>
> Signed-off-by: Yunfei Dong <[email protected]>
> ---
> compared with v3:
> - rewrite clock-names according to different platforms.
>
> Reference series:
> [1]: v5 of this series is presend by Allen-KH Cheng.
> message-id: [email protected]
> ---
> .../media/mediatek,vcodec-subdev-decoder.yaml | 41 ++++++++++++++++---
> 1 file changed, 35 insertions(+), 6 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
> index 7c5b4a91c59b..a08b2c814f40 100644
> --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
> +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
> @@ -110,15 +110,12 @@ patternProperties:
> Refer to bindings/iommu/mediatek,iommu.yaml.
>
> clocks:
> + minItems: 1
Why 1? Looks like it should be 4 or 5 clocks.
> maxItems: 5
>
> clock-names:
> - items:
> - - const: sel
> - - const: soc-vdec
> - - const: soc-lat
> - - const: vdec
> - - const: top
> + minItems: 1
> + maxItems: 5
>
> assigned-clocks:
> maxItems: 1
> @@ -159,6 +156,38 @@ then:
> required:
> - interrupts
>
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - mediatek,mt8192-vcodec-dec
> + then:
> + properties:
> + clock-names:
> + items:
> + - const: sel
> + - const: soc-vdec
> + - const: soc-lat
> + - const: vdec
> + - const: top
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - mediatek,mt8195-vcodec-dec
> + then:
> + properties:
> + clock-names:
> + items:
> + - const: sel
> + - const: vdec
> + - const: lat
> + - const: top
> +
> additionalProperties: false
>
> examples:
> --
> 2.18.0
>
>
Hi Rob,
Thanks for your suggestion.
On Mon, 2022-12-05 at 11:54 -0600, Rob Herring wrote:
> On Fri, Dec 02, 2022 at 11:44:48AM +0800, Yunfei Dong wrote:
> > mt8195 and mt8192 have different clock numbers, separate 'clock-
> > names'
> > according to compatible name.
> >
> > Signed-off-by: Yunfei Dong <[email protected]>
> > ---
> > compared with v3:
> > - rewrite clock-names according to different platforms.
> >
> > Reference series:
> > [1]: v5 of this series is presend by Allen-KH Cheng.
> > message-id: [email protected]
> > ---
> > .../media/mediatek,vcodec-subdev-decoder.yaml | 41
> > ++++++++++++++++---
> > 1 file changed, 35 insertions(+), 6 deletions(-)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-
> > decoder.yaml
> > b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-
> > decoder.yaml
> > index 7c5b4a91c59b..a08b2c814f40 100644
> > --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-
> > subdev-decoder.yaml
> > +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-
> > subdev-decoder.yaml
> > @@ -110,15 +110,12 @@ patternProperties:
> > Refer to bindings/iommu/mediatek,iommu.yaml.
> >
> > clocks:
> > + minItems: 1
>
> Why 1? Looks like it should be 4 or 5 clocks.
>
Yes, I should write this vale to 4, will change it again if 1 is used
in the future.
Best regards,
Yunfei Dong
> > maxItems: 5
> >
> > clock-names:
> > - items:
> > - - const: sel
> > - - const: soc-vdec
> > - - const: soc-lat
> > - - const: vdec
> > - - const: top
> > + minItems: 1
> > + maxItems: 5
> >
> > assigned-clocks:
> > maxItems: 1
> > @@ -159,6 +156,38 @@ then:
> > required:
> > - interrupts
> >
> > +allOf:
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - mediatek,mt8192-vcodec-dec
> > + then:
> > + properties:
> > + clock-names:
> > + items:
> > + - const: sel
> > + - const: soc-vdec
> > + - const: soc-lat
> > + - const: vdec
> > + - const: top
> > +
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - mediatek,mt8195-vcodec-dec
> > + then:
> > + properties:
> > + clock-names:
> > + items:
> > + - const: sel
> > + - const: vdec
> > + - const: lat
> > + - const: top
> > +
> > additionalProperties: false
> >
> > examples:
> > --
> > 2.18.0
> >
> >