This patch series add MediaTek MT7986 SPI NAND and ECC controller
support, split ECC engine with rawnand controller in bindings and
hange to YAML schema.
Changes since V1:
- Use existing sample delay property.
- Add restricting for optional nfi_hclk.
- Improve and perfect dt-bindings documentation.
- Change existing node name to match NAND controller DT bingings.
- Fix issues reported by dt_binding_check.
- Fix issues reported by dtbs_check.
Xiangsheng Hou (9):
spi: mtk-snfi: Add snfi support for MT7986 IC
spi: mtk-snfi: Change default page format to setup default setting
spi: mtk-snfi: Add optional nfi_hclk which needed for MT7986
mtd: nand: ecc-mtk: Add ECC support fot MT7986 IC
dt-bindings: spi: mtk-snfi: Add compatible for MT7986
spi: mtk-snfi: Add snfi sample delay and read latency adjustment
dt-bindings: spi: mtk-snfi: Add read latch latency property
dt-bindings: mtd: Split ECC engine with rawnand controller
dt-bindings: mtd: ecc-mtk: Add compatible for MT7986
.../bindings/mtd/mediatek,mtk-nfc.yaml | 171 +++++++++++++++++
.../mtd/mediatek,nand-ecc-engine.yaml | 63 +++++++
.../devicetree/bindings/mtd/mtk-nand.txt | 176 ------------------
.../bindings/spi/mediatek,spi-mtk-snfi.yaml | 58 +++++-
arch/arm/boot/dts/mt2701.dtsi | 2 +-
arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 2 +-
arch/arm64/boot/dts/mediatek/mt7622.dtsi | 2 +-
drivers/mtd/nand/ecc-mtk.c | 18 ++
drivers/spi/spi-mtk-snfi.c | 66 ++++++-
9 files changed, 366 insertions(+), 192 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mtd/mediatek,mtk-nfc.yaml
create mode 100644 Documentation/devicetree/bindings/mtd/mediatek,nand-ecc-engine.yaml
delete mode 100644 Documentation/devicetree/bindings/mtd/mtk-nand.txt
--
2.25.1
Add snfi support for MT7986 IC.
Signed-off-by: Xiangsheng Hou <[email protected]>
---
drivers/spi/spi-mtk-snfi.c | 29 +++++++++++++++++++++++++++--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-mtk-snfi.c b/drivers/spi/spi-mtk-snfi.c
index d66bf9762557..fa8412ba20e2 100644
--- a/drivers/spi/spi-mtk-snfi.c
+++ b/drivers/spi/spi-mtk-snfi.c
@@ -126,7 +126,8 @@
#define STR_DATA BIT(0)
#define NFI_STA 0x060
-#define NFI_NAND_FSM GENMASK(28, 24)
+#define NFI_NAND_FSM_7622 GENMASK(28, 24)
+#define NFI_NAND_FSM_7986 GENMASK(29, 23)
#define NFI_FSM GENMASK(19, 16)
#define READ_EMPTY BIT(12)
@@ -158,6 +159,7 @@
#define MAS_WR GENMASK(5, 3)
#define MAS_RDDLY GENMASK(2, 0)
#define NFI_MASTERSTA_MASK_7622 (MAS_ADDR | MAS_RD | MAS_WR | MAS_RDDLY)
+#define NFI_MASTERSTA_MASK_7986 3
// SNFI registers
#define SNF_MAC_CTL 0x500
@@ -220,6 +222,11 @@
static const u8 mt7622_spare_sizes[] = { 16, 26, 27, 28 };
+static const u8 mt7986_spare_sizes[] = {
+ 16, 26, 27, 28, 32, 36, 40, 44, 48, 49, 50, 51, 52, 62, 61, 63, 64, 67,
+ 74
+};
+
struct mtk_snand_caps {
u16 sector_size;
u16 max_sectors;
@@ -230,6 +237,7 @@ struct mtk_snand_caps {
bool bbm_swap;
bool empty_page_check;
u32 mastersta_mask;
+ u32 nandfsm_mask;
const u8 *spare_sizes;
u32 num_spare_size;
@@ -244,6 +252,7 @@ static const struct mtk_snand_caps mt7622_snand_caps = {
.bbm_swap = false,
.empty_page_check = false,
.mastersta_mask = NFI_MASTERSTA_MASK_7622,
+ .nandfsm_mask = NFI_NAND_FSM_7622,
.spare_sizes = mt7622_spare_sizes,
.num_spare_size = ARRAY_SIZE(mt7622_spare_sizes)
};
@@ -257,10 +266,25 @@ static const struct mtk_snand_caps mt7629_snand_caps = {
.bbm_swap = true,
.empty_page_check = false,
.mastersta_mask = NFI_MASTERSTA_MASK_7622,
+ .nandfsm_mask = NFI_NAND_FSM_7622,
.spare_sizes = mt7622_spare_sizes,
.num_spare_size = ARRAY_SIZE(mt7622_spare_sizes)
};
+static const struct mtk_snand_caps mt7986_snand_caps = {
+ .sector_size = 1024,
+ .max_sectors = 8,
+ .fdm_size = 8,
+ .fdm_ecc_size = 1,
+ .fifo_size = 64,
+ .bbm_swap = true,
+ .empty_page_check = true,
+ .mastersta_mask = NFI_MASTERSTA_MASK_7986,
+ .nandfsm_mask = NFI_NAND_FSM_7986,
+ .spare_sizes = mt7986_spare_sizes,
+ .num_spare_size = ARRAY_SIZE(mt7986_spare_sizes)
+};
+
struct mtk_snand_conf {
size_t page_size;
size_t oob_size;
@@ -360,7 +384,7 @@ static int mtk_nfi_reset(struct mtk_snand *snf)
}
ret = readl_poll_timeout(snf->nfi_base + NFI_STA, val,
- !(val & (NFI_FSM | NFI_NAND_FSM)), 0,
+ !(val & (NFI_FSM | snf->caps->nandfsm_mask)), 0,
SNFI_POLL_INTERVAL);
if (ret) {
dev_err(snf->dev, "Failed to reset NFI\n");
@@ -1295,6 +1319,7 @@ static irqreturn_t mtk_snand_irq(int irq, void *id)
static const struct of_device_id mtk_snand_ids[] = {
{ .compatible = "mediatek,mt7622-snand", .data = &mt7622_snand_caps },
{ .compatible = "mediatek,mt7629-snand", .data = &mt7629_snand_caps },
+ { .compatible = "mediatek,mt7986-snand", .data = &mt7986_snand_caps },
{},
};
--
2.25.1
Add ECC support fot MT7986 IC.
Signed-off-by: Xiangsheng Hou <[email protected]>
---
drivers/mtd/nand/ecc-mtk.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/drivers/mtd/nand/ecc-mtk.c b/drivers/mtd/nand/ecc-mtk.c
index 9f9b201fe706..c2f6cfa76a04 100644
--- a/drivers/mtd/nand/ecc-mtk.c
+++ b/drivers/mtd/nand/ecc-mtk.c
@@ -79,6 +79,10 @@ static const u8 ecc_strength_mt7622[] = {
4, 6, 8, 10, 12
};
+static const u8 ecc_strength_mt7986[] = {
+ 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24
+};
+
enum mtk_ecc_regs {
ECC_ENCPAR00,
ECC_ENCIRQ_EN,
@@ -483,6 +487,17 @@ static const struct mtk_ecc_caps mtk_ecc_caps_mt7622 = {
.pg_irq_sel = 0,
};
+static const struct mtk_ecc_caps mtk_ecc_caps_mt7986 = {
+ .err_mask = 0x1f,
+ .err_shift = 8,
+ .ecc_strength = ecc_strength_mt7986,
+ .ecc_regs = mt2712_ecc_regs,
+ .num_ecc_strength = 11,
+ .ecc_mode_shift = 5,
+ .parity_bits = 14,
+ .pg_irq_sel = 1,
+};
+
static const struct of_device_id mtk_ecc_dt_match[] = {
{
.compatible = "mediatek,mt2701-ecc",
@@ -493,6 +508,9 @@ static const struct of_device_id mtk_ecc_dt_match[] = {
}, {
.compatible = "mediatek,mt7622-ecc",
.data = &mtk_ecc_caps_mt7622,
+ }, {
+ .compatible = "mediatek,mt7986-ecc",
+ .data = &mtk_ecc_caps_mt7986,
},
{},
};
--
2.25.1
Add snfi sample delay and read latency adjustment which can get
from dts property.
Signed-off-by: Xiangsheng Hou <[email protected]>
---
drivers/spi/spi-mtk-snfi.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/spi/spi-mtk-snfi.c b/drivers/spi/spi-mtk-snfi.c
index 85644308df23..32a9a817869c 100644
--- a/drivers/spi/spi-mtk-snfi.c
+++ b/drivers/spi/spi-mtk-snfi.c
@@ -195,6 +195,8 @@
#define DATA_READ_MODE_X4 2
#define DATA_READ_MODE_DUAL 5
#define DATA_READ_MODE_QUAD 6
+#define DATA_READ_LATCH_LAT GENMASK(9, 8)
+#define DATA_READ_LATCH_LAT_S 8
#define PG_LOAD_CUSTOM_EN BIT(7)
#define DATARD_CUSTOM_EN BIT(6)
#define CS_DESELECT_CYC_S 0
@@ -205,6 +207,9 @@
#define SNF_DLY_CTL3 0x548
#define SFCK_SAM_DLY_S 0
+#define SFCK_SAM_DLY GENMASK(5, 0)
+#define SFCK_SAM_DLY_TOTAL 9
+#define SFCK_SAM_DLY_RANGE 47
#define SNF_STA_CTL1 0x550
#define CUS_PG_DONE BIT(28)
@@ -1368,6 +1373,7 @@ static int mtk_snand_probe(struct platform_device *pdev)
const struct of_device_id *dev_id;
struct spi_controller *ctlr;
struct mtk_snand *ms;
+ u32 val = 0;
int ret;
dev_id = of_match_node(mtk_snand_ids, np);
@@ -1446,6 +1452,16 @@ static int mtk_snand_probe(struct platform_device *pdev)
// switch to SNFI mode
nfi_write32(ms, SNF_CFG, SPI_MODE);
+ ret = of_property_read_u32(np, "rx-sample-delay-ns", &val);
+ if (!ret)
+ nfi_rmw32(ms, SNF_DLY_CTL3, SFCK_SAM_DLY,
+ val * SFCK_SAM_DLY_RANGE / SFCK_SAM_DLY_TOTAL);
+
+ ret = of_property_read_u32(np, "mediatek,rx-latch-latency", &val);
+ if (!ret)
+ nfi_rmw32(ms, SNF_MISC_CTL, DATA_READ_LATCH_LAT,
+ val << DATA_READ_LATCH_LAT_S);
+
// setup an initial page format for ops matching page_cache_op template
// before ECC is called.
ret = mtk_snand_setup_pagefmt(ms, SZ_2K, SZ_64);
--
2.25.1
Il 05/12/22 07:57, Xiangsheng Hou ha scritto:
> Add snfi sample delay and read latency adjustment which can get
> from dts property.
>
> Signed-off-by: Xiangsheng Hou <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Il 05/12/22 07:57, Xiangsheng Hou ha scritto:
> Add ECC support fot MT7986 IC.
>
> Signed-off-by: Xiangsheng Hou <[email protected]>
> ---
> drivers/mtd/nand/ecc-mtk.c | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/drivers/mtd/nand/ecc-mtk.c b/drivers/mtd/nand/ecc-mtk.c
> index 9f9b201fe706..c2f6cfa76a04 100644
> --- a/drivers/mtd/nand/ecc-mtk.c
> +++ b/drivers/mtd/nand/ecc-mtk.c
> @@ -79,6 +79,10 @@ static const u8 ecc_strength_mt7622[] = {
> 4, 6, 8, 10, 12
> };
>
> +static const u8 ecc_strength_mt7986[] = {
> + 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24
> +};
> +
> enum mtk_ecc_regs {
> ECC_ENCPAR00,
> ECC_ENCIRQ_EN,
> @@ -483,6 +487,17 @@ static const struct mtk_ecc_caps mtk_ecc_caps_mt7622 = {
> .pg_irq_sel = 0,
> };
>
> +static const struct mtk_ecc_caps mtk_ecc_caps_mt7986 = {
> + .err_mask = 0x1f,
Can't we use GENMASK() to define err_mask instead?
#define MT7986_ERRNUM GENMASK(4, 0)
P.S.: Did I get that right? Is that referred to the ERRNUM(x) bits?
Regards,
Angelo
Il 05/12/22 07:57, Xiangsheng Hou ha scritto:
> Add snfi support for MT7986 IC.
>
> Signed-off-by: Xiangsheng Hou <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Hi Angelo,
On Mon, 2022-12-05 at 15:21 +0100, AngeloGioacchino Del Regno wrote:
> Il 05/12/22 07:57, Xiangsheng Hou ha scritto:
> > Add ECC support fot MT7986 IC.
> >
> > Signed-off-by: Xiangsheng Hou <[email protected]>
> > ---
> > drivers/mtd/nand/ecc-mtk.c | 18 ++++++++++++++++++
> > 1 file changed, 18 insertions(+)
> >
> > diff --git a/drivers/mtd/nand/ecc-mtk.c b/drivers/mtd/nand/ecc-
> > mtk.c
> > index 9f9b201fe706..c2f6cfa76a04 100644
> > --- a/drivers/mtd/nand/ecc-mtk.c
> > +++ b/drivers/mtd/nand/ecc-mtk.c
> > @@ -79,6 +79,10 @@ static const u8 ecc_strength_mt7622[] = {
> > 4, 6, 8, 10, 12
> > };
> >
> > +static const u8 ecc_strength_mt7986[] = {
> > + 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24
> > +};
> > +
> > enum mtk_ecc_regs {
> > ECC_ENCPAR00,
> > ECC_ENCIRQ_EN,
> > @@ -483,6 +487,17 @@ static const struct mtk_ecc_caps
> > mtk_ecc_caps_mt7622 = {
> > .pg_irq_sel = 0,
> > };
> >
> > +static const struct mtk_ecc_caps mtk_ecc_caps_mt7986 = {
> > + .err_mask = 0x1f,
>
> Can't we use GENMASK() to define err_mask instead?
>
> #define MT7986_ERRNUM GENMASK(4, 0)
>
> P.S.: Did I get that right? Is that referred to the ERRNUM(x) bits
Yes, you are right.
I will change like
#define ECC_ERRMASK(x) GENMASK(x, 0),
since other IC driver data will use 0x3f and 0x7f err_mask.
Thanks
Xiangsheng Hou
Il 06/12/22 10:04, Xiangsheng Hou (侯祥胜) ha scritto:
> Hi Angelo,
>
> On Mon, 2022-12-05 at 15:21 +0100, AngeloGioacchino Del Regno wrote:
>> Il 05/12/22 07:57, Xiangsheng Hou ha scritto:
>>> Add ECC support fot MT7986 IC.
>>>
>>> Signed-off-by: Xiangsheng Hou <[email protected]>
>>> ---
>>> drivers/mtd/nand/ecc-mtk.c | 18 ++++++++++++++++++
>>> 1 file changed, 18 insertions(+)
>>>
>>> diff --git a/drivers/mtd/nand/ecc-mtk.c b/drivers/mtd/nand/ecc-
>>> mtk.c
>>> index 9f9b201fe706..c2f6cfa76a04 100644
>>> --- a/drivers/mtd/nand/ecc-mtk.c
>>> +++ b/drivers/mtd/nand/ecc-mtk.c
>>> @@ -79,6 +79,10 @@ static const u8 ecc_strength_mt7622[] = {
>>> 4, 6, 8, 10, 12
>>> };
>>>
>>> +static const u8 ecc_strength_mt7986[] = {
>>> + 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24
>>> +};
>>> +
>>> enum mtk_ecc_regs {
>>> ECC_ENCPAR00,
>>> ECC_ENCIRQ_EN,
>>> @@ -483,6 +487,17 @@ static const struct mtk_ecc_caps
>>> mtk_ecc_caps_mt7622 = {
>>> .pg_irq_sel = 0,
>>> };
>>>
>>> +static const struct mtk_ecc_caps mtk_ecc_caps_mt7986 = {
>>> + .err_mask = 0x1f,
>>
>> Can't we use GENMASK() to define err_mask instead?
>>
>> #define MT7986_ERRNUM GENMASK(4, 0)
>>
>> P.S.: Did I get that right? Is that referred to the ERRNUM(x) bits
>
> Yes, you are right.
> I will change like
> #define ECC_ERRMASK(x) GENMASK(x, 0),
> since other IC driver data will use 0x3f and 0x7f err_mask.
>
I would prefer, instead, something like
#define MT7986_ERRNUM GENMASK(....)
#define MT7622_ERRNUM GENMASK(....)
#define MT.... (etc)
instead of a macro calling another macro.
Regards,
Angelo
On Mon, 5 Dec 2022 14:57:47 +0800, Xiangsheng Hou wrote:
> This patch series add MediaTek MT7986 SPI NAND and ECC controller
> support, split ECC engine with rawnand controller in bindings and
> hange to YAML schema.
>
> Changes since V1:
> - Use existing sample delay property.
> - Add restricting for optional nfi_hclk.
> - Improve and perfect dt-bindings documentation.
> - Change existing node name to match NAND controller DT bingings.
> - Fix issues reported by dt_binding_check.
> - Fix issues reported by dtbs_check.
>
> [...]
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
Thanks!
[1/9] spi: mtk-snfi: Add snfi support for MT7986 IC
commit: 7073888c86601389e17f3ee8ab15ab7aef148839
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
On Tue, 2022-12-06 at 13:22 +0100, AngeloGioacchino Del Regno wrote:
> Il 06/12/22 10:04, Xiangsheng Hou (侯祥胜) ha scritto:
> > Hi Angelo,
> >
> > On Mon, 2022-12-05 at 15:21 +0100, AngeloGioacchino Del Regno
> > wrote:
> > > Il 05/12/22 07:57, Xiangsheng Hou ha scritto:
> > > > Add ECC support fot MT7986 IC.
> > > >
> > > > Signed-off-by: Xiangsheng Hou <[email protected]>
> > > > ---
> > > > drivers/mtd/nand/ecc-mtk.c | 18 ++++++++++++++++++
> > > > 1 file changed, 18 insertions(+)
> > > >
> > > > diff --git a/drivers/mtd/nand/ecc-mtk.c b/drivers/mtd/nand/ecc-
> > > > mtk.c
> > > > index 9f9b201fe706..c2f6cfa76a04 100644
> > > > --- a/drivers/mtd/nand/ecc-mtk.c
> > > > +++ b/drivers/mtd/nand/ecc-mtk.c
> > > > @@ -79,6 +79,10 @@ static const u8 ecc_strength_mt7622[] = {
> > > > 4, 6, 8, 10, 12
> > > > };
> > > >
> > > > +static const u8 ecc_strength_mt7986[] = {
> > > > + 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24
> > > > +};
> > > > +
> > > > enum mtk_ecc_regs {
> > > > ECC_ENCPAR00,
> > > > ECC_ENCIRQ_EN,
> > > > @@ -483,6 +487,17 @@ static const struct mtk_ecc_caps
> > > > mtk_ecc_caps_mt7622 = {
> > > > .pg_irq_sel = 0,
> > > > };
> > > >
> > > > +static const struct mtk_ecc_caps mtk_ecc_caps_mt7986 = {
> > > > + .err_mask = 0x1f,
> > >
> > > Can't we use GENMASK() to define err_mask instead?
> > >
> > > #define MT7986_ERRNUM GENMASK(4, 0)
> > >
> > > P.S.: Did I get that right? Is that referred to the ERRNUM(x)
> > > bits
> >
> > Yes, you are right.
> > I will change like
> > #define ECC_ERRMASK(x) GENMASK(x, 0),
> > since other IC driver data will use 0x3f and 0x7f err_mask.
> >
>
> I would prefer, instead, something like
>
> #define MT7986_ERRNUM GENMASK(....)
> #define MT7622_ERRNUM GENMASK(....)
> #define MT.... (etc)
>
> instead of a macro calling another macro.
Will do.
Thanks
Xiangsheng Hou