With the decoupling of PAT and MTRR initialization, PAT will be used
even with MTRRs disabled. This seems to break booting up as TDX guest,
as the recommended sequence to set the PAT MSR across CPUs can't work
in TDX guests due to disabling caches via setting CR0.CD isn't allowed
in TDX mode.
This is an inconsistency in the Intel documentation between the SDM
and the TDX specification. For now handle TDX mode the same way as Xen
PV guest mode by just accepting the current PAT MSR setting without
trying to modify it.
Signed-off-by: Juergen Gross <[email protected]>
---
arch/x86/mm/pat/memtype.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/x86/mm/pat/memtype.c b/arch/x86/mm/pat/memtype.c
index 9aab17d660cd..4e50add760ad 100644
--- a/arch/x86/mm/pat/memtype.c
+++ b/arch/x86/mm/pat/memtype.c
@@ -296,8 +296,12 @@ void __init pat_bp_init(void)
/*
* Xen PV doesn't allow to set PAT MSR, but all cache modes are
* supported.
+ * When running as TDX guest setting the PAT MSR won't work either
+ * due to the requirement to set CR0.CD when doing so. Rely on
+ * firmware to have set the PAT MSR correctly.
*/
- if (pat_disabled || cpu_feature_enabled(X86_FEATURE_XENPV)) {
+ if (pat_disabled || cpu_feature_enabled(X86_FEATURE_XENPV) ||
+ cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) {
init_cache_modes(pat_msr_val);
return;
}
--
2.35.3
The following commit has been merged into the x86/cpu branch of tip:
Commit-ID: c11ca45441d56ed6d353548cad660e04f0b6605d
Gitweb: https://git.kernel.org/tip/c11ca45441d56ed6d353548cad660e04f0b6605d
Author: Juergen Gross <[email protected]>
AuthorDate: Mon, 05 Dec 2022 09:04:32 +01:00
Committer: Borislav Petkov (AMD) <[email protected]>
CommitterDate: Mon, 05 Dec 2022 11:03:27 +01:00
x86/pat: Handle TDX guest PAT initialization
With the decoupling of PAT and MTRR initialization, PAT will be used
even with MTRRs disabled. This seems to break booting up as TDX guest,
as the recommended sequence to set the PAT MSR across CPUs can't work
in TDX guests due to disabling caches via setting CR0.CD isn't allowed
in TDX mode.
This is an inconsistency in the Intel documentation between the SDM
and the TDX specification. For now handle TDX mode the same way as Xen
PV guest mode by just accepting the current PAT MSR setting without
trying to modify it.
[ bp: Align conditions for better readability. ]
Signed-off-by: Juergen Gross <[email protected]>
Signed-off-by: Borislav Petkov (AMD) <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
---
arch/x86/mm/pat/memtype.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/x86/mm/pat/memtype.c b/arch/x86/mm/pat/memtype.c
index 9aab17d..46de9cf 100644
--- a/arch/x86/mm/pat/memtype.c
+++ b/arch/x86/mm/pat/memtype.c
@@ -296,8 +296,13 @@ void __init pat_bp_init(void)
/*
* Xen PV doesn't allow to set PAT MSR, but all cache modes are
* supported.
+ * When running as TDX guest setting the PAT MSR won't work either
+ * due to the requirement to set CR0.CD when doing so. Rely on
+ * firmware to have set the PAT MSR correctly.
*/
- if (pat_disabled || cpu_feature_enabled(X86_FEATURE_XENPV)) {
+ if (pat_disabled ||
+ cpu_feature_enabled(X86_FEATURE_XENPV) ||
+ cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) {
init_cache_modes(pat_msr_val);
return;
}
On Mon, Dec 05, 2022 at 09:04:32AM +0100, Juergen Gross wrote:
> With the decoupling of PAT and MTRR initialization, PAT will be used
> even with MTRRs disabled. This seems to break booting up as TDX guest,
> as the recommended sequence to set the PAT MSR across CPUs can't work
> in TDX guests due to disabling caches via setting CR0.CD isn't allowed
> in TDX mode.
>
> This is an inconsistency in the Intel documentation between the SDM
> and the TDX specification. For now handle TDX mode the same way as Xen
> PV guest mode by just accepting the current PAT MSR setting without
> trying to modify it.
>
> Signed-off-by: Juergen Gross <[email protected]>
Good enough for now. I will follow up if something comes up from the
discussion around the topic.
Acked-by: Kirill A. Shutemov <[email protected]>
> ---
> arch/x86/mm/pat/memtype.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/arch/x86/mm/pat/memtype.c b/arch/x86/mm/pat/memtype.c
> index 9aab17d660cd..4e50add760ad 100644
> --- a/arch/x86/mm/pat/memtype.c
> +++ b/arch/x86/mm/pat/memtype.c
> @@ -296,8 +296,12 @@ void __init pat_bp_init(void)
> /*
> * Xen PV doesn't allow to set PAT MSR, but all cache modes are
> * supported.
> + * When running as TDX guest setting the PAT MSR won't work either
> + * due to the requirement to set CR0.CD when doing so. Rely on
> + * firmware to have set the PAT MSR correctly.
s/firmware/TDX module/
> */
> - if (pat_disabled || cpu_feature_enabled(X86_FEATURE_XENPV)) {
> + if (pat_disabled || cpu_feature_enabled(X86_FEATURE_XENPV) ||
> + cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) {
> init_cache_modes(pat_msr_val);
> return;
> }
--
Kiryl Shutsemau / Kirill A. Shutemov