LinuxLists.cc - [PATCH net-next v4 0/4] phy: aquantia: Determine rate adaptation support from registers

2022-12-16 17:02:38

Subject: [PATCH net-next v4 0/4] phy: aquantia: Determine rate adaptation support from registers

This attempts to address the problems first reported in [1]. Tim has an
Aquantia phy where the firmware is set up to use "5G XFI" (underclocked
10GBASE-R) when rate adapting lower speeds. This results in us
advertising that we support lower speeds and then failing to bring the
link up. To avoid this, determine whether to enable rate adaptation
based on what's programmed by the firmware. This is "the worst choice"
[2], but we can't really do better until we have more insight into
what the firmware is doing. At the very least, we can prevent bad
firmware from causing us to advertise the wrong modes.

Past submissions may be found at [3, 4].

[1] https://lore.kernel.org/netdev/CAJ+vNU3zeNqiGhjTKE8jRjDYR0D7f=iqPLB8phNyA2CWixy7JA@mail.gmail.com/
[2] https://lore.kernel.org/netdev/20221118171643.vu6uxbnmog4sna65@skbuf/
[3] https://lore.kernel.org/netdev/[email protected]/
[4] https://lore.kernel.org/netdev/[email protected]/

Changes in v4:
- Reorganize MDIO defines
- Fix kerneldoc using - instead of : for parameters

Changes in v3:
- Update speed register bits
- Fix incorrect bits for PMA/PMD speed

Changes in v2:
- Move/rename phylink_interface_max_speed
- Rework to just validate things instead of modifying registers

Sean Anderson (4):
net: phy: Move/rename phylink_interface_max_speed
phy: mdio: Reorganize defines
net: mdio: Update speed register bits
phy: aquantia: Determine rate adaptation support from registers

drivers/net/phy/aquantia_main.c | 160 ++++++++++++++++++++++++++++++--
drivers/net/phy/phy-core.c | 70 ++++++++++++++
drivers/net/phy/phylink.c | 75 +--------------
include/linux/phy.h | 1 +
include/uapi/linux/mdio.h | 109 ++++++++++++++--------
5 files changed, 299 insertions(+), 116 deletions(-)

--
2.35.1.1320.gc452695387.dirty

2022-12-16 17:02:58

by Sean Anderson

[permalink] [raw]

Subject: [PATCH net-next v4 1/4] net: phy: Move/rename phylink_interface_max_speed

This is really a core phy function like phy_interface_num_ports. Move it
to drivers/net/phy/phy-core.c and rename it accordingly.

Signed-off-by: Sean Anderson <[email protected]>
Reviewed-by: Russell King (Oracle) <[email protected]>
---

(no changes since v2)

Changes in v2:
- New

drivers/net/phy/phy-core.c | 70 +++++++++++++++++++++++++++++++++++
drivers/net/phy/phylink.c | 75 ++------------------------------------
include/linux/phy.h | 1 +
3 files changed, 74 insertions(+), 72 deletions(-)

diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c
index 5d08c627a516..5a515434a228 100644
--- a/drivers/net/phy/phy-core.c
+++ b/drivers/net/phy/phy-core.c
@@ -150,6 +150,76 @@ int phy_interface_num_ports(phy_interface_t interface)
}
EXPORT_SYMBOL_GPL(phy_interface_num_ports);

+/**
+ * phy_interface_max_speed() - get the maximum speed of a phy interface
+ * @interface: phy interface mode defined by &typedef phy_interface_t
+ *
+ * Determine the maximum speed of a phy interface. This is intended to help
+ * determine the correct speed to pass to the MAC when the phy is performing
+ * rate matching.
+ *
+ * Return: The maximum speed of @interface
+ */
+int phy_interface_max_speed(phy_interface_t interface)
+{
+ switch (interface) {
+ case PHY_INTERFACE_MODE_100BASEX:
+ case PHY_INTERFACE_MODE_REVRMII:
+ case PHY_INTERFACE_MODE_RMII:
+ case PHY_INTERFACE_MODE_SMII:
+ case PHY_INTERFACE_MODE_REVMII:
+ case PHY_INTERFACE_MODE_MII:
+ return SPEED_100;
+
+ case PHY_INTERFACE_MODE_TBI:
+ case PHY_INTERFACE_MODE_MOCA:
+ case PHY_INTERFACE_MODE_RTBI:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_1000BASEKX:
+ case PHY_INTERFACE_MODE_TRGMII:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_QSGMII:
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_GMII:
+ return SPEED_1000;
+
+ case PHY_INTERFACE_MODE_2500BASEX:
+ return SPEED_2500;
+
+ case PHY_INTERFACE_MODE_5GBASER:
+ return SPEED_5000;
+
+ case PHY_INTERFACE_MODE_XGMII:
+ case PHY_INTERFACE_MODE_RXAUI:
+ case PHY_INTERFACE_MODE_XAUI:
+ case PHY_INTERFACE_MODE_10GBASER:
+ case PHY_INTERFACE_MODE_10GKR:
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_QUSGMII:
+ return SPEED_10000;
+
+ case PHY_INTERFACE_MODE_25GBASER:
+ return SPEED_25000;
+
+ case PHY_INTERFACE_MODE_XLGMII:
+ return SPEED_40000;
+
+ case PHY_INTERFACE_MODE_INTERNAL:
+ case PHY_INTERFACE_MODE_NA:
+ case PHY_INTERFACE_MODE_MAX:
+ /* No idea! Garbage in, unknown out */
+ return SPEED_UNKNOWN;
+ }
+
+ /* If we get here, someone forgot to add an interface mode above */
+ WARN_ON_ONCE(1);
+ return SPEED_UNKNOWN;
+}
+EXPORT_SYMBOL_GPL(phy_interface_max_speed);
+
/* A mapping of all SUPPORTED settings to speed/duplex. This table
* must be grouped by speed and sorted in descending match priority
* - iow, descending speed.
diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index 09cc65c0da93..f8cba09f9d87 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -156,75 +156,6 @@ static const char *phylink_an_mode_str(unsigned int mode)
return mode < ARRAY_SIZE(modestr) ? modestr[mode] : "unknown";
}

-/**
- * phylink_interface_max_speed() - get the maximum speed of a phy interface
- * @interface: phy interface mode defined by &typedef phy_interface_t
- *
- * Determine the maximum speed of a phy interface. This is intended to help
- * determine the correct speed to pass to the MAC when the phy is performing
- * rate matching.
- *
- * Return: The maximum speed of @interface
- */
-static int phylink_interface_max_speed(phy_interface_t interface)
-{
- switch (interface) {
- case PHY_INTERFACE_MODE_100BASEX:
- case PHY_INTERFACE_MODE_REVRMII:
- case PHY_INTERFACE_MODE_RMII:
- case PHY_INTERFACE_MODE_SMII:
- case PHY_INTERFACE_MODE_REVMII:
- case PHY_INTERFACE_MODE_MII:
- return SPEED_100;
-
- case PHY_INTERFACE_MODE_TBI:
- case PHY_INTERFACE_MODE_MOCA:
- case PHY_INTERFACE_MODE_RTBI:
- case PHY_INTERFACE_MODE_1000BASEX:
- case PHY_INTERFACE_MODE_1000BASEKX:
- case PHY_INTERFACE_MODE_TRGMII:
- case PHY_INTERFACE_MODE_RGMII_TXID:
- case PHY_INTERFACE_MODE_RGMII_RXID:
- case PHY_INTERFACE_MODE_RGMII_ID:
- case PHY_INTERFACE_MODE_RGMII:
- case PHY_INTERFACE_MODE_QSGMII:
- case PHY_INTERFACE_MODE_SGMII:
- case PHY_INTERFACE_MODE_GMII:
- return SPEED_1000;
-
- case PHY_INTERFACE_MODE_2500BASEX:
- return SPEED_2500;
-
- case PHY_INTERFACE_MODE_5GBASER:
- return SPEED_5000;
-
- case PHY_INTERFACE_MODE_XGMII:
- case PHY_INTERFACE_MODE_RXAUI:
- case PHY_INTERFACE_MODE_XAUI:
- case PHY_INTERFACE_MODE_10GBASER:
- case PHY_INTERFACE_MODE_10GKR:
- case PHY_INTERFACE_MODE_USXGMII:
- case PHY_INTERFACE_MODE_QUSGMII:
- return SPEED_10000;
-
- case PHY_INTERFACE_MODE_25GBASER:
- return SPEED_25000;
-
- case PHY_INTERFACE_MODE_XLGMII:
- return SPEED_40000;
-
- case PHY_INTERFACE_MODE_INTERNAL:
- case PHY_INTERFACE_MODE_NA:
- case PHY_INTERFACE_MODE_MAX:
- /* No idea! Garbage in, unknown out */
- return SPEED_UNKNOWN;
- }
-
- /* If we get here, someone forgot to add an interface mode above */
- WARN_ON_ONCE(1);
- return SPEED_UNKNOWN;
-}
-
/**
* phylink_caps_to_linkmodes() - Convert capabilities to ethtool link modes
* @linkmodes: ethtool linkmode mask (must be already initialised)
@@ -435,7 +366,7 @@ unsigned long phylink_get_capabilities(phy_interface_t interface,
unsigned long mac_capabilities,
int rate_matching)
{
- int max_speed = phylink_interface_max_speed(interface);
+ int max_speed = phy_interface_max_speed(interface);
unsigned long caps = MAC_SYM_PAUSE | MAC_ASYM_PAUSE;
unsigned long matched_caps = 0;

@@ -1221,7 +1152,7 @@ static void phylink_link_up(struct phylink *pl,
* the link_state) to the interface speed, and will send
* pause frames to the MAC to limit its transmission speed.
*/
- speed = phylink_interface_max_speed(link_state.interface);
+ speed = phy_interface_max_speed(link_state.interface);
duplex = DUPLEX_FULL;
rx_pause = true;
break;
@@ -1231,7 +1162,7 @@ static void phylink_link_up(struct phylink *pl,
* the link_state) to the interface speed, and will cause
* collisions to the MAC to limit its transmission speed.
*/
- speed = phylink_interface_max_speed(link_state.interface);
+ speed = phy_interface_max_speed(link_state.interface);
duplex = DUPLEX_HALF;
break;
}
diff --git a/include/linux/phy.h b/include/linux/phy.h
index 71eeb4e3b1fd..65d21a79bab3 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -1004,6 +1004,7 @@ const char *phy_duplex_to_str(unsigned int duplex);
const char *phy_rate_matching_to_str(int rate_matching);

int phy_interface_num_ports(phy_interface_t interface);
+int phy_interface_max_speed(phy_interface_t interface);

/* A structure for mapping a particular speed and duplex
* combination to a particular SUPPORTED and ADVERTISED value
--
2.35.1.1320.gc452695387.dirty

2022-12-16 17:23:28

by Sean Anderson

[permalink] [raw]

Subject: [PATCH net-next v4 3/4] net: mdio: Update speed register bits

This updates the speed register bits to the 2018 revision of 802.3.

Signed-off-by: Sean Anderson <[email protected]>
---

(no changes since v3)

Changes in v3:
- New

include/uapi/linux/mdio.h | 7 +++++++
1 file changed, 7 insertions(+)

diff --git a/include/uapi/linux/mdio.h b/include/uapi/linux/mdio.h
index 14b779a8577b..490466f9a5c5 100644
--- a/include/uapi/linux/mdio.h
+++ b/include/uapi/linux/mdio.h
@@ -147,6 +147,7 @@
#define MDIO_SPEED_10G 0x0001 /* 10G capable */

/* PMA/PMD Speed register. */
+#define MDIO_PMA_SPEED_10G MDIO_SPEED_10G
#define MDIO_PMA_SPEED_2B 0x0002 /* 2BASE-TL capable */
#define MDIO_PMA_SPEED_10P 0x0004 /* 10PASS-TS capable */
#define MDIO_PMA_SPEED_1000 0x0010 /* 1000M capable */
@@ -154,9 +155,15 @@
#define MDIO_PMA_SPEED_10 0x0040 /* 10M capable */

/* PCS et al. Speed register. */
+#define MDIO_PCS_SPEED_10G MDIO_SPEED_10G
#define MDIO_PCS_SPEED_10P2B 0x0002 /* 10PASS-TS/2BASE-TL capable */
+#define MDIO_PCS_SPEED_40G 0x0004 /* 450G capable */
+#define MDIO_PCS_SPEED_100G 0x0008 /* 100G capable */
+#define MDIO_PCS_SPEED_25G 0x0010 /* 25G capable */
#define MDIO_PCS_SPEED_2_5G 0x0040 /* 2.5G capable */
#define MDIO_PCS_SPEED_5G 0x0080 /* 5G capable */
+#define MDIO_PCS_SPEED_200G 0x0100 /* 200G capable */
+#define MDIO_PCS_SPEED_400G 0x0200 /* 400G capable */

/* Device present registers. */
#define MDIO_DEVS_PRESENT(devad) (1 << (devad))
--
2.35.1.1320.gc452695387.dirty

2022-12-16 17:24:10

by Sean Anderson

[permalink] [raw]

Subject: [PATCH net-next v4 2/4] phy: mdio: Reorganize defines

Reorder all registers to be grouped by MMD. Groups fields in
similarly-named registers in the same way. This is especially useful for
registers which may have some bits in common, but interpret other bits
in different ways. The comments have been tweaked to more closely follow
802.3's naming.

Signed-off-by: Sean Anderson <[email protected]>
---

Changes in v4:
- New

include/uapi/linux/mdio.h | 102 ++++++++++++++++++++++++--------------
1 file changed, 64 insertions(+), 38 deletions(-)

diff --git a/include/uapi/linux/mdio.h b/include/uapi/linux/mdio.h
index 75b7257a51e1..14b779a8577b 100644
--- a/include/uapi/linux/mdio.h
+++ b/include/uapi/linux/mdio.h
@@ -37,40 +37,47 @@
#define MDIO_DEVS2 6
#define MDIO_CTRL2 7 /* 10G control 2 */
#define MDIO_STAT2 8 /* 10G status 2 */
+#define MDIO_PKGID1 14 /* Package identifier */
+#define MDIO_PKGID2 15
+
+/* PMA/PMD registers. */
#define MDIO_PMA_TXDIS 9 /* 10G PMA/PMD transmit disable */
#define MDIO_PMA_RXDET 10 /* 10G PMA/PMD receive signal detect */
#define MDIO_PMA_EXTABLE 11 /* 10G PMA/PMD extended ability */
-#define MDIO_PKGID1 14 /* Package identifier */
-#define MDIO_PKGID2 15
-#define MDIO_AN_ADVERTISE 16 /* AN advertising (base page) */
-#define MDIO_AN_LPA 19 /* AN LP abilities (base page) */
-#define MDIO_PCS_EEE_ABLE 20 /* EEE Capability register */
-#define MDIO_PCS_EEE_ABLE2 21 /* EEE Capability register 2 */
+#define MDIO_PMA_PMD_BT1 18 /* BASE-T1 PMA/PMD extended ability */
#define MDIO_PMA_NG_EXTABLE 21 /* 2.5G/5G PMA/PMD extended ability */
-#define MDIO_PCS_EEE_WK_ERR 22 /* EEE wake error counter */
-#define MDIO_PHYXS_LNSTAT 24 /* PHY XGXS lane state */
-#define MDIO_AN_EEE_ADV 60 /* EEE advertisement */
-#define MDIO_AN_EEE_LPABLE 61 /* EEE link partner ability */
-#define MDIO_AN_EEE_ADV2 62 /* EEE advertisement 2 */
-#define MDIO_AN_EEE_LPABLE2 63 /* EEE link partner ability 2 */
-#define MDIO_AN_CTRL2 64 /* AN THP bypass request control */
-
-/* Media-dependent registers. */
#define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
#define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */
#define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A.
* Lanes B-D are numbered 134-136. */
#define MDIO_PMA_10GBR_FSRT_CSR 147 /* 10GBASE-R fast retrain status and control */
#define MDIO_PMA_10GBR_FECABLE 170 /* 10GBASE-R FEC ability */
+#define MDIO_PMA_PMD_BT1_CTRL 2100 /* BASE-T1 PMA/PMD control register */
+#define MDIO_B10L_PMA_CTRL 2294 /* 10BASE-T1L PMA control */
+#define MDIO_PMA_10T1L_STAT 2295 /* 10BASE-T1L PMA status */
+
+/* PCS registers */
+#define MDIO_PCS_EEE_ABLE 20 /* EEE Capability register */
+#define MDIO_PCS_EEE_ABLE2 21 /* EEE Capability register 2 */
+#define MDIO_PCS_EEE_WK_ERR 22 /* EEE wake error counter */
#define MDIO_PCS_10GBX_STAT1 24 /* 10GBASE-X PCS status 1 */
#define MDIO_PCS_10GBRT_STAT1 32 /* 10GBASE-R/-T PCS status 1 */
#define MDIO_PCS_10GBRT_STAT2 33 /* 10GBASE-R/-T PCS status 2 */
+#define MDIO_PCS_10T1L_CTRL 2278 /* 10BASE-T1L PCS control */
+
+/* PHY XS registers */
+#define MDIO_PHYXS_LNSTAT 24 /* PHY XGXS lane state */
+
+/* Auto_negotiation registers */
+#define MDIO_AN_ADVERTISE 16 /* AN advertising (base page) */
+#define MDIO_AN_LPA 19 /* AN LP abilities (base page) */
#define MDIO_AN_10GBT_CTRL 32 /* 10GBASE-T auto-negotiation control */
#define MDIO_AN_10GBT_STAT 33 /* 10GBASE-T auto-negotiation status */
-#define MDIO_B10L_PMA_CTRL 2294 /* 10BASE-T1L PMA control */
-#define MDIO_PMA_10T1L_STAT 2295 /* 10BASE-T1L PMA status */
-#define MDIO_PCS_10T1L_CTRL 2278 /* 10BASE-T1L PCS control */
-#define MDIO_PMA_PMD_BT1 18 /* BASE-T1 PMA/PMD extended ability */
+#define MDIO_AN_EEE_ADV 60 /* EEE advertisement */
+#define MDIO_AN_EEE_LPABLE 61 /* EEE link partner ability */
+#define MDIO_AN_EEE_ADV2 62 /* EEE advertisement 2 */
+#define MDIO_AN_EEE_LPABLE2 63 /* EEE link partner ability 2 */
+#define MDIO_AN_CTRL2 64 /* AN THP bypass request control */
#define MDIO_AN_T1_CTRL 512 /* BASE-T1 AN control */
#define MDIO_AN_T1_STAT 513 /* BASE-T1 AN status */
#define MDIO_AN_T1_ADV_L 514 /* BASE-T1 AN advertisement register [15:0] */
@@ -79,7 +86,6 @@
#define MDIO_AN_T1_LP_L 517 /* BASE-T1 AN LP Base Page ability register [15:0] */
#define MDIO_AN_T1_LP_M 518 /* BASE-T1 AN LP Base Page ability register [31:16] */
#define MDIO_AN_T1_LP_H 519 /* BASE-T1 AN LP Base Page ability register [47:32] */
-#define MDIO_PMA_PMD_BT1_CTRL 2100 /* BASE-T1 PMA/PMD control register */

/* LASI (Link Alarm Status Interrupt) registers, defined by XENPAK MSA. */
#define MDIO_PMA_LASI_RXCTRL 0x9000 /* RX_ALARM control */
@@ -89,7 +95,7 @@
#define MDIO_PMA_LASI_TXSTAT 0x9004 /* TX_ALARM status */
#define MDIO_PMA_LASI_STAT 0x9005 /* LASI status */

-/* Control register 1. */
+/* Generic control 1 register. */
/* Enable extended speed selection */
#define MDIO_CTRL1_SPEEDSELEXT (BMCR_SPEED1000 | BMCR_SPEED100)
/* All speed selection bits */
@@ -97,15 +103,6 @@
#define MDIO_CTRL1_FULLDPLX BMCR_FULLDPLX
#define MDIO_CTRL1_LPOWER BMCR_PDOWN
#define MDIO_CTRL1_RESET BMCR_RESET
-#define MDIO_PMA_CTRL1_LOOPBACK 0x0001
-#define MDIO_PMA_CTRL1_SPEED1000 BMCR_SPEED1000
-#define MDIO_PMA_CTRL1_SPEED100 BMCR_SPEED100
-#define MDIO_PCS_CTRL1_LOOPBACK BMCR_LOOPBACK
-#define MDIO_PHYXS_CTRL1_LOOPBACK BMCR_LOOPBACK
-#define MDIO_AN_CTRL1_RESTART BMCR_ANRESTART
-#define MDIO_AN_CTRL1_ENABLE BMCR_ANENABLE
-#define MDIO_AN_CTRL1_XNP 0x2000 /* Enable extended next page */
-#define MDIO_PCS_CTRL1_CLKSTOP_EN 0x400 /* Stop the clock during LPI */

/* 10 Gb/s */
#define MDIO_CTRL1_SPEED10G (MDIO_CTRL1_SPEEDSELEXT | 0x00)
@@ -116,10 +113,29 @@
/* 5 Gb/s */
#define MDIO_CTRL1_SPEED5G (MDIO_CTRL1_SPEEDSELEXT | 0x1c)

-/* Status register 1. */
+/* PMA/PMD control 1 register. */
+#define MDIO_PMA_CTRL1_LOOPBACK 0x0001
+#define MDIO_PMA_CTRL1_SPEED1000 BMCR_SPEED1000
+#define MDIO_PMA_CTRL1_SPEED100 BMCR_SPEED100
+
+/* PCS control 1 register. */
+#define MDIO_PCS_CTRL1_LOOPBACK BMCR_LOOPBACK
+#define MDIO_PCS_CTRL1_CLKSTOP_EN 0x400 /* Stop the clock during LPI */
+
+/* PHY XS control 1 register. */
+#define MDIO_PHYXS_CTRL1_LOOPBACK BMCR_LOOPBACK
+
+/* AN control register. */
+#define MDIO_AN_CTRL1_RESTART BMCR_ANRESTART
+#define MDIO_AN_CTRL1_ENABLE BMCR_ANENABLE
+#define MDIO_AN_CTRL1_XNP 0x2000 /* Enable extended next page */
+
+/* Generic status 1 register. */
#define MDIO_STAT1_LPOWERABLE 0x0002 /* Low-power ability */
#define MDIO_STAT1_LSTATUS BMSR_LSTATUS
#define MDIO_STAT1_FAULT 0x0080 /* Fault */
+
+/* AN status register. */
#define MDIO_AN_STAT1_LPABLE 0x0001 /* Link partner AN ability */
#define MDIO_AN_STAT1_ABLE BMSR_ANEGCAPABLE
#define MDIO_AN_STAT1_RFAULT BMSR_RFAULT
@@ -127,13 +143,17 @@
#define MDIO_AN_STAT1_PAGE 0x0040 /* Page received */
#define MDIO_AN_STAT1_XNP 0x0080 /* Extended next page status */

-/* Speed register. */
+/* Generic Speed register. */
#define MDIO_SPEED_10G 0x0001 /* 10G capable */
+
+/* PMA/PMD Speed register. */
#define MDIO_PMA_SPEED_2B 0x0002 /* 2BASE-TL capable */
#define MDIO_PMA_SPEED_10P 0x0004 /* 10PASS-TS capable */
#define MDIO_PMA_SPEED_1000 0x0010 /* 1000M capable */
#define MDIO_PMA_SPEED_100 0x0020 /* 100M capable */
#define MDIO_PMA_SPEED_10 0x0040 /* 10M capable */
+
+/* PCS et al. Speed register. */
#define MDIO_PCS_SPEED_10P2B 0x0002 /* 10PASS-TS/2BASE-TL capable */
#define MDIO_PCS_SPEED_2_5G 0x0040 /* 2.5G capable */
#define MDIO_PCS_SPEED_5G 0x0080 /* 5G capable */
@@ -152,7 +172,7 @@
#define MDIO_DEVS_VEND1 MDIO_DEVS_PRESENT(MDIO_MMD_VEND1)
#define MDIO_DEVS_VEND2 MDIO_DEVS_PRESENT(MDIO_MMD_VEND2)

-/* Control register 2. */
+/* PMA/PMD control 2 register. */
#define MDIO_PMA_CTRL2_TYPE 0x000f /* PMA/PMD type selection */
#define MDIO_PMA_CTRL2_10GBCX4 0x0000 /* 10GBASE-CX4 type */
#define MDIO_PMA_CTRL2_10GBEW 0x0001 /* 10GBASE-EW type */
@@ -173,17 +193,21 @@
#define MDIO_PMA_CTRL2_2_5GBT 0x0030 /* 2.5GBaseT type */
#define MDIO_PMA_CTRL2_5GBT 0x0031 /* 5GBaseT type */
#define MDIO_PMA_CTRL2_BASET1 0x003D /* BASE-T1 type */
+
+/* PCS control 2 register. */
#define MDIO_PCS_CTRL2_TYPE 0x0003 /* PCS type selection */
#define MDIO_PCS_CTRL2_10GBR 0x0000 /* 10GBASE-R type */
#define MDIO_PCS_CTRL2_10GBX 0x0001 /* 10GBASE-X type */
#define MDIO_PCS_CTRL2_10GBW 0x0002 /* 10GBASE-W type */
#define MDIO_PCS_CTRL2_10GBT 0x0003 /* 10GBASE-T type */

-/* Status register 2. */
+/* Generic status 2 register. */
#define MDIO_STAT2_RXFAULT 0x0400 /* Receive fault */
#define MDIO_STAT2_TXFAULT 0x0800 /* Transmit fault */
#define MDIO_STAT2_DEVPRST 0xc000 /* Device present */
#define MDIO_STAT2_DEVPRST_VAL 0x8000 /* Device present value */
+
+/* PMA/PMD status 2 register */
#define MDIO_PMA_STAT2_LBABLE 0x0001 /* PMA loopback ability */
#define MDIO_PMA_STAT2_10GBEW 0x0002 /* 10GBASE-EW ability */
#define MDIO_PMA_STAT2_10GBLW 0x0004 /* 10GBASE-LW ability */
@@ -196,27 +220,29 @@
#define MDIO_PMA_STAT2_EXTABLE 0x0200 /* Extended abilities */
#define MDIO_PMA_STAT2_RXFLTABLE 0x1000 /* Receive fault ability */
#define MDIO_PMA_STAT2_TXFLTABLE 0x2000 /* Transmit fault ability */
+
+/* PCS status 2 register */
#define MDIO_PCS_STAT2_10GBR 0x0001 /* 10GBASE-R capable */
#define MDIO_PCS_STAT2_10GBX 0x0002 /* 10GBASE-X capable */
#define MDIO_PCS_STAT2_10GBW 0x0004 /* 10GBASE-W capable */
#define MDIO_PCS_STAT2_RXFLTABLE 0x1000 /* Receive fault ability */
#define MDIO_PCS_STAT2_TXFLTABLE 0x2000 /* Transmit fault ability */

-/* Transmit disable register. */
+/* PMD Transmit disable register. */
#define MDIO_PMD_TXDIS_GLOBAL 0x0001 /* Global PMD TX disable */
#define MDIO_PMD_TXDIS_0 0x0002 /* PMD TX disable 0 */
#define MDIO_PMD_TXDIS_1 0x0004 /* PMD TX disable 1 */
#define MDIO_PMD_TXDIS_2 0x0008 /* PMD TX disable 2 */
#define MDIO_PMD_TXDIS_3 0x0010 /* PMD TX disable 3 */

-/* Receive signal detect register. */
+/* PMD receive signal detect register. */
#define MDIO_PMD_RXDET_GLOBAL 0x0001 /* Global PMD RX signal detect */
#define MDIO_PMD_RXDET_0 0x0002 /* PMD RX signal detect 0 */
#define MDIO_PMD_RXDET_1 0x0004 /* PMD RX signal detect 1 */
#define MDIO_PMD_RXDET_2 0x0008 /* PMD RX signal detect 2 */
#define MDIO_PMD_RXDET_3 0x0010 /* PMD RX signal detect 3 */

-/* Extended abilities register. */
+/* PMA/PMD extended ability register. */
#define MDIO_PMA_EXTABLE_10GCX4 0x0001 /* 10GBASE-CX4 ability */
#define MDIO_PMA_EXTABLE_10GBLRM 0x0002 /* 10GBASE-LRM ability */
#define MDIO_PMA_EXTABLE_10GBT 0x0004 /* 10GBASE-T ability */
@@ -229,7 +255,7 @@
#define MDIO_PMA_EXTABLE_BT1 0x0800 /* BASE-T1 ability */
#define MDIO_PMA_EXTABLE_NBT 0x4000 /* 2.5/5GBASE-T ability */

-/* PHY XGXS lane state register. */
+/* 10G PHY XGXS lane status register. */
#define MDIO_PHYXS_LNSTAT_SYNC0 0x0001
#define MDIO_PHYXS_LNSTAT_SYNC1 0x0002
#define MDIO_PHYXS_LNSTAT_SYNC2 0x0004
--
2.35.1.1320.gc452695387.dirty

2022-12-16 17:44:26

by Russell King (Oracle)

[permalink] [raw]

Subject: Re: [PATCH net-next v4 0/4] phy: aquantia: Determine rate adaptation support from registers

Hi Sean,

Please note net-next is currently closed due to the merge window, so
please don't send patches for it. However, feel free to send RFC
patches for net-next so that reviews can still happen.

Thanks!

On Fri, Dec 16, 2022 at 11:48:47AM -0500, Sean Anderson wrote:
> This attempts to address the problems first reported in [1]. Tim has an
> Aquantia phy where the firmware is set up to use "5G XFI" (underclocked
> 10GBASE-R) when rate adapting lower speeds. This results in us
> advertising that we support lower speeds and then failing to bring the
> link up. To avoid this, determine whether to enable rate adaptation
> based on what's programmed by the firmware. This is "the worst choice"
> [2], but we can't really do better until we have more insight into
> what the firmware is doing. At the very least, we can prevent bad
> firmware from causing us to advertise the wrong modes.
>
> Past submissions may be found at [3, 4].
>
> [1] https://lore.kernel.org/netdev/CAJ+vNU3zeNqiGhjTKE8jRjDYR0D7f=iqPLB8phNyA2CWixy7JA@mail.gmail.com/
> [2] https://lore.kernel.org/netdev/20221118171643.vu6uxbnmog4sna65@skbuf/
> [3] https://lore.kernel.org/netdev/[email protected]/
> [4] https://lore.kernel.org/netdev/[email protected]/
>
> Changes in v4:
> - Reorganize MDIO defines
> - Fix kerneldoc using - instead of : for parameters
>
> Changes in v3:
> - Update speed register bits
> - Fix incorrect bits for PMA/PMD speed
>
> Changes in v2:
> - Move/rename phylink_interface_max_speed
> - Rework to just validate things instead of modifying registers
>
> Sean Anderson (4):
> net: phy: Move/rename phylink_interface_max_speed
> phy: mdio: Reorganize defines
> net: mdio: Update speed register bits
> phy: aquantia: Determine rate adaptation support from registers
>
> drivers/net/phy/aquantia_main.c | 160 ++++++++++++++++++++++++++++++--
> drivers/net/phy/phy-core.c | 70 ++++++++++++++
> drivers/net/phy/phylink.c | 75 +--------------
> include/linux/phy.h | 1 +
> include/uapi/linux/mdio.h | 109 ++++++++++++++--------
> 5 files changed, 299 insertions(+), 116 deletions(-)
>
> --
> 2.35.1.1320.gc452695387.dirty
>
>

--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!

2022-12-16 18:13:59

by Sean Anderson

[permalink] [raw]

Subject: [PATCH net-next v4 4/4] phy: aquantia: Determine rate adaptation support from registers

When autonegotiation completes, the phy interface will be set based on
the global config register for that speed. If the SERDES mode is set to
something which the MAC does not support, then the link will not come
up. To avoid this, validate each combination of interface speed and link
speed which might be configured. This way, we ensure that we only
consider rate adaptation in our advertisement when we can actually use
it.

The API for get_rate_matching requires that PHY_INTERFACE_MODE_NA be
handled properly. To do this, we adopt a structure similar to
phylink_validate. At the top-level, we either validate a particular
interface speed or all of them. Below that, we validate each combination
of serdes speed and link speed.

For some firmwares, not all speeds are supported. In this case, the
global config register for that speed will be initialized to zero
(indicating that rate adaptation is not supported). We can detect this
by reading the PMA/PMD speed register to determine which speeds are
supported. This register is read once in probe and cached for later.

Signed-off-by: Sean Anderson <[email protected]>
---
This commit fixes 3c42563b3041 ("net: phy: aquantia: Add support for
rate matching"). In an effort to avoid backporting of this commit until
it has soaked in master for a while, the fixes tag has been left off.

Changes in v4:
- Fix kerneldoc using - instead of : for parameters

Changes in v3:
- Fix incorrect bits for PMA/PMD speed

Changes in v2:
- Rework to just validate things instead of modifying registers

drivers/net/phy/aquantia_main.c | 160 ++++++++++++++++++++++++++++++--
1 file changed, 154 insertions(+), 6 deletions(-)

diff --git a/drivers/net/phy/aquantia_main.c b/drivers/net/phy/aquantia_main.c
index 334a6904ca5a..e942b99be823 100644
--- a/drivers/net/phy/aquantia_main.c
+++ b/drivers/net/phy/aquantia_main.c
@@ -111,6 +111,12 @@
#define VEND1_GLOBAL_CFG_RATE_ADAPT_NONE 0
#define VEND1_GLOBAL_CFG_RATE_ADAPT_USX 1
#define VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE 2
+#define VEND1_GLOBAL_CFG_SERDES_MODE GENMASK(2, 0)
+#define VEND1_GLOBAL_CFG_SERDES_MODE_XFI 0
+#define VEND1_GLOBAL_CFG_SERDES_MODE_SGMII 3
+#define VEND1_GLOBAL_CFG_SERDES_MODE_OCSGMII 4
+#define VEND1_GLOBAL_CFG_SERDES_MODE_XFI5G 6
+#define VEND1_GLOBAL_CFG_SERDES_MODE_XFI20G 7

#define VEND1_GLOBAL_RSVD_STAT1 0xc885
#define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID GENMASK(7, 4)
@@ -175,6 +181,7 @@ static const struct aqr107_hw_stat aqr107_hw_stats[] = {

struct aqr107_priv {
u64 sgmii_stats[AQR107_SGMII_STAT_SZ];
+ int pmapmd_speeds;
};

static int aqr107_get_sset_count(struct phy_device *phydev)
@@ -677,13 +684,146 @@ static int aqr107_wait_processor_intensive_op(struct phy_device *phydev)
return 0;
}

+/**
+ * struct aqr107_link_speed_cfg - Common configuration for link speeds
+ * @speed: The speed of this config
+ * @reg: The global system configuration register for this speed
+ * @speed_bit: The bit in the PMA/PMD speed ability register which determines
+ * whether this link speed is supported
+ */
+struct aqr107_link_speed_cfg {
+ int speed;
+ u16 reg, speed_bit;
+};
+
+/**
+ * aqr107_rate_adapt_ok_one() - Validate rate adaptation for one configuration
+ * @phydev: The phy to act on
+ * @serdes_speed: The speed of the serdes (aka the phy interface)
+ * @link_cfg: The config for the link speed
+ *
+ * This function validates whether rate adaptation will work for a particular
+ * combination of @serdes_speed and @link_cfg.
+ *
+ * Return: %true if the @link_cfg.reg is configured for rate adaptation, %true
+ * if @link_cfg.speed will not be advertised, %false otherwise.
+ */
+static bool aqr107_rate_adapt_ok_one(struct phy_device *phydev, int serdes_speed,
+ const struct aqr107_link_speed_cfg *link_cfg)
+{
+ struct aqr107_priv *priv = phydev->priv;
+ int val;
+
+ phydev_dbg(phydev, "validating link_speed=%d serdes_speed=%d\n",
+ link_cfg->speed, serdes_speed);
+
+ /* Vacuously OK, since we won't advertise it anyway */
+ if (!(priv->pmapmd_speeds & link_cfg->speed_bit))
+ return true;
+
+ val = phy_read_mmd(phydev, MDIO_MMD_VEND1, link_cfg->reg);
+ if (val < 0) {
+ phydev_warn(phydev, "could not read register %x:%.04x (err = %d)\n",
+ MDIO_MMD_VEND1, link_cfg->reg, val);
+ return false;
+ }
+
+ phydev_dbg(phydev, "%x:%.04x = %.04x\n", MDIO_MMD_VEND1, link_cfg->reg, val);
+ if (FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val) !=
+ VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE)
+ return false;
+
+ switch (FIELD_GET(VEND1_GLOBAL_CFG_SERDES_MODE, val)) {
+ case VEND1_GLOBAL_CFG_SERDES_MODE_XFI20G:
+ return serdes_speed == SPEED_20000;
+ case VEND1_GLOBAL_CFG_SERDES_MODE_XFI:
+ return serdes_speed == SPEED_10000;
+ case VEND1_GLOBAL_CFG_SERDES_MODE_XFI5G:
+ return serdes_speed == SPEED_5000;
+ case VEND1_GLOBAL_CFG_SERDES_MODE_OCSGMII:
+ return serdes_speed == SPEED_2500;
+ case VEND1_GLOBAL_CFG_SERDES_MODE_SGMII:
+ return serdes_speed == SPEED_1000;
+ default:
+ return false;
+ }
+}
+
+/**
+ * aqr107_rate_adapt_ok() - Validate rate adaptation for an interface speed
+ * @phydev: The phy device
+ * @speed: The serdes (phy interface) speed
+ *
+ * This validates whether rate adaptation will work for a particular @speed.
+ * All link speeds less than or equal to @speed are validate to ensure they are
+ * configured properly.
+ *
+ * Return: %true if rate adaptation is supported for @speed, %false otherwise.
+ */
+static bool aqr107_rate_adapt_ok(struct phy_device *phydev, int speed)
+{
+ static const struct aqr107_link_speed_cfg speed_table[] = {
+ {
+ .speed = SPEED_10,
+ .reg = VEND1_GLOBAL_CFG_10M,
+ .speed_bit = MDIO_PMA_SPEED_10,
+ },
+ {
+ .speed = SPEED_100,
+ .reg = VEND1_GLOBAL_CFG_100M,
+ .speed_bit = MDIO_PMA_SPEED_100,
+ },
+ {
+ .speed = SPEED_1000,
+ .reg = VEND1_GLOBAL_CFG_1G,
+ .speed_bit = MDIO_PMA_SPEED_1000,
+ },
+ {
+ .speed = SPEED_2500,
+ .reg = VEND1_GLOBAL_CFG_2_5G,
+ .speed_bit = MDIO_PMA_SPEED_2_5G,
+ },
+ {
+ .speed = SPEED_5000,
+ .reg = VEND1_GLOBAL_CFG_5G,
+ .speed_bit = MDIO_PMA_SPEED_5G,
+ },
+ {
+ .speed = SPEED_10000,
+ .reg = VEND1_GLOBAL_CFG_10G,
+ .speed_bit = MDIO_PMA_SPEED_10G,
+ },
+ };
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(speed_table) &&
+ speed_table[i].speed <= speed; i++)
+ if (!aqr107_rate_adapt_ok_one(phydev, speed, &speed_table[i]))
+ return false;
+
+ /* Must match at least one speed */
+ if (i == ARRAY_SIZE(speed_table) && speed != speed_table[i].speed)
+ return false;
+
+ return true;
+}
+
static int aqr107_get_rate_matching(struct phy_device *phydev,
phy_interface_t iface)
{
- if (iface == PHY_INTERFACE_MODE_10GBASER ||
- iface == PHY_INTERFACE_MODE_2500BASEX ||
- iface == PHY_INTERFACE_MODE_NA)
+ if (iface != PHY_INTERFACE_MODE_NA) {
+ if (aqr107_rate_adapt_ok(phydev,
+ phy_interface_max_speed(iface)))
+ return RATE_MATCH_PAUSE;
+ else
+ return RATE_MATCH_NONE;
+ }
+
+ if (aqr107_rate_adapt_ok(phydev, SPEED_10000) ||
+ aqr107_rate_adapt_ok(phydev, SPEED_2500) ||
+ aqr107_rate_adapt_ok(phydev, SPEED_1000))
return RATE_MATCH_PAUSE;
+
return RATE_MATCH_NONE;
}

@@ -713,10 +853,18 @@ static int aqr107_resume(struct phy_device *phydev)

static int aqr107_probe(struct phy_device *phydev)
{
- phydev->priv = devm_kzalloc(&phydev->mdio.dev,
- sizeof(struct aqr107_priv), GFP_KERNEL);
- if (!phydev->priv)
+ struct aqr107_priv *priv;
+
+ priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
return -ENOMEM;
+ phydev->priv = priv;
+
+ priv->pmapmd_speeds = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_SPEED);
+ if (priv->pmapmd_speeds < 0) {
+ phydev_err(phydev, "could not read PMA/PMD speeds\n");
+ return priv->pmapmd_speeds;
+ };

return aqr_hwmon_probe(phydev);
}
--
2.35.1.1320.gc452695387.dirty

2022-12-16 19:07:41

by kernel test robot

[permalink] [raw]

Subject: Re: [PATCH net-next v4 4/4] phy: aquantia: Determine rate adaptation support from registers

Attachments:

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config (283.51 kB)
Download all attachments

2022-12-16 19:50:14

by kernel test robot

[permalink] [raw]

Subject: Re: [PATCH net-next v4 4/4] phy: aquantia: Determine rate adaptation support from registers

Hi Sean,

I love your patch! Yet something to improve:

[auto build test ERROR on net-next/master]

url: https://github.com/intel-lab-lkp/linux/commits/Sean-Anderson/phy-aquantia-Determine-rate-adaptation-support-from-registers/20221217-005201
patch link: https://lore.kernel.org/r/20221216164851.2932043-5-sean.anderson%40seco.com
patch subject: [PATCH net-next v4 4/4] phy: aquantia: Determine rate adaptation support from registers
config: hexagon-randconfig-r041-20221216
compiler: clang version 16.0.0 (https://github.com/llvm/llvm-project 98b13979fb05f3ed288a900deb843e7b27589e58)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/d13e19ac57e06d0b5d6ddb81c27801c0b8ec9b70
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Sean-Anderson/phy-aquantia-Determine-rate-adaptation-support-from-registers/20221217-005201
git checkout d13e19ac57e06d0b5d6ddb81c27801c0b8ec9b70
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=hexagon olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=hexagon SHELL=/bin/bash drivers/net/phy/

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <[email protected]>

All errors (new ones prefixed by >>):

In file included from drivers/net/phy/aquantia_main.c:14:
In file included from include/linux/phy.h:16:
In file included from include/linux/ethtool.h:18:
In file included from include/linux/netlink.h:7:
In file included from include/linux/skbuff.h:17:
In file included from include/linux/bvec.h:10:
In file included from include/linux/highmem.h:12:
In file included from include/linux/hardirq.h:11:
In file included from ./arch/hexagon/include/generated/asm/hardirq.h:1:
In file included from include/asm-generic/hardirq.h:17:
In file included from include/linux/irq.h:20:
In file included from include/linux/io.h:13:
In file included from arch/hexagon/include/asm/io.h:334:
include/asm-generic/io.h:547:31: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
val = __raw_readb(PCI_IOBASE + addr);
~~~~~~~~~~ ^
include/asm-generic/io.h:560:61: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
val = __le16_to_cpu((__le16 __force)__raw_readw(PCI_IOBASE + addr));
~~~~~~~~~~ ^
include/uapi/linux/byteorder/little_endian.h:37:51: note: expanded from macro '__le16_to_cpu'
#define __le16_to_cpu(x) ((__force __u16)(__le16)(x))
^
In file included from drivers/net/phy/aquantia_main.c:14:
In file included from include/linux/phy.h:16:
In file included from include/linux/ethtool.h:18:
In file included from include/linux/netlink.h:7:
In file included from include/linux/skbuff.h:17:
In file included from include/linux/bvec.h:10:
In file included from include/linux/highmem.h:12:
In file included from include/linux/hardirq.h:11:
In file included from ./arch/hexagon/include/generated/asm/hardirq.h:1:
In file included from include/asm-generic/hardirq.h:17:
In file included from include/linux/irq.h:20:
In file included from include/linux/io.h:13:
In file included from arch/hexagon/include/asm/io.h:334:
include/asm-generic/io.h:573:61: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
val = __le32_to_cpu((__le32 __force)__raw_readl(PCI_IOBASE + addr));
~~~~~~~~~~ ^
include/uapi/linux/byteorder/little_endian.h:35:51: note: expanded from macro '__le32_to_cpu'
#define __le32_to_cpu(x) ((__force __u32)(__le32)(x))
^
In file included from drivers/net/phy/aquantia_main.c:14:
In file included from include/linux/phy.h:16:
In file included from include/linux/ethtool.h:18:
In file included from include/linux/netlink.h:7:
In file included from include/linux/skbuff.h:17:
In file included from include/linux/bvec.h:10:
In file included from include/linux/highmem.h:12:
In file included from include/linux/hardirq.h:11:
In file included from ./arch/hexagon/include/generated/asm/hardirq.h:1:
In file included from include/asm-generic/hardirq.h:17:
In file included from include/linux/irq.h:20:
In file included from include/linux/io.h:13:
In file included from arch/hexagon/include/asm/io.h:334:
include/asm-generic/io.h:584:33: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
__raw_writeb(value, PCI_IOBASE + addr);
~~~~~~~~~~ ^
include/asm-generic/io.h:594:59: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
__raw_writew((u16 __force)cpu_to_le16(value), PCI_IOBASE + addr);
~~~~~~~~~~ ^
include/asm-generic/io.h:604:59: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
__raw_writel((u32 __force)cpu_to_le32(value), PCI_IOBASE + addr);
~~~~~~~~~~ ^
>> drivers/net/phy/aquantia_main.c:784:17: error: use of undeclared identifier 'MDIO_PMA_SPEED_2_5G'
.speed_bit = MDIO_PMA_SPEED_2_5G,
^
>> drivers/net/phy/aquantia_main.c:789:17: error: use of undeclared identifier 'MDIO_PMA_SPEED_5G'
.speed_bit = MDIO_PMA_SPEED_5G,
^
>> drivers/net/phy/aquantia_main.c:799:18: error: invalid application of 'sizeof' to an incomplete type 'const struct aqr107_link_speed_cfg[]'
for (i = 0; i < ARRAY_SIZE(speed_table) &&
^~~~~~~~~~~~~~~~~~~~~~~
include/linux/kernel.h:55:32: note: expanded from macro 'ARRAY_SIZE'
#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]) + __must_be_array(arr))
^~~~~
drivers/net/phy/aquantia_main.c:805:11: error: invalid application of 'sizeof' to an incomplete type 'const struct aqr107_link_speed_cfg[]'
if (i == ARRAY_SIZE(speed_table) && speed != speed_table[i].speed)
^~~~~~~~~~~~~~~~~~~~~~~
include/linux/kernel.h:55:32: note: expanded from macro 'ARRAY_SIZE'
#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]) + __must_be_array(arr))
^~~~~
6 warnings and 4 errors generated.

Kconfig warnings: (for reference only)
WARNING: unmet direct dependencies detected for DEBUG_MAPLE_TREE
Depends on [n]: DEBUG_KERNEL [=n]
Selected by [y]:
- TEST_MAPLE_TREE [=y] && RUNTIME_TESTING_MENU [=y]

vim +/MDIO_PMA_SPEED_2_5G +784 drivers/net/phy/aquantia_main.c

751
752 /**
753 * aqr107_rate_adapt_ok() - Validate rate adaptation for an interface speed
754 * @phydev: The phy device
755 * @speed: The serdes (phy interface) speed
756 *
757 * This validates whether rate adaptation will work for a particular @speed.
758 * All link speeds less than or equal to @speed are validate to ensure they are
759 * configured properly.
760 *
761 * Return: %true if rate adaptation is supported for @speed, %false otherwise.
762 */
763 static bool aqr107_rate_adapt_ok(struct phy_device *phydev, int speed)
764 {
765 static const struct aqr107_link_speed_cfg speed_table[] = {
766 {
767 .speed = SPEED_10,
768 .reg = VEND1_GLOBAL_CFG_10M,
769 .speed_bit = MDIO_PMA_SPEED_10,
770 },
771 {
772 .speed = SPEED_100,
773 .reg = VEND1_GLOBAL_CFG_100M,
774 .speed_bit = MDIO_PMA_SPEED_100,
775 },
776 {
777 .speed = SPEED_1000,
778 .reg = VEND1_GLOBAL_CFG_1G,
779 .speed_bit = MDIO_PMA_SPEED_1000,
780 },
781 {
782 .speed = SPEED_2500,
783 .reg = VEND1_GLOBAL_CFG_2_5G,
> 784 .speed_bit = MDIO_PMA_SPEED_2_5G,
785 },
786 {
787 .speed = SPEED_5000,
788 .reg = VEND1_GLOBAL_CFG_5G,
> 789 .speed_bit = MDIO_PMA_SPEED_5G,
790 },
791 {
792 .speed = SPEED_10000,
793 .reg = VEND1_GLOBAL_CFG_10G,
794 .speed_bit = MDIO_PMA_SPEED_10G,
795 },
796 };
797 int i;
798
> 799 for (i = 0; i < ARRAY_SIZE(speed_table) &&
800 speed_table[i].speed <= speed; i++)
801 if (!aqr107_rate_adapt_ok_one(phydev, speed, &speed_table[i]))
802 return false;
803
804 /* Must match at least one speed */
805 if (i == ARRAY_SIZE(speed_table) && speed != speed_table[i].speed)
806 return false;
807
808 return true;
809 }
810

--
0-DAY CI Kernel Test Service
https://01.org/lkp

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