Hi all,
The support for configuring CLK_SET_RATE_PARENT flag for a few specific
clocks was only used by the legacy Allwinner A10 sunxi clock, and the
reason its compatible was dropped was that the code supporting the
legacy sunxi platforms was removed (as the below-mentioned patch set
highlights) and no other fixed factor clock needed to do the same.
https://lore.kernel.org/lkml/[email protected]/T/
The current patch series adds "ti,k3-am62-oldi-clk-div" (TI's display
subsystem (DSS) clock for the 1st videoport (vp0) on the AM625 SoC) as
a fixed factor clock and further, it also re-introduces the same support
to set the CLK_SET_RATE_PARENT flag.
Based on the clock-set request from DSS (equivalent to pixel frequency),
this clock asks its parent for a serial clock (with 7 times the pixel
frequrncy), which is required for the generation of serial LVDS signals.
This clock thus requires the CLK_SET_RATE_PARENT flag to be set, in
order to propagate the set clock-rate request to its parent clock.
Aradhya Bhatia (2):
dt-bindings: clock: fixed-factor: Add TI AM62 SoC OLDI clock
clk: fixed-factor: Re-introduce support for clocks to set parent
clock-rate
.../devicetree/bindings/clock/fixed-factor-clock.yaml | 1 +
drivers/clk/clk-fixed-factor.c | 11 ++++++++++-
2 files changed, 11 insertions(+), 1 deletion(-)
--
2.39.0
Add support for the clock "ti,k3-am62-oldi-clk-div".
Also add support for this clock to propagate the clock set request to
its parent clock, by setting the CLK_SET_RATE_PARENT flag.
Signed-off-by: Aradhya Bhatia <[email protected]>
---
drivers/clk/clk-fixed-factor.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
index f734e34735a9..1a78e2d870dd 100644
--- a/drivers/clk/clk-fixed-factor.c
+++ b/drivers/clk/clk-fixed-factor.c
@@ -245,10 +245,16 @@ struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev,
EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor);
#ifdef CONFIG_OF
+static const struct of_device_id set_rate_parent_matches[] = {
+ { .compatible = "ti,k3-am62-oldi-clk-div" },
+ { /* Sentinel */ },
+};
+
static struct clk_hw *_of_fixed_factor_clk_setup(struct device_node *node)
{
struct clk_hw *hw;
const char *clk_name = node->name;
+ unsigned long flags = 0;
u32 div, mult;
int ret;
@@ -264,10 +270,13 @@ static struct clk_hw *_of_fixed_factor_clk_setup(struct device_node *node)
return ERR_PTR(-EIO);
}
+ if (of_match_node(set_rate_parent_matches, node))
+ flags |= CLK_SET_RATE_PARENT;
+
of_property_read_string(node, "clock-output-names", &clk_name);
hw = __clk_hw_register_fixed_factor(NULL, node, clk_name, NULL, NULL, 0,
- 0, mult, div, false);
+ flags, mult, div, false);
if (IS_ERR(hw)) {
/*
* Clear OF_POPULATED flag so that clock registration can be
--
2.39.0