From: Weidong Wang <[email protected]>
The Awinic AW883XX is an I2S/TDM input, high efficiency
digital Smart K audio amplifier with an integrated 10.25V
smart boost convert
Signed-off-by: Nick Li <[email protected]>
Signed-off-by: Bruce zhao <[email protected]>
Signed-off-by: Weidong Wang <[email protected]>
---
sound/soc/codecs/Kconfig | 10 +
sound/soc/codecs/Makefile | 6 +
sound/soc/codecs/aw883xx/aw883xx_data_type.h | 143 +++++++
.../soc/codecs/aw883xx/aw883xx_pid_2049_reg.h | 384 ++++++++++++++++++
4 files changed, 543 insertions(+)
create mode 100644 sound/soc/codecs/aw883xx/aw883xx_data_type.h
create mode 100644 sound/soc/codecs/aw883xx/aw883xx_pid_2049_reg.h
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index 0f9d71490075..ea1dd48c642b 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -54,6 +54,7 @@ config SND_SOC_ALL_CODECS
imply SND_SOC_ALC5623
imply SND_SOC_ALC5632
imply SND_SOC_AW8738
+ imply SND_SOC_AW883XX
imply SND_SOC_BT_SCO
imply SND_SOC_BD28623
imply SND_SOC_CQ0093VC
@@ -2167,4 +2168,13 @@ config SND_SOC_LPASS_TX_MACRO
select SND_SOC_LPASS_MACRO_COMMON
tristate "Qualcomm TX Macro in LPASS(Low Power Audio SubSystem)"
+config SND_SOC_AW883XX
+ tristate "Soc Audio for awinic aw883xx series"
+ depends on I2C
+ help
+ this option enables support for aw883xx series Smart PA.
+ The Awinic AW883XX is an I2S/TDM input, high efficiency
+ digital Smart K audio amplifier with an integrated 10V
+ smart boost convert.
+
endmenu
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index 71d3ce5867e4..afcac34e4d78 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -358,6 +358,10 @@ snd-soc-tas2780-objs := tas2780.o
# Mux
snd-soc-simple-mux-objs := simple-mux.o
+snd_soc_aw883xx-objs := aw883xx/aw883xx.o \
+ aw883xx/aw883xx_device.o \
+ aw883xx/aw883xx_bin_parse.o \
+
obj-$(CONFIG_SND_SOC_88PM860X) += snd-soc-88pm860x.o
obj-$(CONFIG_SND_SOC_AB8500_CODEC) += snd-soc-ab8500-codec.o
obj-$(CONFIG_SND_SOC_AC97_CODEC) += snd-soc-ac97.o
@@ -721,3 +725,5 @@ obj-$(CONFIG_SND_SOC_LPASS_TX_MACRO) += snd-soc-lpass-tx-macro.o
# Mux
obj-$(CONFIG_SND_SOC_SIMPLE_MUX) += snd-soc-simple-mux.o
+
+obj-$(CONFIG_SND_SOC_AW883XX) +=snd_soc_aw883xx.o
diff --git a/sound/soc/codecs/aw883xx/aw883xx_data_type.h b/sound/soc/codecs/aw883xx/aw883xx_data_type.h
new file mode 100644
index 000000000000..cf60953792f2
--- /dev/null
+++ b/sound/soc/codecs/aw883xx/aw883xx_data_type.h
@@ -0,0 +1,143 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * aw883xx.c -- ALSA SoC AW883XX codec support
+ *
+ * Copyright (c) 2022 AWINIC Technology CO., LTD
+ *
+ * Author: Bruce zhao <[email protected]>
+ */
+
+#ifndef __AW883XX_DATA_TYPE_H__
+#define __AW883XX_DATA_TYPE_H__
+
+#define PROJECT_NAME_MAX (24)
+#define CUSTOMER_NAME_MAX (16)
+#define CFG_VERSION_MAX (4)
+#define DEV_NAME_MAX (16)
+#define PROFILE_STR_MAX (32)
+
+#define ACF_FILE_ID (0xa15f908)
+
+enum aw_cfg_hdr_version {
+ AW_CFG_HDR_VER = 0x00000001,
+ AW_CFG_HDR_VER_V1 = 0x01000000,
+};
+
+enum aw_cfg_dde_type {
+ AW_DEV_NONE_TYPE_ID = 0xFFFFFFFF,
+ AW_DEV_TYPE_ID = 0x00000000,
+ AW_SKT_TYPE_ID = 0x00000001,
+ AW_DEV_DEFAULT_TYPE_ID = 0x00000002,
+};
+
+enum aw_sec_type {
+ ACF_SEC_TYPE_REG = 0,
+ ACF_SEC_TYPE_DSP,
+ ACF_SEC_TYPE_DSP_CFG,
+ ACF_SEC_TYPE_DSP_FW,
+ ACF_SEC_TYPE_HDR_REG,
+ ACF_SEC_TYPE_HDR_DSP_CFG,
+ ACF_SEC_TYPE_HDR_DSP_FW,
+ ACF_SEC_TYPE_MULTIPLE_BIN,
+ ACF_SEC_TYPE_SKT_PROJECT,
+ ACF_SEC_TYPE_DSP_PROJECT,
+ ACF_SEC_TYPE_MONITOR,
+ ACF_SEC_TYPE_MAX,
+};
+
+enum profile_data_type {
+ AW_DATA_TYPE_REG = 0,
+ AW_DATA_TYPE_DSP_CFG,
+ AW_DATA_TYPE_DSP_FW,
+ AW_DATA_TYPE_MAX,
+};
+
+enum aw_prof_type {
+ AW_PROFILE_MUSIC = 0,
+ AW_PROFILE_VOICE,
+ AW_PROFILE_VOIP,
+ AW_PROFILE_RINGTONE,
+ AW_PROFILE_RINGTONE_HS,
+ AW_PROFILE_LOWPOWER,
+ AW_PROFILE_BYPASS,
+ AW_PROFILE_MMI,
+ AW_PROFILE_FM,
+ AW_PROFILE_NOTIFICATION,
+ AW_PROFILE_RECEIVER,
+ AW_PROFILE_MAX,
+};
+
+enum aw_profile_status {
+ AW_PROFILE_WAIT = 0,
+ AW_PROFILE_OK,
+};
+
+struct aw_cfg_hdr {
+ u32 id;
+ char project[PROJECT_NAME_MAX];
+ char custom[CUSTOMER_NAME_MAX];
+ char version[CFG_VERSION_MAX];
+ u32 author_id;
+ u32 ddt_size;
+ u32 ddt_num;
+ u32 hdr_offset;
+ u32 hdr_version;
+ u32 reserved[3];
+};
+
+struct aw_cfg_dde {
+ u32 type;
+ char dev_name[DEV_NAME_MAX];
+ u16 dev_index;
+ u16 dev_bus;
+ u16 dev_addr;
+ u16 dev_profile;
+ u32 data_type;
+ u32 data_size;
+ u32 data_offset;
+ u32 data_crc;
+ u32 reserved[5];
+};
+
+struct aw_cfg_dde_v1 {
+ u32 type;
+ char dev_name[DEV_NAME_MAX];
+ u16 dev_index;
+ u16 dev_bus;
+ u16 dev_addr;
+ u16 dev_profile;
+ u32 data_type;
+ u32 data_size;
+ u32 data_offset;
+ u32 data_crc;
+ char dev_profile_str[PROFILE_STR_MAX];
+ u32 chip_id;
+ u32 reserved[4];
+};
+
+struct aw_sec_data_desc {
+ u32 len;
+ u8 *data;
+};
+
+struct aw_prof_desc {
+ u32 id;
+ u32 prof_st;
+ char *prf_str;
+ u32 fw_ver;
+ struct aw_sec_data_desc sec_desc[AW_DATA_TYPE_MAX];
+};
+
+struct aw_all_prof_info {
+ struct aw_prof_desc prof_desc[AW_PROFILE_MAX];
+};
+
+struct aw_prof_info {
+ int count;
+ int prof_type;
+ char **prof_name_list;
+ struct aw_prof_desc *prof_desc;
+};
+
+#endif
+
diff --git a/sound/soc/codecs/aw883xx/aw883xx_pid_2049_reg.h b/sound/soc/codecs/aw883xx/aw883xx_pid_2049_reg.h
new file mode 100644
index 000000000000..7305a21bf05a
--- /dev/null
+++ b/sound/soc/codecs/aw883xx/aw883xx_pid_2049_reg.h
@@ -0,0 +1,384 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * aw883xx.c -- ALSA SoC AW883XX codec support
+ *
+ * Copyright (c) 2022 AWINIC Technology CO., LTD
+ *
+ * Author: Bruce zhao <[email protected]>
+ */
+
+#ifndef __AW883XX_PID_2049_REG_H__
+#define __AW883XX_PID_2049_REG_H__
+
+#define AW_PID_2049_ID_REG (0x00)
+#define AW_PID_2049_SYSST_REG (0x01)
+#define AW_PID_2049_SYSINT_REG (0x02)
+#define AW_PID_2049_SYSINTM_REG (0x03)
+#define AW_PID_2049_SYSCTRL_REG (0x04)
+#define AW_PID_2049_SYSCTRL2_REG (0x05)
+#define AW_PID_2049_I2SCTRL_REG (0x06)
+#define AW_PID_2049_I2SCFG1_REG (0x07)
+#define AW_PID_2049_I2SCFG2_REG (0x08)
+#define AW_PID_2049_HAGCCFG1_REG (0x09)
+#define AW_PID_2049_HAGCCFG2_REG (0x0A)
+#define AW_PID_2049_HAGCCFG3_REG (0x0B)
+#define AW_PID_2049_HAGCCFG4_REG (0x0C)
+#define AW_PID_2049_HAGCCFG5_REG (0x0D)
+#define AW_PID_2049_HAGCCFG6_REG (0x0E)
+#define AW_PID_2049_HAGCCFG7_REG (0x0F)
+#define AW_PID_2049_MPDCFG_REG (0x10)
+#define AW_PID_2049_PWMCTRL_REG (0x11)
+#define AW_PID_2049_I2SCFG3_REG (0x12)
+#define AW_PID_2049_DBGCTRL_REG (0x13)
+#define AW_PID_2049_HAGCST_REG (0x20)
+#define AW_PID_2049_VBAT_REG (0x21)
+#define AW_PID_2049_TEMP_REG (0x22)
+#define AW_PID_2049_PVDD_REG (0x23)
+#define AW_PID_2049_ISNDAT_REG (0x24)
+#define AW_PID_2049_VSNDAT_REG (0x25)
+#define AW_PID_2049_I2SINT_REG (0x26)
+#define AW_PID_2049_I2SCAPCNT_REG (0x27)
+#define AW_PID_2049_ANASTA1_REG (0x28)
+#define AW_PID_2049_ANASTA2_REG (0x29)
+#define AW_PID_2049_ANASTA3_REG (0x2A)
+#define AW_PID_2049_ANASTA4_REG (0x2B)
+#define AW_PID_2049_TESTDET_REG (0x2C)
+#define AW_PID_2049_TESTIN_REG (0x38)
+#define AW_PID_2049_TESTOUT_REG (0x39)
+#define AW_PID_2049_DSPMADD_REG (0x40)
+#define AW_PID_2049_DSPMDAT_REG (0x41)
+#define AW_PID_2049_WDT_REG (0x42)
+#define AW_PID_2049_ACR1_REG (0x43)
+#define AW_PID_2049_ACR2_REG (0x44)
+#define AW_PID_2049_ASR1_REG (0x45)
+#define AW_PID_2049_ASR2_REG (0x46)
+#define AW_PID_2049_DSPCFG_REG (0x47)
+#define AW_PID_2049_ASR3_REG (0x48)
+#define AW_PID_2049_ASR4_REG (0x49)
+#define AW_PID_2049_VSNCTRL1_REG (0x50)
+#define AW_PID_2049_ISNCTRL1_REG (0x51)
+#define AW_PID_2049_PLLCTRL1_REG (0x52)
+#define AW_PID_2049_PLLCTRL2_REG (0x53)
+#define AW_PID_2049_PLLCTRL3_REG (0x54)
+#define AW_PID_2049_CDACTRL1_REG (0x55)
+#define AW_PID_2049_CDACTRL2_REG (0x56)
+#define AW_PID_2049_SADCCTRL1_REG (0x57)
+#define AW_PID_2049_SADCCTRL2_REG (0x58)
+#define AW_PID_2049_CPCTRL1_REG (0x59)
+#define AW_PID_2049_BSTCTRL1_REG (0x60)
+#define AW_PID_2049_BSTCTRL2_REG (0x61)
+#define AW_PID_2049_BSTCTRL3_REG (0x62)
+#define AW_PID_2049_BSTCTRL4_REG (0x63)
+#define AW_PID_2049_BSTCTRL5_REG (0x64)
+#define AW_PID_2049_BSTCTRL6_REG (0x65)
+#define AW_PID_2049_BSTCTRL7_REG (0x66)
+#define AW_PID_2049_DSMCFG1_REG (0x67)
+#define AW_PID_2049_DSMCFG2_REG (0x68)
+#define AW_PID_2049_DSMCFG3_REG (0x69)
+#define AW_PID_2049_DSMCFG4_REG (0x6A)
+#define AW_PID_2049_DSMCFG5_REG (0x6B)
+#define AW_PID_2049_DSMCFG6_REG (0x6C)
+#define AW_PID_2049_DSMCFG7_REG (0x6D)
+#define AW_PID_2049_DSMCFG8_REG (0x6E)
+#define AW_PID_2049_TESTCTRL1_REG (0x70)
+#define AW_PID_2049_TESTCTRL2_REG (0x71)
+#define AW_PID_2049_EFCTRL1_REG (0x72)
+#define AW_PID_2049_EFCTRL2_REG (0x73)
+#define AW_PID_2049_EFWH_REG (0x74)
+#define AW_PID_2049_EFWM2_REG (0x75)
+#define AW_PID_2049_EFWM1_REG (0x76)
+#define AW_PID_2049_EFWL_REG (0x77)
+#define AW_PID_2049_EFRH_REG (0x78)
+#define AW_PID_2049_EFRM2_REG (0x79)
+#define AW_PID_2049_EFRM1_REG (0x7A)
+#define AW_PID_2049_EFRL_REG (0x7B)
+#define AW_PID_2049_TM_REG (0x7C)
+
+enum aw883xx_id {
+ AW883XX_PID_2049 = 0x2049,
+};
+
+#define AW_PID_2049_REG_MAX (0x7D)
+
+#define AW_PID_2049_VOLUME_STEP_DB (6 * 8)
+
+#define AW_PID_2049_UVLS_START_BIT (14)
+#define AW_PID_2049_UVLS_NORMAL (0)
+#define AW_PID_2049_UVLS_NORMAL_VALUE \
+ (AW_PID_2049_UVLS_NORMAL << AW_PID_2049_UVLS_START_BIT)
+
+#define AW_PID_2049_DSPS_START_BIT (12)
+#define AW_PID_2049_DSPS_BITS_LEN (1)
+#define AW_PID_2049_DSPS_MASK \
+ (~(((1<<AW_PID_2049_DSPS_BITS_LEN)-1) << AW_PID_2049_DSPS_START_BIT))
+
+#define AW_PID_2049_DSPS_NORMAL (0)
+#define AW_PID_2049_DSPS_NORMAL_VALUE \
+ (AW_PID_2049_DSPS_NORMAL << AW_PID_2049_DSPS_START_BIT)
+
+#define AW_PID_2049_BSTOCS_START_BIT (11)
+#define AW_PID_2049_BSTOCS_OVER_CURRENT (1)
+#define AW_PID_2049_BSTOCS_OVER_CURRENT_VALUE \
+ (AW_PID_2049_BSTOCS_OVER_CURRENT << AW_PID_2049_BSTOCS_START_BIT)
+
+#define AW_PID_2049_BSTS_START_BIT (9)
+#define AW_PID_2049_BSTS_FINISHED (1)
+#define AW_PID_2049_BSTS_FINISHED_VALUE \
+ (AW_PID_2049_BSTS_FINISHED << AW_PID_2049_BSTS_START_BIT)
+
+#define AW_PID_2049_SWS_START_BIT (8)
+#define AW_PID_2049_SWS_SWITCHING (1)
+#define AW_PID_2049_SWS_SWITCHING_VALUE \
+ (AW_PID_2049_SWS_SWITCHING << AW_PID_2049_SWS_START_BIT)
+
+#define AW_PID_2049_NOCLKS_START_BIT (5)
+#define AW_PID_2049_NOCLKS_NO_CLOCK (1)
+#define AW_PID_2049_NOCLKS_NO_CLOCK_VALUE \
+ (AW_PID_2049_NOCLKS_NO_CLOCK << AW_PID_2049_NOCLKS_START_BIT)
+
+#define AW_PID_2049_CLKS_START_BIT (4)
+#define AW_PID_2049_CLKS_STABLE (1)
+#define AW_PID_2049_CLKS_STABLE_VALUE \
+ (AW_PID_2049_CLKS_STABLE << AW_PID_2049_CLKS_START_BIT)
+
+#define AW_PID_2049_OCDS_START_BIT (3)
+#define AW_PID_2049_OCDS_OC (1)
+#define AW_PID_2049_OCDS_OC_VALUE \
+ (AW_PID_2049_OCDS_OC << AW_PID_2049_OCDS_START_BIT)
+
+#define AW_PID_2049_OTHS_START_BIT (1)
+#define AW_PID_2049_OTHS_OT (1)
+#define AW_PID_2049_OTHS_OT_VALUE \
+ (AW_PID_2049_OTHS_OT << AW_PID_2049_OTHS_START_BIT)
+
+#define AW_PID_2049_PLLS_START_BIT (0)
+#define AW_PID_2049_PLLS_LOCKED (1)
+#define AW_PID_2049_PLLS_LOCKED_VALUE \
+ (AW_PID_2049_PLLS_LOCKED << AW_PID_2049_PLLS_START_BIT)
+
+#define AW_PID_2049_BIT_PLL_CHECK \
+ (AW_PID_2049_CLKS_STABLE_VALUE | \
+ AW_PID_2049_PLLS_LOCKED_VALUE)
+
+#define AW_PID_2049_BIT_SYSST_CHECK_MASK \
+ (~(AW_PID_2049_UVLS_NORMAL_VALUE | \
+ AW_PID_2049_BSTOCS_OVER_CURRENT_VALUE | \
+ AW_PID_2049_BSTS_FINISHED_VALUE | \
+ AW_PID_2049_SWS_SWITCHING_VALUE | \
+ AW_PID_2049_NOCLKS_NO_CLOCK_VALUE | \
+ AW_PID_2049_CLKS_STABLE_VALUE | \
+ AW_PID_2049_OCDS_OC_VALUE | \
+ AW_PID_2049_OTHS_OT_VALUE | \
+ AW_PID_2049_PLLS_LOCKED_VALUE))
+
+#define AW_PID_2049_BIT_SYSST_CHECK \
+ (AW_PID_2049_BSTS_FINISHED_VALUE | \
+ AW_PID_2049_SWS_SWITCHING_VALUE | \
+ AW_PID_2049_CLKS_STABLE_VALUE | \
+ AW_PID_2049_PLLS_LOCKED_VALUE)
+
+#define AW_PID_2049_WDI_START_BIT (6)
+#define AW_PID_2049_WDI_INT_VALUE (1)
+#define AW_PID_2049_WDI_INTERRUPT \
+ (AW_PID_2049_WDI_INT_VALUE << AW_PID_2049_WDI_START_BIT)
+
+#define AW_PID_2049_NOCLKI_START_BIT (5)
+#define AW_PID_2049_NOCLKI_INT_VALUE (1)
+#define AW_PID_2049_NOCLKI_INTERRUPT \
+ (AW_PID_2049_NOCLKI_INT_VALUE << AW_PID_2049_NOCLKI_START_BIT)
+
+#define AW_PID_2049_CLKI_START_BIT (4)
+#define AW_PID_2049_CLKI_INT_VALUE (1)
+#define AW_PID_2049_CLKI_INTERRUPT \
+ (AW_PID_2049_CLKI_INT_VALUE << AW_PID_2049_CLKI_START_BIT)
+
+#define AW_PID_2049_PLLI_START_BIT (0)
+#define AW_PID_2049_PLLI_INT_VALUE (1)
+#define AW_PID_2049_PLLI_INTERRUPT \
+ (AW_PID_2049_PLLI_INT_VALUE << AW_PID_2049_PLLI_START_BIT)
+
+#define AW_PID_2049_BIT_SYSINT_CHECK \
+ (AW_PID_2049_WDI_INTERRUPT | \
+ AW_PID_2049_CLKI_INTERRUPT | \
+ AW_PID_2049_NOCLKI_INTERRUPT | \
+ AW_PID_2049_PLLI_INTERRUPT)
+
+#define AW_PID_2049_HMUTE_START_BIT (8)
+#define AW_PID_2049_HMUTE_BITS_LEN (1)
+#define AW_PID_2049_HMUTE_MASK \
+ (~(((1<<AW_PID_2049_HMUTE_BITS_LEN)-1) << AW_PID_2049_HMUTE_START_BIT))
+
+#define AW_PID_2049_HMUTE_DISABLE (0)
+#define AW_PID_2049_HMUTE_DISABLE_VALUE \
+ (AW_PID_2049_HMUTE_DISABLE << AW_PID_2049_HMUTE_START_BIT)
+
+#define AW_PID_2049_HMUTE_ENABLE (1)
+#define AW_PID_2049_HMUTE_ENABLE_VALUE \
+ (AW_PID_2049_HMUTE_ENABLE << AW_PID_2049_HMUTE_START_BIT)
+
+#define AW_PID_2049_RCV_MODE_START_BIT (7)
+#define AW_PID_2049_RCV_MODE_BITS_LEN (1)
+#define AW_PID_2049_RCV_MODE_MASK \
+ (~(((1<<AW_PID_2049_RCV_MODE_BITS_LEN)-1) << AW_PID_2049_RCV_MODE_START_BIT))
+
+#define AW_PID_2049_RCV_MODE_RECEIVER (1)
+#define AW_PID_2049_RCV_MODE_RECEIVER_VALUE \
+ (AW_PID_2049_RCV_MODE_RECEIVER << AW_PID_2049_RCV_MODE_START_BIT)
+
+#define AW_PID_2049_DSPBY_START_BIT (2)
+#define AW_PID_2049_DSPBY_BITS_LEN (1)
+#define AW_PID_2049_DSPBY_MASK \
+ (~(((1<<AW_PID_2049_DSPBY_BITS_LEN)-1) << AW_PID_2049_DSPBY_START_BIT))
+
+#define AW_PID_2049_DSPBY_WORKING (0)
+#define AW_PID_2049_DSPBY_WORKING_VALUE \
+ (AW_PID_2049_DSPBY_WORKING << AW_PID_2049_DSPBY_START_BIT)
+
+#define AW_PID_2049_DSPBY_BYPASS (1)
+#define AW_PID_2049_DSPBY_BYPASS_VALUE \
+ (AW_PID_2049_DSPBY_BYPASS << AW_PID_2049_DSPBY_START_BIT)
+
+#define AW_PID_2049_AMPPD_START_BIT (1)
+#define AW_PID_2049_AMPPD_BITS_LEN (1)
+#define AW_PID_2049_AMPPD_MASK \
+ (~(((1<<AW_PID_2049_AMPPD_BITS_LEN)-1) << AW_PID_2049_AMPPD_START_BIT))
+
+#define AW_PID_2049_AMPPD_WORKING (0)
+#define AW_PID_2049_AMPPD_WORKING_VALUE \
+ (AW_PID_2049_AMPPD_WORKING << AW_PID_2049_AMPPD_START_BIT)
+
+#define AW_PID_2049_AMPPD_POWER_DOWN (1)
+#define AW_PID_2049_AMPPD_POWER_DOWN_VALUE \
+ (AW_PID_2049_AMPPD_POWER_DOWN << AW_PID_2049_AMPPD_START_BIT)
+
+#define AW_PID_2049_PWDN_START_BIT (0)
+#define AW_PID_2049_PWDN_BITS_LEN (1)
+#define AW_PID_2049_PWDN_MASK \
+ (~(((1<<AW_PID_2049_PWDN_BITS_LEN)-1) << AW_PID_2049_PWDN_START_BIT))
+
+#define AW_PID_2049_PWDN_WORKING (0)
+#define AW_PID_2049_PWDN_WORKING_VALUE \
+ (AW_PID_2049_PWDN_WORKING << AW_PID_2049_PWDN_START_BIT)
+
+#define AW_PID_2049_PWDN_POWER_DOWN (1)
+#define AW_PID_2049_PWDN_POWER_DOWN_VALUE \
+ (AW_PID_2049_PWDN_POWER_DOWN << AW_PID_2049_PWDN_START_BIT)
+
+#define AW_PID_2049_MUTE_VOL (90 * 8)
+#define AW_PID_2049_VOLUME_STEP_DB (6 * 8)
+
+#define AW_PID_2049_VOL_6DB_START (6)
+#define AW_PID_2049_VOL_START_BIT (6)
+#define AW_PID_2049_VOL_BITS_LEN (10)
+#define AW_PID_2049_VOL_MASK \
+ (~(((1<<AW_PID_2049_VOL_BITS_LEN)-1) << AW_PID_2049_VOL_START_BIT))
+
+#define AW_PID_2049_VOL_DEFAULT_VALUE (0)
+
+#define AW_PID_2049_I2STXEN_START_BIT (0)
+#define AW_PID_2049_I2STXEN_BITS_LEN (1)
+#define AW_PID_2049_I2STXEN_MASK \
+ (~(((1<<AW_PID_2049_I2STXEN_BITS_LEN)-1) << AW_PID_2049_I2STXEN_START_BIT))
+
+#define AW_PID_2049_I2STXEN_DISABLE (0)
+#define AW_PID_2049_I2STXEN_DISABLE_VALUE \
+ (AW_PID_2049_I2STXEN_DISABLE << AW_PID_2049_I2STXEN_START_BIT)
+
+#define AW_PID_2049_I2STXEN_ENABLE (1)
+#define AW_PID_2049_I2STXEN_ENABLE_VALUE \
+ (AW_PID_2049_I2STXEN_ENABLE << AW_PID_2049_I2STXEN_START_BIT)
+
+#define AW_PID_2049_AGC_DSP_CTL_START_BIT (15)
+#define AW_PID_2049_AGC_DSP_CTL_BITS_LEN (1)
+#define AW_PID_2049_AGC_DSP_CTL_MASK \
+ (~(((1<<AW_PID_2049_AGC_DSP_CTL_BITS_LEN)-1) << AW_PID_2049_AGC_DSP_CTL_START_BIT))
+
+#define AW_PID_2049_AGC_DSP_CTL_DISABLE (0)
+#define AW_PID_2049_AGC_DSP_CTL_DISABLE_VALUE \
+ (AW_PID_2049_AGC_DSP_CTL_DISABLE << AW_PID_2049_AGC_DSP_CTL_START_BIT)
+
+#define AW_PID_2049_AGC_DSP_CTL_ENABLE (1)
+#define AW_PID_2049_AGC_DSP_CTL_ENABLE_VALUE \
+ (AW_PID_2049_AGC_DSP_CTL_ENABLE << AW_PID_2049_AGC_DSP_CTL_START_BIT)
+
+#define AW_PID_2049_VDSEL_START_BIT (0)
+#define AW_PID_2049_VDSEL_BITS_LEN (1)
+#define AW_PID_2049_VDSEL_MASK \
+ (~(((1<<AW_PID_2049_VDSEL_BITS_LEN)-1) << AW_PID_2049_VDSEL_START_BIT))
+
+#define AW_PID_2049_MEM_CLKSEL_START_BIT (3)
+#define AW_PID_2049_MEM_CLKSEL_BITS_LEN (1)
+#define AW_PID_2049_MEM_CLKSEL_MASK \
+ (~(((1<<AW_PID_2049_MEM_CLKSEL_BITS_LEN)-1) << AW_PID_2049_MEM_CLKSEL_START_BIT))
+
+#define AW_PID_2049_MEM_CLKSEL_OSC_CLK (0)
+#define AW_PID_2049_MEM_CLKSEL_OSC_CLK_VALUE \
+ (AW_PID_2049_MEM_CLKSEL_OSC_CLK << AW_PID_2049_MEM_CLKSEL_START_BIT)
+
+#define AW_PID_2049_MEM_CLKSEL_DAP_HCLK (1)
+#define AW_PID_2049_MEM_CLKSEL_DAP_HCLK_VALUE \
+ (AW_PID_2049_MEM_CLKSEL_DAP_HCLK << AW_PID_2049_MEM_CLKSEL_START_BIT)
+
+#define AW_PID_2049_CCO_MUX_START_BIT (14)
+#define AW_PID_2049_CCO_MUX_BITS_LEN (1)
+#define AW_PID_2049_CCO_MUX_MASK \
+ (~(((1<<AW_PID_2049_CCO_MUX_BITS_LEN)-1) << AW_PID_2049_CCO_MUX_START_BIT))
+
+#define AW_PID_2049_CCO_MUX_DIVIDED (0)
+#define AW_PID_2049_CCO_MUX_DIVIDED_VALUE \
+ (AW_PID_2049_CCO_MUX_DIVIDED << AW_PID_2049_CCO_MUX_START_BIT)
+
+#define AW_PID_2049_CCO_MUX_BYPASS (1)
+#define AW_PID_2049_CCO_MUX_BYPASS_VALUE \
+ (AW_PID_2049_CCO_MUX_BYPASS << AW_PID_2049_CCO_MUX_START_BIT)
+
+#define AW_PID_2049_EF_VSN_GESLP_START_BIT (0)
+#define AW_PID_2049_EF_VSN_GESLP_BITS_LEN (10)
+#define AW_PID_2049_EF_VSN_GESLP_MASK \
+ (~(((1<<AW_PID_2049_EF_VSN_GESLP_BITS_LEN)-1) << AW_PID_2049_EF_VSN_GESLP_START_BIT))
+
+#define AW_PID_2049_EF_VSN_GESLP_SIGN_MASK (~(1 << 9))
+#define AW_PID_2049_EF_VSN_GESLP_SIGN_NEG (0xfe00)
+
+#define AW_PID_2049_EF_ISN_GESLP_START_BIT (0)
+#define AW_PID_2049_EF_ISN_GESLP_BITS_LEN (10)
+#define AW_PID_2049_EF_ISN_GESLP_MASK \
+ (~(((1<<AW_PID_2049_EF_ISN_GESLP_BITS_LEN)-1) << AW_PID_2049_EF_ISN_GESLP_START_BIT))
+
+#define AW_PID_2049_EF_ISN_GESLP_SIGN_MASK (~(1 << 9))
+#define AW_PID_2049_EF_ISN_GESLP_SIGN_NEG (0xfe00)
+
+#define AW_PID_2049_CABL_BASE_VALUE (1000)
+#define AW_PID_2049_ICABLK_FACTOR (1)
+#define AW_PID_2049_VCABLK_FACTOR (1)
+#define AW_PID_2049_VCAL_FACTOR (1 << 12)
+#define AW_PID_2049_VSCAL_FACTOR (16500)
+#define AW_PID_2049_ISCAL_FACTOR (3667)
+#define AW_PID_2049_EF_VSENSE_GAIN_SHIFT (0)
+
+#define AW_PID_2049_VCABLK_FACTOR_DAC (2)
+#define AW_PID_2049_VSCAL_FACTOR_DAC (11790)
+#define AW_PID_2049_EF_DAC_GESLP_SHIFT (10)
+#define AW_PID_2049_EF_DAC_GESLP_SIGN_MASK (1 << 5)
+#define AW_PID_2049_EF_DAC_GESLP_SIGN_NEG (0xffc0)
+
+#define AW_PID_2049_VCALB_ADJ_FACTOR (12)
+
+#define AW_PID_2049_WDT_CNT_START_BIT (0)
+#define AW_PID_2049_WDT_CNT_BITS_LEN (8)
+#define AW_PID_2049_WDT_CNT_MASK \
+ (~(((1<<AW_PID_2049_WDT_CNT_BITS_LEN)-1) << AW_PID_2049_WDT_CNT_START_BIT))
+
+#define AW_PID_2049_DSP_CFG_ADDR (0x9C80)
+#define AW_PID_2049_DSP_FW_ADDR (0x8C00)
+#define AW_PID_2049_DSP_REG_VMAX (0x9C94)
+#define AW_PID_2049_DSP_REG_CFG_ADPZ_RE (0x9D00)
+#define AW_PID_2049_DSP_REG_VCALB (0x9CF7)
+#define AW_PID_2049_DSP_RE_SHIFT (12)
+
+#define AW_PID_2049_DSP_REG_CFG_ADPZ_RA (0x9D02)
+#define AW_PID_2049_DSP_REG_CRC_ADDR (0x9F42)
+#define AW_PID_2049_DSP_REG_CFGF0_FS (0x9F44)
+#define AW_PID_2049_DSP_CALI_F0_DELAY (0x9CFD)
+
+#endif
--
2.38.1
Hi,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on bff687b3dad6e0e56b27f4d3ed8a9695f35c7b1a]
url: https://github.com/intel-lab-lkp/linux/commits/wangweidong-a-awinic-com/ASoC-codecs-Add-i2c-and-codec-registration-for-aw883xx-and-their-associated-operation-functions/20221230-173723
base: bff687b3dad6e0e56b27f4d3ed8a9695f35c7b1a
patch link: https://lore.kernel.org/r/20221230093454.190579-5-wangweidong.a%40awinic.com
patch subject: [PATCH V8 4/5] ASoC: codecs: Aw883xx chip register file, data type file and Kconfig Makefile
config: loongarch-randconfig-s043-20221225
compiler: loongarch64-linux-gcc (GCC) 12.1.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# apt-get install sparse
# sparse version: v0.6.4-39-gce1a6720-dirty
# https://github.com/intel-lab-lkp/linux/commit/870b0ec7349df27824602f880bb5a2118aec84e5
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review wangweidong-a-awinic-com/ASoC-codecs-Add-i2c-and-codec-registration-for-aw883xx-and-their-associated-operation-functions/20221230-173723
git checkout 870b0ec7349df27824602f880bb5a2118aec84e5
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' O=build_dir ARCH=loongarch olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' O=build_dir ARCH=loongarch SHELL=/bin/bash sound/soc/codecs/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <[email protected]>
sparse warnings: (new ones prefixed by >>)
>> sound/soc/codecs/aw883xx/aw883xx_device.c:367:23: sparse: sparse: incorrect type in assignment (different base types) @@ expected unsigned short [usertype] data1 @@ got restricted __le16 [usertype] @@
sound/soc/codecs/aw883xx/aw883xx_device.c:367:23: sparse: expected unsigned short [usertype] data1
sound/soc/codecs/aw883xx/aw883xx_device.c:367:23: sparse: got restricted __le16 [usertype]
>> sound/soc/codecs/aw883xx/aw883xx_device.c:371:23: sparse: sparse: incorrect type in assignment (different base types) @@ expected unsigned int [usertype] data2 @@ got restricted __le32 [usertype] @@
sound/soc/codecs/aw883xx/aw883xx_device.c:371:23: sparse: expected unsigned int [usertype] data2
sound/soc/codecs/aw883xx/aw883xx_device.c:371:23: sparse: got restricted __le32 [usertype]
vim +367 sound/soc/codecs/aw883xx/aw883xx_device.c
acf2ebfd20ae60 Weidong Wang 2022-12-30 348
acf2ebfd20ae60 Weidong Wang 2022-12-30 349 static int aw_dev_modify_dsp_cfg(struct aw_device *aw_dev,
acf2ebfd20ae60 Weidong Wang 2022-12-30 350 unsigned int addr, unsigned int dsp_data, unsigned char data_type)
acf2ebfd20ae60 Weidong Wang 2022-12-30 351 {
acf2ebfd20ae60 Weidong Wang 2022-12-30 352 struct aw_sec_data_desc *crc_dsp_cfg = &aw_dev->crc_dsp_cfg;
acf2ebfd20ae60 Weidong Wang 2022-12-30 353 u32 addr_offset;
acf2ebfd20ae60 Weidong Wang 2022-12-30 354 u16 data1;
acf2ebfd20ae60 Weidong Wang 2022-12-30 355 u32 data2;
acf2ebfd20ae60 Weidong Wang 2022-12-30 356
acf2ebfd20ae60 Weidong Wang 2022-12-30 357 dev_dbg(aw_dev->dev, "addr:0x%x, dsp_data:0x%x", addr, dsp_data);
acf2ebfd20ae60 Weidong Wang 2022-12-30 358
acf2ebfd20ae60 Weidong Wang 2022-12-30 359 addr_offset = (addr - AW_PID_2049_DSP_CFG_ADDR) * 2;
acf2ebfd20ae60 Weidong Wang 2022-12-30 360 if (addr_offset > crc_dsp_cfg->len) {
acf2ebfd20ae60 Weidong Wang 2022-12-30 361 dev_err(aw_dev->dev, "addr_offset[%d] > crc_dsp_cfg->len[%d]",
acf2ebfd20ae60 Weidong Wang 2022-12-30 362 addr_offset, crc_dsp_cfg->len);
acf2ebfd20ae60 Weidong Wang 2022-12-30 363 return -EINVAL;
acf2ebfd20ae60 Weidong Wang 2022-12-30 364 }
acf2ebfd20ae60 Weidong Wang 2022-12-30 365 switch (data_type) {
acf2ebfd20ae60 Weidong Wang 2022-12-30 366 case AW_DSP_16_DATA:
acf2ebfd20ae60 Weidong Wang 2022-12-30 @367 data1 = cpu_to_le16((u16)dsp_data);
acf2ebfd20ae60 Weidong Wang 2022-12-30 368 memcpy(crc_dsp_cfg->data + addr_offset, (u8 *)&data1, 2);
acf2ebfd20ae60 Weidong Wang 2022-12-30 369 break;
acf2ebfd20ae60 Weidong Wang 2022-12-30 370 case AW_DSP_32_DATA:
acf2ebfd20ae60 Weidong Wang 2022-12-30 @371 data2 = cpu_to_le32(dsp_data);
acf2ebfd20ae60 Weidong Wang 2022-12-30 372 memcpy(crc_dsp_cfg->data + addr_offset, (u8 *)&data2, 4);
acf2ebfd20ae60 Weidong Wang 2022-12-30 373 break;
acf2ebfd20ae60 Weidong Wang 2022-12-30 374 default:
acf2ebfd20ae60 Weidong Wang 2022-12-30 375 dev_err(aw_dev->dev, "data type[%d] unsupported", data_type);
acf2ebfd20ae60 Weidong Wang 2022-12-30 376 return -EINVAL;
acf2ebfd20ae60 Weidong Wang 2022-12-30 377 }
acf2ebfd20ae60 Weidong Wang 2022-12-30 378
acf2ebfd20ae60 Weidong Wang 2022-12-30 379 return 0;
acf2ebfd20ae60 Weidong Wang 2022-12-30 380 }
acf2ebfd20ae60 Weidong Wang 2022-12-30 381
--
0-DAY CI Kernel Test Service
https://01.org/lkp
Hi,
url: https://github.com/intel-lab-lkp/linux/commits/wangweidong-a-awinic-com/ASoC-codecs-Add-i2c-and-codec-registration-for-aw883xx-and-their-associated-operation-functions/20221230-173723
base: bff687b3dad6e0e56b27f4d3ed8a9695f35c7b1a
patch link: https://lore.kernel.org/r/20221230093454.190579-5-wangweidong.a%40awinic.com
patch subject: [PATCH V8 4/5] ASoC: codecs: Aw883xx chip register file, data type file and Kconfig Makefile
config: loongarch-randconfig-m031-20230103
compiler: loongarch64-linux-gcc (GCC) 12.1.0
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <[email protected]>
| Reported-by: Dan Carpenter <[email protected]>
New smatch warnings:
sound/soc/codecs/aw883xx/aw883xx_device.c:1163 aw_dev_dsp_update_container() warn: inconsistent returns '&aw_dev->dsp_lock'.
sound/soc/codecs/aw883xx/aw883xx_device.c:1303 aw_dev_check_sram() warn: inconsistent returns '&aw_dev->dsp_lock'.
Old smatch warnings:
sound/soc/codecs/aw883xx/aw883xx_device.c:1078 aw_dev_update_reg_container() error: uninitialized symbol 'ret'.
sound/soc/codecs/aw883xx/aw883xx_device.c:1271 aw_dev_check_sram() warn: missing unwind goto?
vim +1163 sound/soc/codecs/aw883xx/aw883xx_device.c
acf2ebfd20ae60 Weidong Wang 2022-12-30 1120 static int aw_dev_dsp_update_container(struct aw_device *aw_dev,
acf2ebfd20ae60 Weidong Wang 2022-12-30 1121 unsigned char *data, unsigned int len, unsigned short base)
acf2ebfd20ae60 Weidong Wang 2022-12-30 1122 {
acf2ebfd20ae60 Weidong Wang 2022-12-30 1123 #ifdef AW_DSP_I2C_WRITES
These ifdefs are not ideal.
acf2ebfd20ae60 Weidong Wang 2022-12-30 1124 u32 tmp_len;
acf2ebfd20ae60 Weidong Wang 2022-12-30 1125 #else
acf2ebfd20ae60 Weidong Wang 2022-12-30 1126 u16 reg_val;
acf2ebfd20ae60 Weidong Wang 2022-12-30 1127 #endif
acf2ebfd20ae60 Weidong Wang 2022-12-30 1128 int i, ret;
acf2ebfd20ae60 Weidong Wang 2022-12-30 1129
acf2ebfd20ae60 Weidong Wang 2022-12-30 1130 mutex_lock(&aw_dev->dsp_lock);
acf2ebfd20ae60 Weidong Wang 2022-12-30 1131 #ifdef AW_DSP_I2C_WRITES
acf2ebfd20ae60 Weidong Wang 2022-12-30 1132 ret = regmap_write(aw_dev->regmap, AW_PID_2049_DSPMADD_REG, base);
acf2ebfd20ae60 Weidong Wang 2022-12-30 1133 if (ret)
acf2ebfd20ae60 Weidong Wang 2022-12-30 1134 return ret;
acf2ebfd20ae60 Weidong Wang 2022-12-30 1135
acf2ebfd20ae60 Weidong Wang 2022-12-30 1136 for (i = 0; i < len; i += AW_MAX_RAM_WRITE_BYTE_SIZE) {
acf2ebfd20ae60 Weidong Wang 2022-12-30 1137 if ((len - i) < AW_MAX_RAM_WRITE_BYTE_SIZE)
acf2ebfd20ae60 Weidong Wang 2022-12-30 1138 tmp_len = len - i;
acf2ebfd20ae60 Weidong Wang 2022-12-30 1139 else
acf2ebfd20ae60 Weidong Wang 2022-12-30 1140 tmp_len = AW_MAX_RAM_WRITE_BYTE_SIZE;
acf2ebfd20ae60 Weidong Wang 2022-12-30 1141
acf2ebfd20ae60 Weidong Wang 2022-12-30 1142 ret = regmap_raw_write(aw_dev->regmap, AW_PID_2049_DSPMDAT_REG,
acf2ebfd20ae60 Weidong Wang 2022-12-30 1143 &data[i], tmp_len);
acf2ebfd20ae60 Weidong Wang 2022-12-30 1144 if (ret)
acf2ebfd20ae60 Weidong Wang 2022-12-30 1145 return ret;
Needs unlock before returning.
acf2ebfd20ae60 Weidong Wang 2022-12-30 1146 }
acf2ebfd20ae60 Weidong Wang 2022-12-30 1147
acf2ebfd20ae60 Weidong Wang 2022-12-30 1148 #else
acf2ebfd20ae60 Weidong Wang 2022-12-30 1149 /* i2c write */
acf2ebfd20ae60 Weidong Wang 2022-12-30 1150 ret = regmap_write(aw_dev->regmap, AW_PID_2049_DSPMADD_REG, base);
acf2ebfd20ae60 Weidong Wang 2022-12-30 1151 if (ret)
acf2ebfd20ae60 Weidong Wang 2022-12-30 1152 return ret;
Here too
acf2ebfd20ae60 Weidong Wang 2022-12-30 1153 for (i = 0; i < len; i += 2) {
acf2ebfd20ae60 Weidong Wang 2022-12-30 1154 reg_val = (data[i] << 8) + data[i + 1];
acf2ebfd20ae60 Weidong Wang 2022-12-30 1155 ret = regmap_write(aw_dev->regmap, AW_PID_2049_DSPMDAT_REG,
acf2ebfd20ae60 Weidong Wang 2022-12-30 1156 reg_val);
acf2ebfd20ae60 Weidong Wang 2022-12-30 1157 if (ret)
acf2ebfd20ae60 Weidong Wang 2022-12-30 1158 return ret;
Here.
acf2ebfd20ae60 Weidong Wang 2022-12-30 1159 }
acf2ebfd20ae60 Weidong Wang 2022-12-30 1160 #endif
acf2ebfd20ae60 Weidong Wang 2022-12-30 1161 mutex_unlock(&aw_dev->dsp_lock);
acf2ebfd20ae60 Weidong Wang 2022-12-30 1162
acf2ebfd20ae60 Weidong Wang 2022-12-30 @1163 return 0;
acf2ebfd20ae60 Weidong Wang 2022-12-30 1164 }
acf2ebfd20ae60 Weidong Wang 2022-12-30 1165
acf2ebfd20ae60 Weidong Wang 2022-12-30 1166 static int aw_dev_dsp_update_fw(struct aw_device *aw_dev,
acf2ebfd20ae60 Weidong Wang 2022-12-30 1167 unsigned char *data, unsigned int len)
acf2ebfd20ae60 Weidong Wang 2022-12-30 1168 {
acf2ebfd20ae60 Weidong Wang 2022-12-30 1169
acf2ebfd20ae60 Weidong Wang 2022-12-30 1170 dev_dbg(aw_dev->dev, "dsp firmware len:%d", len);
acf2ebfd20ae60 Weidong Wang 2022-12-30 1171
acf2ebfd20ae60 Weidong Wang 2022-12-30 1172 if (len && (data != NULL)) {
Flip this around.
if (!len || !data)
return -EINVAL;
Always do error handling, not success handling.
acf2ebfd20ae60 Weidong Wang 2022-12-30 1173 aw_dev_dsp_update_container(aw_dev,
acf2ebfd20ae60 Weidong Wang 2022-12-30 1174 data, len, AW_PID_2049_DSP_FW_ADDR);
acf2ebfd20ae60 Weidong Wang 2022-12-30 1175 aw_dev->dsp_fw_len = len;
acf2ebfd20ae60 Weidong Wang 2022-12-30 1176 } else {
acf2ebfd20ae60 Weidong Wang 2022-12-30 1177 dev_err(aw_dev->dev, "dsp firmware data is null or len is 0");
acf2ebfd20ae60 Weidong Wang 2022-12-30 1178 return -EINVAL;
acf2ebfd20ae60 Weidong Wang 2022-12-30 1179 }
acf2ebfd20ae60 Weidong Wang 2022-12-30 1180
acf2ebfd20ae60 Weidong Wang 2022-12-30 1181 return 0;
acf2ebfd20ae60 Weidong Wang 2022-12-30 1182 }
acf2ebfd20ae60 Weidong Wang 2022-12-30 1183
acf2ebfd20ae60 Weidong Wang 2022-12-30 1184 static int aw_dev_copy_to_crc_dsp_cfg(struct aw_device *aw_dev,
acf2ebfd20ae60 Weidong Wang 2022-12-30 1185 unsigned char *data, unsigned int size)
acf2ebfd20ae60 Weidong Wang 2022-12-30 1186 {
acf2ebfd20ae60 Weidong Wang 2022-12-30 1187 struct aw_sec_data_desc *crc_dsp_cfg = &aw_dev->crc_dsp_cfg;
acf2ebfd20ae60 Weidong Wang 2022-12-30 1188
acf2ebfd20ae60 Weidong Wang 2022-12-30 1189 if (!crc_dsp_cfg->data) {
acf2ebfd20ae60 Weidong Wang 2022-12-30 1190 crc_dsp_cfg->data = devm_kzalloc(aw_dev->dev, size, GFP_KERNEL);
acf2ebfd20ae60 Weidong Wang 2022-12-30 1191 if (!crc_dsp_cfg->data)
acf2ebfd20ae60 Weidong Wang 2022-12-30 1192 return -ENOMEM;
acf2ebfd20ae60 Weidong Wang 2022-12-30 1193 crc_dsp_cfg->len = size;
acf2ebfd20ae60 Weidong Wang 2022-12-30 1194 } else if (crc_dsp_cfg->len < size) {
acf2ebfd20ae60 Weidong Wang 2022-12-30 1195 devm_kfree(aw_dev->dev, crc_dsp_cfg->data);
acf2ebfd20ae60 Weidong Wang 2022-12-30 1196 crc_dsp_cfg->data = devm_kzalloc(aw_dev->dev, size, GFP_KERNEL);
acf2ebfd20ae60 Weidong Wang 2022-12-30 1197 if (!crc_dsp_cfg->data) {
acf2ebfd20ae60 Weidong Wang 2022-12-30 1198 dev_err(aw_dev->dev, "error allocating memory");
I am surprised this error message does not generate a checkpatch
warning. kmalloc() has its own better warnings. Delete this one.
acf2ebfd20ae60 Weidong Wang 2022-12-30 1199 return -ENOMEM;
acf2ebfd20ae60 Weidong Wang 2022-12-30 1200 }
acf2ebfd20ae60 Weidong Wang 2022-12-30 1201 crc_dsp_cfg->len = size;
acf2ebfd20ae60 Weidong Wang 2022-12-30 1202 }
acf2ebfd20ae60 Weidong Wang 2022-12-30 1203 memcpy(crc_dsp_cfg->data, data, size);
acf2ebfd20ae60 Weidong Wang 2022-12-30 1204 swab16_array((u16 *)crc_dsp_cfg->data, size >> 1);
acf2ebfd20ae60 Weidong Wang 2022-12-30 1205
acf2ebfd20ae60 Weidong Wang 2022-12-30 1206 return 0;
acf2ebfd20ae60 Weidong Wang 2022-12-30 1207 }
acf2ebfd20ae60 Weidong Wang 2022-12-30 1208
acf2ebfd20ae60 Weidong Wang 2022-12-30 1209 static int aw_dev_dsp_update_cfg(struct aw_device *aw_dev,
acf2ebfd20ae60 Weidong Wang 2022-12-30 1210 unsigned char *data, unsigned int len)
acf2ebfd20ae60 Weidong Wang 2022-12-30 1211 {
acf2ebfd20ae60 Weidong Wang 2022-12-30 1212 int ret;
acf2ebfd20ae60 Weidong Wang 2022-12-30 1213
acf2ebfd20ae60 Weidong Wang 2022-12-30 1214 dev_dbg(aw_dev->dev, "dsp config len:%d", len);
acf2ebfd20ae60 Weidong Wang 2022-12-30 1215
acf2ebfd20ae60 Weidong Wang 2022-12-30 1216 if (len && (data != NULL)) {
Flip this around.
if (!len || !data)
return -EINVAL;
aw_dev_dsp_update_container(aw_dev, data, len,
AW_PID_2049_DSP_CFG_ADDR);
acf2ebfd20ae60 Weidong Wang 2022-12-30 1217 aw_dev_dsp_update_container(aw_dev,
acf2ebfd20ae60 Weidong Wang 2022-12-30 1218 data, len, AW_PID_2049_DSP_CFG_ADDR);
acf2ebfd20ae60 Weidong Wang 2022-12-30 1219 aw_dev->dsp_cfg_len = len;
acf2ebfd20ae60 Weidong Wang 2022-12-30 1220
acf2ebfd20ae60 Weidong Wang 2022-12-30 1221 ret = aw_dev_copy_to_crc_dsp_cfg(aw_dev, data, len);
acf2ebfd20ae60 Weidong Wang 2022-12-30 1222 if (ret)
acf2ebfd20ae60 Weidong Wang 2022-12-30 1223 return ret;
acf2ebfd20ae60 Weidong Wang 2022-12-30 1224
acf2ebfd20ae60 Weidong Wang 2022-12-30 1225 ret = aw_dev_set_vcalb(aw_dev);
acf2ebfd20ae60 Weidong Wang 2022-12-30 1226 if (ret)
acf2ebfd20ae60 Weidong Wang 2022-12-30 1227 return ret;
acf2ebfd20ae60 Weidong Wang 2022-12-30 1228 ret = aw_dev_get_ra(&aw_dev->cali_desc);
acf2ebfd20ae60 Weidong Wang 2022-12-30 1229 if (ret)
acf2ebfd20ae60 Weidong Wang 2022-12-30 1230 return ret;
acf2ebfd20ae60 Weidong Wang 2022-12-30 1231 ret = aw_dev_get_cali_f0_delay(aw_dev);
acf2ebfd20ae60 Weidong Wang 2022-12-30 1232 if (ret)
acf2ebfd20ae60 Weidong Wang 2022-12-30 1233 return ret;
acf2ebfd20ae60 Weidong Wang 2022-12-30 1234
acf2ebfd20ae60 Weidong Wang 2022-12-30 1235 ret = aw_dev_get_vmax(aw_dev, &aw_dev->vmax_desc.init_vmax);
acf2ebfd20ae60 Weidong Wang 2022-12-30 1236 if (ret) {
acf2ebfd20ae60 Weidong Wang 2022-12-30 1237 dev_err(aw_dev->dev, "get vmax failed");
acf2ebfd20ae60 Weidong Wang 2022-12-30 1238 return ret;
acf2ebfd20ae60 Weidong Wang 2022-12-30 1239 }
acf2ebfd20ae60 Weidong Wang 2022-12-30 1240 dev_dbg(aw_dev->dev, "get init vmax:0x%x",
acf2ebfd20ae60 Weidong Wang 2022-12-30 1241 aw_dev->vmax_desc.init_vmax);
acf2ebfd20ae60 Weidong Wang 2022-12-30 1242 aw_dev->dsp_crc_st = AW_DSP_CRC_NA;
acf2ebfd20ae60 Weidong Wang 2022-12-30 1243 } else {
acf2ebfd20ae60 Weidong Wang 2022-12-30 1244 dev_err(aw_dev->dev, "dsp config data is null or len is 0");
acf2ebfd20ae60 Weidong Wang 2022-12-30 1245 return -EINVAL;
acf2ebfd20ae60 Weidong Wang 2022-12-30 1246 }
acf2ebfd20ae60 Weidong Wang 2022-12-30 1247
acf2ebfd20ae60 Weidong Wang 2022-12-30 1248 return 0;
acf2ebfd20ae60 Weidong Wang 2022-12-30 1249 }
acf2ebfd20ae60 Weidong Wang 2022-12-30 1250
acf2ebfd20ae60 Weidong Wang 2022-12-30 1251 static int aw_dev_check_sram(struct aw_device *aw_dev)
acf2ebfd20ae60 Weidong Wang 2022-12-30 1252 {
acf2ebfd20ae60 Weidong Wang 2022-12-30 1253 unsigned int reg_val;
acf2ebfd20ae60 Weidong Wang 2022-12-30 1254 int ret;
acf2ebfd20ae60 Weidong Wang 2022-12-30 1255
acf2ebfd20ae60 Weidong Wang 2022-12-30 1256 mutex_lock(&aw_dev->dsp_lock);
acf2ebfd20ae60 Weidong Wang 2022-12-30 1257 /* check the odd bits of reg 0x40 */
acf2ebfd20ae60 Weidong Wang 2022-12-30 1258 ret = regmap_write(aw_dev->regmap, AW_PID_2049_DSPMADD_REG, AW_DSP_ODD_NUM_BIT_TEST);
acf2ebfd20ae60 Weidong Wang 2022-12-30 1259 if (ret)
acf2ebfd20ae60 Weidong Wang 2022-12-30 1260 return ret;
goto error;
acf2ebfd20ae60 Weidong Wang 2022-12-30 1261 ret = regmap_read(aw_dev->regmap, AW_PID_2049_DSPMADD_REG, ®_val);
acf2ebfd20ae60 Weidong Wang 2022-12-30 1262 if (reg_val != AW_DSP_ODD_NUM_BIT_TEST || ret) {
acf2ebfd20ae60 Weidong Wang 2022-12-30 1263 dev_err(aw_dev->dev, "check reg 0x40 odd bit failed, read[0x%x] != write[0x%x]",
acf2ebfd20ae60 Weidong Wang 2022-12-30 1264 reg_val, AW_DSP_ODD_NUM_BIT_TEST);
This does not set the error code correctly. Technically, it reg_val is
unintialized if ret is negative so it's an uninitialized variable bug
as well. Write it like so:
ret = regmap_read(aw_dev->regmap, AW_PID_2049_DSPMADD_REG, ®_val);
if (ret)
goto error;
if (reg_val != AW_DSP_ODD_NUM_BIT_TEST) {
ret = -EINVAL;
goto error;
}
acf2ebfd20ae60 Weidong Wang 2022-12-30 1265 goto error;
acf2ebfd20ae60 Weidong Wang 2022-12-30 1266 }
acf2ebfd20ae60 Weidong Wang 2022-12-30 1267
acf2ebfd20ae60 Weidong Wang 2022-12-30 1268 /* check the even bits of reg 0x40 */
acf2ebfd20ae60 Weidong Wang 2022-12-30 1269 ret = regmap_write(aw_dev->regmap, AW_PID_2049_DSPMADD_REG, AW_DSP_EVEN_NUM_BIT_TEST);
acf2ebfd20ae60 Weidong Wang 2022-12-30 1270 if (ret)
acf2ebfd20ae60 Weidong Wang 2022-12-30 1271 return ret;
goto error;
acf2ebfd20ae60 Weidong Wang 2022-12-30 1272 ret = regmap_read(aw_dev->regmap, AW_PID_2049_DSPMADD_REG, ®_val);
acf2ebfd20ae60 Weidong Wang 2022-12-30 1273 if (reg_val != AW_DSP_EVEN_NUM_BIT_TEST || ret) {
acf2ebfd20ae60 Weidong Wang 2022-12-30 1274 dev_err(aw_dev->dev, "check reg 0x40 even bit failed, read[0x%x] != write[0x%x]",
acf2ebfd20ae60 Weidong Wang 2022-12-30 1275 reg_val, AW_DSP_EVEN_NUM_BIT_TEST);
acf2ebfd20ae60 Weidong Wang 2022-12-30 1276 goto error;
acf2ebfd20ae60 Weidong Wang 2022-12-30 1277 }
acf2ebfd20ae60 Weidong Wang 2022-12-30 1278
acf2ebfd20ae60 Weidong Wang 2022-12-30 1279 /* check dsp_fw_base_addr */
acf2ebfd20ae60 Weidong Wang 2022-12-30 1280 aw_dev_dsp_write_16bit(aw_dev, AW_PID_2049_DSP_FW_ADDR, AW_DSP_EVEN_NUM_BIT_TEST);
acf2ebfd20ae60 Weidong Wang 2022-12-30 1281 aw_dev_dsp_read_16bit(aw_dev, AW_PID_2049_DSP_FW_ADDR, ®_val);
acf2ebfd20ae60 Weidong Wang 2022-12-30 1282 if (reg_val != AW_DSP_EVEN_NUM_BIT_TEST) {
acf2ebfd20ae60 Weidong Wang 2022-12-30 1283 dev_err(aw_dev->dev, "check dsp fw addr failed, read[0x%x] != write[0x%x]",
acf2ebfd20ae60 Weidong Wang 2022-12-30 1284 reg_val, AW_DSP_EVEN_NUM_BIT_TEST);
acf2ebfd20ae60 Weidong Wang 2022-12-30 1285 goto error;
acf2ebfd20ae60 Weidong Wang 2022-12-30 1286 }
acf2ebfd20ae60 Weidong Wang 2022-12-30 1287
acf2ebfd20ae60 Weidong Wang 2022-12-30 1288 /* check dsp_cfg_base_addr */
acf2ebfd20ae60 Weidong Wang 2022-12-30 1289 aw_dev_dsp_write_16bit(aw_dev, AW_PID_2049_DSP_CFG_ADDR, AW_DSP_ODD_NUM_BIT_TEST);
acf2ebfd20ae60 Weidong Wang 2022-12-30 1290
acf2ebfd20ae60 Weidong Wang 2022-12-30 1291 aw_dev_dsp_read_16bit(aw_dev, AW_PID_2049_DSP_CFG_ADDR, ®_val);
acf2ebfd20ae60 Weidong Wang 2022-12-30 1292 if (reg_val != AW_DSP_ODD_NUM_BIT_TEST) {
acf2ebfd20ae60 Weidong Wang 2022-12-30 1293 dev_err(aw_dev->dev, "check dsp cfg failed, read[0x%x] != write[0x%x]",
acf2ebfd20ae60 Weidong Wang 2022-12-30 1294 reg_val, AW_DSP_ODD_NUM_BIT_TEST);
acf2ebfd20ae60 Weidong Wang 2022-12-30 1295 goto error;
acf2ebfd20ae60 Weidong Wang 2022-12-30 1296 }
acf2ebfd20ae60 Weidong Wang 2022-12-30 1297
acf2ebfd20ae60 Weidong Wang 2022-12-30 1298 mutex_unlock(&aw_dev->dsp_lock);
acf2ebfd20ae60 Weidong Wang 2022-12-30 1299 return 0;
acf2ebfd20ae60 Weidong Wang 2022-12-30 1300
acf2ebfd20ae60 Weidong Wang 2022-12-30 1301 error:
acf2ebfd20ae60 Weidong Wang 2022-12-30 1302 mutex_unlock(&aw_dev->dsp_lock);
acf2ebfd20ae60 Weidong Wang 2022-12-30 @1303 return -EPERM;
Oh. Huh. Change this to "return ret;"
acf2ebfd20ae60 Weidong Wang 2022-12-30 1304 }
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests