The patch, backwards compatible, extends the driver to initialize the
clock directly from the device tree.
Signed-off-by: Dario Binacchi <[email protected]>
---
drivers/clk/imx/clk-gate2.c | 86 +++++++++++++++++++++++++++++++++++++
1 file changed, 86 insertions(+)
diff --git a/drivers/clk/imx/clk-gate2.c b/drivers/clk/imx/clk-gate2.c
index f16c4019f402..b28150bf1ff6 100644
--- a/drivers/clk/imx/clk-gate2.c
+++ b/drivers/clk/imx/clk-gate2.c
@@ -12,9 +12,26 @@
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/err.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
#include <linux/string.h>
#include "clk.h"
+#define CLK_GATE2_CGR_DISABLED 0
+#define CLK_GATE2_CGR_RUN 1
+#define CLK_GATE2_CGR_RUN_WAIT 2
+#define CLK_GATE2_CGR_RUN_WAIT_STOP 3
+#define CLK_GATE2_CGR_MASK 3
+
+#define CLK_GATE2_MAX_GROUPS 16
+
+struct clk_gate2_group {
+ const char *name;
+ unsigned int share_count;
+};
+
+static struct clk_gate2_group clk_gate2_groups[CLK_GATE2_MAX_GROUPS];
+
/**
* DOC: basic gateable clock which can gate and ungate its output
*
@@ -175,3 +192,72 @@ struct clk_hw *clk_hw_register_gate2(struct device *dev, const char *name,
return hw;
}
EXPORT_SYMBOL_GPL(clk_hw_register_gate2);
+
+/**
+ * of_imx_gate2_clk_setup() - Setup function for imx low power gate
+ * clock
+ * @node: device node for the clock
+ */
+static void __init of_imx_gate2_clk_setup(struct device_node *node)
+{
+ void __iomem *reg;
+ u8 i, bit_idx = 0;
+ u8 cgr_val = CLK_GATE2_CGR_RUN_WAIT_STOP;
+ u8 cgr_mask = CLK_GATE2_CGR_MASK;
+ unsigned long flags = CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_PARENT;
+ u8 gate2_flags = 0;
+ unsigned int *share_count = NULL;
+ const char *name = node->name, *parent_name;
+ const char *str;
+ struct clk_hw *hw;
+ u32 val;
+
+ reg = of_iomap(node, 0);
+ if (IS_ERR(reg)) {
+ pr_err("failed to get reg address for %pOFn\n", node);
+ return;
+ }
+
+ if (!of_property_read_u32(node, "fsl,bit-shift", &val))
+ bit_idx = val;
+
+ if (of_clk_get_parent_count(node) != 1) {
+ pr_err("%pOFn must have 1 parent clock\n", node);
+ return;
+ }
+
+ if (!of_property_read_string(node, "sharing-group", &str)) {
+ for (i = 0; clk_gate2_groups[i].name &&
+ i < ARRAY_SIZE(clk_gate2_groups); i++) {
+ if (!strcmp(clk_gate2_groups[i].name, str)) {
+ share_count = &clk_gate2_groups[i].share_count;
+ break;
+ }
+ }
+
+ if (i == ARRAY_SIZE(clk_gate2_groups)) {
+ pr_err("failed to get shared count for %pOFn\n", node);
+ return;
+ }
+
+ if (!share_count) {
+ clk_gate2_groups[i].name =
+ kstrdup_const(str, GFP_KERNEL);
+ share_count = &clk_gate2_groups[i].share_count;
+ }
+ }
+
+ parent_name = of_clk_get_parent_name(node, 0);
+ of_property_read_string(node, "clock-output-names", &name);
+
+ hw = clk_hw_register_gate2(NULL, name, parent_name, flags, reg, bit_idx,
+ cgr_val, cgr_mask, gate2_flags,
+ &imx_ccm_lock, share_count);
+ if (!IS_ERR(hw))
+ of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw);
+
+ pr_debug("name: %s, parent: %s, enable-bit: %d, flags: 0x%lx, gate2_flags: 0x%x\n",
+ name, parent_name, bit_idx, flags, gate2_flags);
+}
+CLK_OF_DECLARE(fsl_imx8mn_gate2_clk, "fsl,imx8mn-low-power-gate-clock",
+ of_imx_gate2_clk_setup);
--
2.32.0