From: Sinthu Raja <[email protected]>
Hi All,
This series of patch add support to enable lanes 2 and 3 swap by
configuring the LN23 bit of the SerDes WIZ control register. Also,
it's possible that the Type-C plug orientation on the DIR line will
be implemented through hardware design. In that situation, there
won't be an external GPIO line available, but the driver still needs
to address this since the DT won't use the typec-dir-gpios property.
Update code to handle if typec-dir-gpios property is not specified in DT.
Changes in V2:
=============
Address review comments:
- Update commit description as per review comments.
- Restore code to check only debounce delay only if typec-dir-gpios property is specified in DT.
- Rename enum variable name from wiz_lane_typec_swap_mode to wiz_typec_master_lane.
- Rename lane_phy_reg variable as master_lane_num.
- Update inline comments.
V1: https://lore.kernel.org/lkml/[email protected]/T/
Sinthu Raja (2):
phy: ti: j721e-wiz: Manage TypeC lane swap if typec-dir-gpios not
specified
phy: ti: j721e-wiz: Add support to enable LN23 Type-C swap
drivers/phy/ti/phy-j721e-wiz.c | 66 ++++++++++++++++++++++++++++------
1 file changed, 56 insertions(+), 10 deletions(-)
--
2.36.1
From: Sinthu Raja <[email protected]>
The WIZ acts as a wrapper for SerDes and has Lanes 0 and 2 reserved
for USB for type-C lane swap if Lane 1 and Lane 3 are linked to the
USB PHY that is integrated into the SerDes IP. The WIZ control register
has to be configured to support this lane swap feature.
The support for swapping lanes 2 and 3 is missing and therefore
add support to configure the control register to swap between
lanes 2 and 3 if PHY type is USB.
Signed-off-by: Sinthu Raja <[email protected]>
---
Changes in V2:
=============
Address review comments:
- Update commit description.
- Rename enum variable name from wiz_lane_typec_swap_mode to wiz_typec_master_lane.
- Rename enumerators name specific to list of master lanes used for lane swapping.
- Add inline comments.
V1: https://lore.kernel.org/lkml/[email protected]/T/#m5e2d1a15d647f5df9dd28ed2dedc4b0812d6466f
drivers/phy/ti/phy-j721e-wiz.c | 33 ++++++++++++++++++++++++++++++---
1 file changed, 30 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index 571f0ca18874..815e8124b94a 100644
--- a/drivers/phy/ti/phy-j721e-wiz.c
+++ b/drivers/phy/ti/phy-j721e-wiz.c
@@ -58,6 +58,14 @@ enum wiz_lane_standard_mode {
LANE_MODE_GEN4,
};
+/*
+ * List of master lanes used for lane swapping
+ */
+enum wiz_typec_master_lane {
+ LANE0 = 0,
+ LANE2 = 2,
+};
+
enum wiz_refclk_mux_sel {
PLL0_REFCLK,
PLL1_REFCLK,
@@ -194,6 +202,9 @@ static const struct reg_field p_mac_div_sel1[WIZ_MAX_LANES] = {
static const struct reg_field typec_ln10_swap =
REG_FIELD(WIZ_SERDES_TYPEC, 30, 30);
+static const struct reg_field typec_ln23_swap =
+ REG_FIELD(WIZ_SERDES_TYPEC, 31, 31);
+
struct wiz_clk_mux {
struct clk_hw hw;
struct regmap_field *field;
@@ -367,6 +378,7 @@ struct wiz {
struct regmap_field *mux_sel_field[WIZ_MUX_NUM_CLOCKS];
struct regmap_field *div_sel_field[WIZ_DIV_NUM_CLOCKS_16G];
struct regmap_field *typec_ln10_swap;
+ struct regmap_field *typec_ln23_swap;
struct regmap_field *sup_legacy_clk_override;
struct device *dev;
@@ -676,6 +688,13 @@ static int wiz_regfield_init(struct wiz *wiz)
return PTR_ERR(wiz->typec_ln10_swap);
}
+ wiz->typec_ln23_swap = devm_regmap_field_alloc(dev, regmap,
+ typec_ln23_swap);
+ if (IS_ERR(wiz->typec_ln23_swap)) {
+ dev_err(dev, "LN23_SWAP reg field init failed\n");
+ return PTR_ERR(wiz->typec_ln23_swap);
+ }
+
wiz->phy_en_refclk = devm_regmap_field_alloc(dev, regmap, phy_en_refclk);
if (IS_ERR(wiz->phy_en_refclk)) {
dev_err(dev, "PHY_EN_REFCLK reg field init failed\n");
@@ -1254,9 +1273,17 @@ static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev,
int i;
for (i = 0; i < num_lanes; i++) {
- if ((wiz->lane_phy_type[i] == PHY_TYPE_USB3)
- && wiz->master_lane_num[i] == 0) {
- regmap_field_write(wiz->typec_ln10_swap, 1);
+ if (wiz->lane_phy_type[i] == PHY_TYPE_USB3) {
+ switch (wiz->master_lane_num[i]) {
+ case LANE0:
+ regmap_field_write(wiz->typec_ln10_swap, 1);
+ break;
+ case LANE2:
+ regmap_field_write(wiz->typec_ln23_swap, 1);
+ break;
+ default:
+ break;
+ }
}
}
}
--
2.36.1
On Wed, Jan 11, 2023 at 3:24 PM Roger Quadros <[email protected]> wrote:
>
> Hi Sinthu,
>
> On 06/01/2023 09:17, Sinthu Raja wrote:
> > From: Sinthu Raja <[email protected]>
> >
> > The WIZ acts as a wrapper for SerDes and has Lanes 0 and 2 reserved
> > for USB for type-C lane swap if Lane 1 and Lane 3 are linked to the
> > USB PHY that is integrated into the SerDes IP. The WIZ control register
> > has to be configured to support this lane swap feature.
> >
> > The support for swapping lanes 2 and 3 is missing and therefore
> > add support to configure the control register to swap between
> > lanes 2 and 3 if PHY type is USB.
> >
> > Signed-off-by: Sinthu Raja <[email protected]>
> > ---
> >
> > Changes in V2:
> > =============
> > Address review comments:
> > - Update commit description.
> > - Rename enum variable name from wiz_lane_typec_swap_mode to wiz_typec_master_lane.
> > - Rename enumerators name specific to list of master lanes used for lane swapping.
> > - Add inline comments.
> >
> > V1: https://linkprotect.cudasvc.com/url?a=https%3a%2f%2flore.kernel.org%2flkml%2f20221213124854.3779-2-sinthu.raja%40ti.com%2fT%2f%23m5e2d1a15d647f5df9dd28ed2dedc4b0812d6466f&c=E,1,Y-aGHFF9W5xMNeMlJ71LqKOZsmcrFFVOKtXq77GFhXQctctl3hRfr-TLmdAnjdaeSzzP0z8DPPPmxLORLMeyROZypsrLBJDsa2LdQkLThbo_gfu7bN9Uj_qC&typo=1
> >
> > drivers/phy/ti/phy-j721e-wiz.c | 33 ++++++++++++++++++++++++++++++---
> > 1 file changed, 30 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
> > index 571f0ca18874..815e8124b94a 100644
> > --- a/drivers/phy/ti/phy-j721e-wiz.c
> > +++ b/drivers/phy/ti/phy-j721e-wiz.c
> > @@ -58,6 +58,14 @@ enum wiz_lane_standard_mode {
> > LANE_MODE_GEN4,
> > };
> >
> > +/*
> > + * List of master lanes used for lane swapping
> > + */
> > +enum wiz_typec_master_lane {
> > + LANE0 = 0,
> > + LANE2 = 2,
> > +};
> > +
> > enum wiz_refclk_mux_sel {
> > PLL0_REFCLK,
> > PLL1_REFCLK,
> > @@ -194,6 +202,9 @@ static const struct reg_field p_mac_div_sel1[WIZ_MAX_LANES] = {
> > static const struct reg_field typec_ln10_swap =
> > REG_FIELD(WIZ_SERDES_TYPEC, 30, 30);
> >
> > +static const struct reg_field typec_ln23_swap =
> > + REG_FIELD(WIZ_SERDES_TYPEC, 31, 31);
> > +
> > struct wiz_clk_mux {
> > struct clk_hw hw;
> > struct regmap_field *field;
> > @@ -367,6 +378,7 @@ struct wiz {
> > struct regmap_field *mux_sel_field[WIZ_MUX_NUM_CLOCKS];
> > struct regmap_field *div_sel_field[WIZ_DIV_NUM_CLOCKS_16G];
> > struct regmap_field *typec_ln10_swap;
> > + struct regmap_field *typec_ln23_swap;
> > struct regmap_field *sup_legacy_clk_override;
> >
> > struct device *dev;
> > @@ -676,6 +688,13 @@ static int wiz_regfield_init(struct wiz *wiz)
> > return PTR_ERR(wiz->typec_ln10_swap);
> > }
> >
> > + wiz->typec_ln23_swap = devm_regmap_field_alloc(dev, regmap,
> > + typec_ln23_swap);
> > + if (IS_ERR(wiz->typec_ln23_swap)) {
> > + dev_err(dev, "LN23_SWAP reg field init failed\n");
> > + return PTR_ERR(wiz->typec_ln23_swap);
> > + }
> > +
> > wiz->phy_en_refclk = devm_regmap_field_alloc(dev, regmap, phy_en_refclk);
> > if (IS_ERR(wiz->phy_en_refclk)) {
> > dev_err(dev, "PHY_EN_REFCLK reg field init failed\n");
> > @@ -1254,9 +1273,17 @@ static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev,
> > int i;
> >
>
> Don't you have to update the below comment you added in patch 1 to mention about LN23 as well?
Thanks for the review, Roger.
Yes, I have to. My bad. I will send out another version updating this comment.
>
>
> + /* if no typec-dir gpio was specified and PHY type is
> + * USB3 with master lane number is '0', set LN10 SWAP
> + * bit to '1'
> + */
>
>
> > for (i = 0; i < num_lanes; i++) {
> > - if ((wiz->lane_phy_type[i] == PHY_TYPE_USB3)
> > - && wiz->master_lane_num[i] == 0) {
> > - regmap_field_write(wiz->typec_ln10_swap, 1);
> > + if (wiz->lane_phy_type[i] == PHY_TYPE_USB3) {
> > + switch (wiz->master_lane_num[i]) {
> > + case LANE0:
> > + regmap_field_write(wiz->typec_ln10_swap, 1);
> > + break;
> > + case LANE2:
> > + regmap_field_write(wiz->typec_ln23_swap, 1);
> > + break;
> > + default:
> > + break;
> > + }
> > }
> > }
> > }
>
> Otherwise looks good.
>
> cheers,
> -roger
>
--
With Regards
Sinthu Raja
Hi Sinthu,
On 06/01/2023 09:17, Sinthu Raja wrote:
> From: Sinthu Raja <[email protected]>
>
> The WIZ acts as a wrapper for SerDes and has Lanes 0 and 2 reserved
> for USB for type-C lane swap if Lane 1 and Lane 3 are linked to the
> USB PHY that is integrated into the SerDes IP. The WIZ control register
> has to be configured to support this lane swap feature.
>
> The support for swapping lanes 2 and 3 is missing and therefore
> add support to configure the control register to swap between
> lanes 2 and 3 if PHY type is USB.
>
> Signed-off-by: Sinthu Raja <[email protected]>
> ---
>
> Changes in V2:
> =============
> Address review comments:
> - Update commit description.
> - Rename enum variable name from wiz_lane_typec_swap_mode to wiz_typec_master_lane.
> - Rename enumerators name specific to list of master lanes used for lane swapping.
> - Add inline comments.
>
> V1: https://lore.kernel.org/lkml/[email protected]/T/#m5e2d1a15d647f5df9dd28ed2dedc4b0812d6466f
>
> drivers/phy/ti/phy-j721e-wiz.c | 33 ++++++++++++++++++++++++++++++---
> 1 file changed, 30 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
> index 571f0ca18874..815e8124b94a 100644
> --- a/drivers/phy/ti/phy-j721e-wiz.c
> +++ b/drivers/phy/ti/phy-j721e-wiz.c
> @@ -58,6 +58,14 @@ enum wiz_lane_standard_mode {
> LANE_MODE_GEN4,
> };
>
> +/*
> + * List of master lanes used for lane swapping
> + */
> +enum wiz_typec_master_lane {
> + LANE0 = 0,
> + LANE2 = 2,
> +};
> +
> enum wiz_refclk_mux_sel {
> PLL0_REFCLK,
> PLL1_REFCLK,
> @@ -194,6 +202,9 @@ static const struct reg_field p_mac_div_sel1[WIZ_MAX_LANES] = {
> static const struct reg_field typec_ln10_swap =
> REG_FIELD(WIZ_SERDES_TYPEC, 30, 30);
>
> +static const struct reg_field typec_ln23_swap =
> + REG_FIELD(WIZ_SERDES_TYPEC, 31, 31);
> +
> struct wiz_clk_mux {
> struct clk_hw hw;
> struct regmap_field *field;
> @@ -367,6 +378,7 @@ struct wiz {
> struct regmap_field *mux_sel_field[WIZ_MUX_NUM_CLOCKS];
> struct regmap_field *div_sel_field[WIZ_DIV_NUM_CLOCKS_16G];
> struct regmap_field *typec_ln10_swap;
> + struct regmap_field *typec_ln23_swap;
> struct regmap_field *sup_legacy_clk_override;
>
> struct device *dev;
> @@ -676,6 +688,13 @@ static int wiz_regfield_init(struct wiz *wiz)
> return PTR_ERR(wiz->typec_ln10_swap);
> }
>
> + wiz->typec_ln23_swap = devm_regmap_field_alloc(dev, regmap,
> + typec_ln23_swap);
> + if (IS_ERR(wiz->typec_ln23_swap)) {
> + dev_err(dev, "LN23_SWAP reg field init failed\n");
> + return PTR_ERR(wiz->typec_ln23_swap);
> + }
> +
> wiz->phy_en_refclk = devm_regmap_field_alloc(dev, regmap, phy_en_refclk);
> if (IS_ERR(wiz->phy_en_refclk)) {
> dev_err(dev, "PHY_EN_REFCLK reg field init failed\n");
> @@ -1254,9 +1273,17 @@ static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev,
> int i;
>
Don't you have to update the below comment you added in patch 1 to mention about LN23 as well?
+ /* if no typec-dir gpio was specified and PHY type is
+ * USB3 with master lane number is '0', set LN10 SWAP
+ * bit to '1'
+ */
> for (i = 0; i < num_lanes; i++) {
> - if ((wiz->lane_phy_type[i] == PHY_TYPE_USB3)
> - && wiz->master_lane_num[i] == 0) {
> - regmap_field_write(wiz->typec_ln10_swap, 1);
> + if (wiz->lane_phy_type[i] == PHY_TYPE_USB3) {
> + switch (wiz->master_lane_num[i]) {
> + case LANE0:
> + regmap_field_write(wiz->typec_ln10_swap, 1);
> + break;
> + case LANE2:
> + regmap_field_write(wiz->typec_ln23_swap, 1);
> + break;
> + default:
> + break;
> + }
> }
> }
> }
Otherwise looks good.
cheers,
-roger