This series is based on matthias github, for-next.
Allen-KH Cheng (9):
arm64: dts: mediatek: mt8186: Add MTU3 nodes
dt-bindings: spmi: spmi-mtk-pmif: Document mediatek,mt8195-spmi as
fallback of mediatek,mt8186-spmi
arm64: dts: mediatek: mt8186: Add SPMI node
arm64: dts: mediatek: mt8186: Add ADSP mailbox nodes
arm64: dts: mediatek: mt8186: Add ADSP node
arm64: dts: mediatek: mt8186: Add audio controller node
arm64: dts: mediatek: mt8186: Add DPI node
dt-bindings: display: mediatek: Fix the fallback for
mediatek,mt8186-disp-ccorr
arm64: dts: mediatek: mt8186: Add display nodes
.../display/mediatek/mediatek,ccorr.yaml | 2 +-
.../bindings/spmi/mtk,spmi-mtk-pmif.yaml | 11 +-
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 335 ++++++++++++++++++
3 files changed, 344 insertions(+), 4 deletions(-)
--
2.18.0
Add ADSP node for MT8186 SoC.
Signed-off-by: Allen-KH Cheng <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index a0b7dacc10cd..2700c830316f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -640,6 +640,26 @@
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>;
};
+ adsp: adsp@10680000 {
+ compatible = "mediatek,mt8186-dsp";
+ reg = <0 0x10680000 0 0x2000>,
+ <0 0x10800000 0 0x100000>,
+ <0 0x1068b000 0 0x100>,
+ <0 0x1068f000 0 0x1000>;
+ reg-names = "cfg", "sram", "sec", "bus";
+ clocks = <&topckgen CLK_TOP_AUDIODSP>,
+ <&topckgen CLK_TOP_ADSP_BUS>;
+ clock-names = "audiodsp",
+ "adsp_bus";
+ assigned-clocks = <&topckgen CLK_TOP_AUDIODSP>,
+ <&topckgen CLK_TOP_ADSP_BUS>;
+ assigned-clock-parents = <&clk26m>, <&topckgen CLK_TOP_MAINPLL_D2_D2>;
+ mbox-names = "rx", "tx";
+ mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_ADSP_TOP>;
+ status = "disabled";
+ };
+
adsp_mailbox0: mailbox@10686000 {
compatible = "mediatek,mt8186-adsp-mbox";
#mbox-cells = <0>;
--
2.18.0
Add SPMI node for MT8186 SoC.
Signed-off-by: Allen-KH Cheng <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index 3d88480913eb..a8ff984f1192 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -605,6 +605,25 @@
clock-names = "spi", "wrap";
};
+ spmi: spmi@10015000 {
+ compatible = "mediatek,mt8186-spmi",
+ "mediatek,mt8195-spmi";
+ reg = <0 0x10015000 0 0x000e00>,
+ <0 0x1001B000 0 0x000100>;
+ reg-names = "pmif", "spmimst";
+ clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
+ <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>,
+ <&topckgen CLK_TOP_SPMI_MST>;
+ clock-names = "pmif_sys_ck",
+ "pmif_tmr_ck",
+ "spmimst_clk_mux";
+ assigned-clocks = <&topckgen CLK_TOP_SPMI_MST>;
+ assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
+ interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>;
+ status = "disabled";
+ };
+
systimer: timer@10017000 {
compatible = "mediatek,mt8186-timer",
"mediatek,mt6765-timer";
--
2.18.0
Add MTU3 nodes for MT8186 SoC.
Signed-off-by: Allen-KH Cheng <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 75 ++++++++++++++++++++++++
1 file changed, 75 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index c0a3afd55eaf..3d88480913eb 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -908,6 +908,43 @@
status = "disabled";
};
+ ssusb0: usb@11201000 {
+ compatible = "mediatek,mt8186-mtu3",
+ "mediatek,mtu3";
+ reg = <0 0x11201000 0 0x2dff>,
+ <0 0x11203e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ clocks = <&topckgen CLK_TOP_USB_TOP>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>,
+ <&infracfg_ao CLK_INFRA_AO_ICUSB>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
+ interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>;
+ phys = <&u2port0 PHY_TYPE_USB2>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ usb_host0: usb@11200000 {
+ compatible = "mediatek,mt8186-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x11200000 0 0x1000>;
+ reg-names = "mac";
+ clocks = <&topckgen CLK_TOP_USB_TOP>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>,
+ <&infracfg_ao CLK_INFRA_AO_ICUSB>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
+ interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,syscon-wakeup = <&pericfg 0x420 2>;
+ wakeup-source;
+ status = "disabled";
+ };
+ };
+
mmc0: mmc@11230000 {
compatible = "mediatek,mt8186-mmc",
"mediatek,mt8183-mmc";
@@ -939,6 +976,44 @@
status = "disabled";
};
+ ssusb1: usb@11281000 {
+ compatible = "mediatek,mt8186-mtu3",
+ "mediatek,mtu3";
+ reg = <0 0x11281000 0 0x2dff>,
+ <0 0x11283e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>,
+ <&clk26m>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
+ interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>;
+ phys = <&u2port1 PHY_TYPE_USB2>,
+ <&u3port1 PHY_TYPE_USB3>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB_P1>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ usb_host1: usb@11280000 {
+ compatible = "mediatek,mt8186-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x11280000 0 0x1000>;
+ reg-names = "mac";
+ clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>,
+ <&clk26m>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck","xhci_ck";
+ interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,syscon-wakeup = <&pericfg 0x424 2>;
+ wakeup-source;
+ status = "disabled";
+ };
+ };
+
u3phy0: t-phy@11c80000 {
compatible = "mediatek,mt8186-tphy",
"mediatek,generic-tphy-v2";
--
2.18.0
The mt8186-disp-ccorr is not fully compatible with the mt8183-disp-ccorr
implementation. It causes a crash when system resumes if it binds to the
device.
We should use mt8192-disp-ccorr as fallback of mt8186-disp-ccorr.
Fixes: 8a26ea19d4dc ("dt-bindings: display: mediatek: add MT8186 SoC binding")
Signed-off-by: Allen-KH Cheng <[email protected]>
---
.../devicetree/bindings/display/mediatek/mediatek,ccorr.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
index 63fb02014a56..117e3db43f84 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
@@ -32,7 +32,7 @@ properties:
- items:
- enum:
- mediatek,mt8186-disp-ccorr
- - const: mediatek,mt8183-disp-ccorr
+ - const: mediatek,mt8192-disp-ccorr
reg:
maxItems: 1
--
2.18.0
Add DPI node for MT8186 SoC.
Signed-off-by: Allen-KH Cheng <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index c52f9be1e750..eab30ab01572 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -1230,6 +1230,23 @@
power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
};
+ dpi0: dpi@1400a000 {
+ compatible = "mediatek,mt8186-dpi";
+ reg = <0 0x1400a000 0 0x1000>;
+ clocks = <&topckgen CLK_TOP_DPI>,
+ <&mmsys CLK_MM_DISP_DPI>,
+ <&apmixedsys CLK_APMIXED_TVDPLL>;
+ clock-names = "pixel", "engine", "pll";
+ assigned-clocks = <&topckgen CLK_TOP_DPI>;
+ assigned-clock-parents = <&topckgen CLK_TOP_TVDPLL_D2>;
+ interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_LOW 0>;
+ status = "disabled";
+
+ port {
+ dpi_out: endpoint { };
+ };
+ };
+
dsi0: dsi@14013000 {
compatible = "mediatek,mt8186-dsi";
reg = <0 0x14013000 0 0x1000>;
--
2.18.0
On Wed, Jan 11, 2023 at 8:37 PM Allen-KH Cheng
<[email protected]> wrote:
>
> Add DPI node for MT8186 SoC.
>
> Signed-off-by: Allen-KH Cheng <[email protected]>
> ---
> arch/arm64/boot/dts/mediatek/mt8186.dtsi | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> index c52f9be1e750..eab30ab01572 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> @@ -1230,6 +1230,23 @@
> power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
> };
>
> + dpi0: dpi@1400a000 {
You could drop the trailing 0 in the label, since there is only one
instance.
Tested-by: Chen-Yu Tsai <[email protected]>
> + compatible = "mediatek,mt8186-dpi";
> + reg = <0 0x1400a000 0 0x1000>;
> + clocks = <&topckgen CLK_TOP_DPI>,
> + <&mmsys CLK_MM_DISP_DPI>,
> + <&apmixedsys CLK_APMIXED_TVDPLL>;
> + clock-names = "pixel", "engine", "pll";
> + assigned-clocks = <&topckgen CLK_TOP_DPI>;
> + assigned-clock-parents = <&topckgen CLK_TOP_TVDPLL_D2>;
> + interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_LOW 0>;
> + status = "disabled";
> +
> + port {
> + dpi_out: endpoint { };
> + };
> + };
> +
> dsi0: dsi@14013000 {
> compatible = "mediatek,mt8186-dsi";
> reg = <0 0x14013000 0 0x1000>;
> --
> 2.18.0
>
On Wed, Jan 11, 2023 at 8:37 PM Allen-KH Cheng
<[email protected]> wrote:
>
> Add MTU3 nodes for MT8186 SoC.
>
> Signed-off-by: Allen-KH Cheng <[email protected]>
Tested-by: Chen-Yu Tsai <[email protected]>
On Wed, 11 Jan 2023 20:37:10 +0800, Allen-KH Cheng wrote:
> The mt8186-disp-ccorr is not fully compatible with the mt8183-disp-ccorr
> implementation. It causes a crash when system resumes if it binds to the
> device.
>
> We should use mt8192-disp-ccorr as fallback of mt8186-disp-ccorr.
>
> Fixes: 8a26ea19d4dc ("dt-bindings: display: mediatek: add MT8186 SoC binding")
> Signed-off-by: Allen-KH Cheng <[email protected]>
> ---
> .../devicetree/bindings/display/mediatek/mediatek,ccorr.yaml | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Reviewed-by: Rob Herring <[email protected]>