The display subsystem and display port drivers for SC8280XP has been merged, so
they are dropped from this series.
The necessary defconfig update is also added to the series.
Bjorn Andersson (4):
arm64: dts: qcom: sc8280xp: Define some of the display blocks
arm64: dts: qcom: sc8280xp-crd: Enable EDP
arm64: dts: qcom: sa8295-adp: Enable DP instances
arm64: defconfig: Enable SC8280XP Display Clock Controller
arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 243 ++++++-
arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 73 +-
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 811 ++++++++++++++++++++++
arch/arm64/configs/defconfig | 1 +
4 files changed, 1125 insertions(+), 3 deletions(-)
--
2.37.3
From: Bjorn Andersson <[email protected]>
The SC8280XP CRD has a EDP display on MDSS0 DP3, enable relevant nodes
and link it together with the backlight control.
Signed-off-by: Bjorn Andersson <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
---
Changes since v6:
- None
arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 73 ++++++++++++++++++++++-
1 file changed, 72 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
index 551768f97729..db12d8678861 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
@@ -20,7 +20,7 @@ aliases {
serial0 = &qup2_uart17;
};
- backlight {
+ backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pmc8280c_lpg 3 1000000>;
enable-gpios = <&pmc8280_1_gpios 8 GPIO_ACTIVE_HIGH>;
@@ -34,6 +34,22 @@ chosen {
stdout-path = "serial0:115200n8";
};
+ vreg_edp_3p3: regulator-edp-3p3 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_EDP_3P3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&tlmm 25 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&edp_reg_en>;
+
+ regulator-boot-on;
+ };
+
vreg_edp_bl: regulator-edp-bl {
compatible = "regulator-fixed";
@@ -228,6 +244,55 @@ vreg_l9d: ldo9 {
};
};
+&dispcc0 {
+ status = "okay";
+};
+
+&mdss0 {
+ status = "okay";
+};
+
+&mdss0_dp3 {
+ compatible = "qcom,sc8280xp-edp";
+
+ data-lanes = <0 1 2 3>;
+
+ status = "okay";
+
+ aux-bus {
+ panel {
+ compatible = "edp-panel";
+ power-supply = <&vreg_edp_3p3>;
+
+ backlight = <&backlight>;
+
+ ports {
+ port {
+ edp_panel_in: endpoint {
+ remote-endpoint = <&mdss0_dp3_out>;
+ };
+ };
+ };
+ };
+ };
+
+ ports {
+ port@1 {
+ reg = <1>;
+ mdss0_dp3_out: endpoint {
+ remote-endpoint = <&edp_panel_in>;
+ };
+ };
+ };
+};
+
+&mdss0_dp3_phy {
+ vdda-phy-supply = <&vreg_l6b>;
+ vdda-pll-supply = <&vreg_l3b>;
+
+ status = "okay";
+};
+
&pcie2a {
perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
@@ -494,6 +559,12 @@ hastings_reg_en: hastings-reg-en-state {
&tlmm {
gpio-reserved-ranges = <74 6>, <83 4>, <125 2>, <128 2>, <154 7>;
+ edp_reg_en: edp-reg-en-state {
+ pins = "gpio25";
+ function = "gpio";
+ drive-strength = <16>;
+ };
+
kybd_default: kybd-default-state {
disable-pins {
pins = "gpio102";
--
2.37.3
From: Bjorn Andersson <[email protected]>
Define the display clock controllers, the MDSS instances, the DP phys
and connect these together.
Signed-off-by: Bjorn Andersson <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
---
Changes since v6:
- Dropped assigned-clock-rate on MDP_CLK
- Rearranged the properties in all nodes
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 811 +++++++++++++++++++++++++
1 file changed, 811 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 0ea2f19d471b..2ed17baf50d3 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -4,6 +4,7 @@
* Copyright (c) 2022, Linaro Limited
*/
+#include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
@@ -2097,6 +2098,42 @@ usb_1_qmpphy: phy@8903000 {
status = "disabled";
};
+ mdss1_dp0_phy: phy@8909a00 {
+ compatible = "qcom,sc8280xp-dp-phy";
+ reg = <0 0x08909a00 0 0x19c>,
+ <0 0x08909200 0 0xec>,
+ <0 0x08909600 0 0xec>,
+ <0 0x08909000 0 0x1c8>;
+
+ clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>,
+ <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
+ clock-names = "aux", "cfg_ahb";
+ power-domains = <&rpmhpd SC8280XP_MX>;
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ mdss1_dp1_phy: phy@890ca00 {
+ compatible = "qcom,sc8280xp-dp-phy";
+ reg = <0 0x0890ca00 0 0x19c>,
+ <0 0x0890c200 0 0xec>,
+ <0 0x0890c600 0 0xec>,
+ <0 0x0890c000 0 0x1c8>;
+
+ clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>,
+ <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
+ clock-names = "aux", "cfg_ahb";
+ power-domains = <&rpmhpd SC8280XP_MX>;
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
pmu@9091000 {
compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
reg = <0 0x9091000 0 0x1000>;
@@ -2303,6 +2340,314 @@ usb_1_dwc3: usb@a800000 {
};
};
+ mdss0: display-subsystem@ae00000 {
+ compatible = "qcom,sc8280xp-mdss";
+ reg = <0 0x0ae00000 0 0x1000>;
+ reg-names = "mdss";
+
+ clocks = <&gcc GCC_DISP_AHB_CLK>,
+ <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc0 DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface",
+ "ahb",
+ "core";
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
+ <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "mdp0-mem", "mdp1-mem";
+ iommus = <&apps_smmu 0x1000 0x402>;
+ power-domains = <&dispcc0 MDSS_GDSC>;
+ resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ mdss0_mdp: display-controller@ae01000 {
+ compatible = "qcom,sc8280xp-dpu";
+ reg = <0 0x0ae01000 0 0x8f000>,
+ <0 0x0aeb0000 0 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_SF_AXI_CLK>,
+ <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc0 DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "bus",
+ "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+ interrupt-parent = <&mdss0>;
+ interrupts = <0>;
+ power-domains = <&rpmhpd SC8280XP_MMCX>;
+
+ assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <19200000>;
+ operating-points-v2 = <&mdss0_mdp_opp_table>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@5 {
+ reg = <5>;
+ mdss0_intf5_out: endpoint {
+ remote-endpoint = <&mdss0_dp3_in>;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+ mdss0_intf6_out: endpoint {
+ remote-endpoint = <&mdss0_dp2_in>;
+ };
+ };
+ };
+
+ mdss0_mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-375000000 {
+ opp-hz = /bits/ 64 <375000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ required-opps = <&rpmhpd_opp_turbo_l1>;
+ };
+ };
+ };
+
+ mdss0_dp2: displayport-controller@ae9a000 {
+ compatible = "qcom,sc8280xp-dp";
+ reg = <0 0xae9a000 0 0x200>,
+ <0 0xae9a200 0 0x200>,
+ <0 0xae9a400 0 0x600>,
+ <0 0xae9b000 0 0x400>;
+
+ clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>,
+ <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>,
+ <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
+ <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
+ clock-names = "core_iface", "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface", "stream_pixel";
+ interrupt-parent = <&mdss0>;
+ interrupts = <14>;
+ phys = <&mdss0_dp2_phy>;
+ phy-names = "dp";
+ power-domains = <&rpmhpd SC8280XP_MMCX>;
+
+ assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
+ <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
+ assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>;
+ operating-points-v2 = <&mdss0_dp2_opp_table>;
+
+ #sound-dai-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdss0_dp2_in: endpoint {
+ remote-endpoint = <&mdss0_intf6_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+ };
+
+ mdss0_dp2_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-810000000 {
+ opp-hz = /bits/ 64 <810000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
+ mdss0_dp3: displayport-controller@aea0000 {
+ compatible = "qcom,sc8280xp-dp";
+ reg = <0 0xaea0000 0 0x200>,
+ <0 0xaea0200 0 0x200>,
+ <0 0xaea0400 0 0x600>,
+ <0 0xaea1000 0 0x400>;
+
+ clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>,
+ <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK>,
+ <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>,
+ <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>;
+ clock-names = "core_iface", "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface", "stream_pixel";
+ interrupt-parent = <&mdss0>;
+ interrupts = <15>;
+ phys = <&mdss0_dp3_phy>;
+ phy-names = "dp";
+ power-domains = <&dispcc0 MDSS_GDSC>;
+
+ assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
+ <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>;
+ assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>;
+ operating-points-v2 = <&mdss0_dp3_opp_table>;
+
+ #sound-dai-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdss0_dp3_in: endpoint {
+ remote-endpoint = <&mdss0_intf5_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+ };
+
+ mdss0_dp3_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-810000000 {
+ opp-hz = /bits/ 64 <810000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+ };
+
+ mdss0_dp2_phy: phy@aec2a00 {
+ compatible = "qcom,sc8280xp-dp-phy";
+ reg = <0 0x0aec2a00 0 0x19c>,
+ <0 0x0aec2200 0 0xec>,
+ <0 0x0aec2600 0 0xec>,
+ <0 0x0aec2000 0 0x1c8>;
+
+ clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>,
+ <&dispcc0 DISP_CC_MDSS_AHB_CLK>;
+ clock-names = "aux", "cfg_ahb";
+ power-domains = <&rpmhpd SC8280XP_MX>;
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ mdss0_dp3_phy: phy@aec5a00 {
+ compatible = "qcom,sc8280xp-dp-phy";
+ reg = <0 0x0aec5a00 0 0x19c>,
+ <0 0x0aec5200 0 0xec>,
+ <0 0x0aec5600 0 0xec>,
+ <0 0x0aec5000 0 0x1c8>;
+
+ clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>,
+ <&dispcc0 DISP_CC_MDSS_AHB_CLK>;
+ clock-names = "aux", "cfg_ahb";
+ power-domains = <&rpmhpd SC8280XP_MX>;
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ dispcc0: clock-controller@af00000 {
+ compatible = "qcom,sc8280xp-dispcc0";
+ reg = <0 0x0af00000 0 0x20000>;
+
+ clocks = <&gcc GCC_DISP_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&sleep_clk>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <&mdss0_dp2_phy 0>,
+ <&mdss0_dp2_phy 1>,
+ <&mdss0_dp3_phy 0>,
+ <&mdss0_dp3_phy 1>,
+ <0>,
+ <0>,
+ <0>,
+ <0>;
+ power-domains = <&rpmhpd SC8280XP_MMCX>;
+
+ #clock-cells = <1>;
+ #power-domain-cells = <1>;
+ #reset-cells = <1>;
+
+ status = "disabled";
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,sc8280xp-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
@@ -2925,6 +3270,472 @@ IPCC_MPROC_SIGNAL_GLINK_QMP
qcom,remote-pid = <12>;
};
};
+
+ mdss1: display-subsystem@22000000 {
+ compatible = "qcom,sc8280xp-mdss";
+ reg = <0 0x22000000 0 0x1000>;
+ reg-names = "mdss";
+
+ clocks = <&gcc GCC_DISP_AHB_CLK>,
+ <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc1 DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface",
+ "ahb",
+ "core";
+ interconnects = <&mmss_noc MASTER_MDP_CORE1_0 0 &mc_virt SLAVE_EBI1 0>,
+ <&mmss_noc MASTER_MDP_CORE1_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "mdp0-mem", "mdp1-mem";
+ interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+
+ iommus = <&apps_smmu 0x1800 0x402>;
+ power-domains = <&dispcc1 MDSS_GDSC>;
+ resets = <&dispcc1 DISP_CC_MDSS_CORE_BCR>;
+
+ #interrupt-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ mdss1_mdp: display-controller@22001000 {
+ compatible = "qcom,sc8280xp-dpu";
+ reg = <0 0x22001000 0 0x8f000>,
+ <0 0x220b0000 0 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_SF_AXI_CLK>,
+ <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc1 DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc1 DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "bus",
+ "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+ interrupt-parent = <&mdss1>;
+ interrupts = <0>;
+ power-domains = <&rpmhpd SC8280XP_MMCX>;
+
+ assigned-clocks = <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <19200000>;
+ operating-points-v2 = <&mdss1_mdp_opp_table>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdss1_intf0_out: endpoint {
+ remote-endpoint = <&mdss1_dp0_in>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+ mdss1_intf4_out: endpoint {
+ remote-endpoint = <&mdss1_dp1_in>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+ mdss1_intf5_out: endpoint {
+ remote-endpoint = <&mdss1_dp3_in>;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+ mdss1_intf6_out: endpoint {
+ remote-endpoint = <&mdss1_dp2_in>;
+ };
+ };
+ };
+
+ mdss1_mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-375000000 {
+ opp-hz = /bits/ 64 <375000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ required-opps = <&rpmhpd_opp_turbo_l1>;
+ };
+ };
+ };
+
+ mdss1_dp0: displayport-controller@22090000 {
+ compatible = "qcom,sc8280xp-dp";
+ reg = <0 0x22090000 0 0x200>,
+ <0 0x22090200 0 0x200>,
+ <0 0x22090400 0 0x600>,
+ <0 0x22091000 0 0x400>;
+
+ clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>,
+ <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK>,
+ <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
+ <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+ clock-names = "core_iface", "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface", "stream_pixel";
+ interrupt-parent = <&mdss1>;
+ interrupts = <12>;
+ phys = <&mdss1_dp0_phy>;
+ phy-names = "dp";
+ power-domains = <&rpmhpd SC8280XP_MMCX>;
+
+ assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
+ <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
+ assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>;
+ operating-points-v2 = <&mdss1_dp0_opp_table>;
+
+ #sound-dai-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdss1_dp0_in: endpoint {
+ remote-endpoint = <&mdss1_intf0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+ };
+
+ mdss1_dp0_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-810000000 {
+ opp-hz = /bits/ 64 <810000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+
+ };
+
+ mdss1_dp1: displayport-controller@22098000 {
+ compatible = "qcom,sc8280xp-dp";
+ reg = <0 0x22098000 0 0x200>,
+ <0 0x22098200 0 0x200>,
+ <0 0x22098400 0 0x600>,
+ <0 0x22099000 0 0x400>;
+
+ clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>,
+ <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK>,
+ <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
+ <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
+ clock-names = "core_iface", "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface", "stream_pixel";
+ interrupt-parent = <&mdss1>;
+ interrupts = <13>;
+ phys = <&mdss1_dp1_phy>;
+ phy-names = "dp";
+ power-domains = <&rpmhpd SC8280XP_MMCX>;
+
+ assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
+ <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
+ assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>;
+ operating-points-v2 = <&mdss1_dp1_opp_table>;
+
+ #sound-dai-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdss1_dp1_in: endpoint {
+ remote-endpoint = <&mdss1_intf4_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+ };
+
+ mdss1_dp1_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-810000000 {
+ opp-hz = /bits/ 64 <810000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
+ mdss1_dp2: displayport-controller@2209a000 {
+ compatible = "qcom,sc8280xp-dp";
+ reg = <0 0x2209a000 0 0x200>,
+ <0 0x2209a200 0 0x200>,
+ <0 0x2209a400 0 0x600>,
+ <0 0x2209b000 0 0x400>;
+
+ clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>,
+ <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK>,
+ <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
+ <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
+ clock-names = "core_iface", "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface", "stream_pixel";
+ interrupt-parent = <&mdss1>;
+ interrupts = <14>;
+ phys = <&mdss1_dp2_phy>;
+ phy-names = "dp";
+ power-domains = <&rpmhpd SC8280XP_MMCX>;
+
+ assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
+ <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
+ assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>;
+ operating-points-v2 = <&mdss1_dp2_opp_table>;
+
+ #sound-dai-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdss1_dp2_in: endpoint {
+ remote-endpoint = <&mdss1_intf6_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+ };
+
+ mdss1_dp2_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-810000000 {
+ opp-hz = /bits/ 64 <810000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
+ mdss1_dp3: displayport-controller@220a0000 {
+ compatible = "qcom,sc8280xp-dp";
+ reg = <0 0x220a0000 0 0x200>,
+ <0 0x220a0200 0 0x200>,
+ <0 0x220a0400 0 0x600>,
+ <0 0x220a1000 0 0x400>;
+
+ clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>,
+ <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK>,
+ <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>,
+ <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>;
+ clock-names = "core_iface", "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface", "stream_pixel";
+ interrupt-parent = <&mdss1>;
+ interrupts = <15>;
+ phys = <&mdss1_dp3_phy>;
+ phy-names = "dp";
+ power-domains = <&rpmhpd SC8280XP_MMCX>;
+
+ assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
+ <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>;
+ assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>;
+ operating-points-v2 = <&mdss1_dp3_opp_table>;
+
+ #sound-dai-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdss1_dp3_in: endpoint {
+ remote-endpoint = <&mdss1_intf5_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+ };
+
+ mdss1_dp3_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-810000000 {
+ opp-hz = /bits/ 64 <810000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+ };
+
+ mdss1_dp2_phy: phy@220c2a00 {
+ compatible = "qcom,sc8280xp-dp-phy";
+ reg = <0 0x220c2a00 0 0x19c>,
+ <0 0x220c2200 0 0xec>,
+ <0 0x220c2600 0 0xec>,
+ <0 0x220c2000 0 0x1c8>;
+
+ clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>,
+ <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
+ clock-names = "aux", "cfg_ahb";
+ power-domains = <&rpmhpd SC8280XP_MX>;
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ mdss1_dp3_phy: phy@220c5a00 {
+ compatible = "qcom,sc8280xp-dp-phy";
+ reg = <0 0x220c5a00 0 0x19c>,
+ <0 0x220c5200 0 0xec>,
+ <0 0x220c5600 0 0xec>,
+ <0 0x220c5000 0 0x1c8>;
+
+ clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>,
+ <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
+ clock-names = "aux", "cfg_ahb";
+ power-domains = <&rpmhpd SC8280XP_MX>;
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ dispcc1: clock-controller@22100000 {
+ compatible = "qcom,sc8280xp-dispcc1";
+ reg = <0 0x22100000 0 0x20000>;
+
+ clocks = <&gcc GCC_DISP_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <0>,
+ <&mdss1_dp0_phy 0>,
+ <&mdss1_dp0_phy 1>,
+ <&mdss1_dp1_phy 0>,
+ <&mdss1_dp1_phy 1>,
+ <&mdss1_dp2_phy 0>,
+ <&mdss1_dp2_phy 1>,
+ <&mdss1_dp3_phy 0>,
+ <&mdss1_dp3_phy 1>,
+ <0>,
+ <0>,
+ <0>,
+ <0>;
+ power-domains = <&rpmhpd SC8280XP_MMCX>;
+
+ #clock-cells = <1>;
+ #power-domain-cells = <1>;
+ #reset-cells = <1>;
+
+ status = "disabled";
+ };
};
sound: sound {
--
2.37.3
On 11.01.2023 04:59, Bjorn Andersson wrote:
> From: Bjorn Andersson <[email protected]>
>
> Define the display clock controllers, the MDSS instances, the DP phys
> and connect these together.
>
> Signed-off-by: Bjorn Andersson <[email protected]>
> Signed-off-by: Bjorn Andersson <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
>
> Changes since v6:
> - Dropped assigned-clock-rate on MDP_CLK
> - Rearranged the properties in all nodes
>
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 811 +++++++++++++++++++++++++
> 1 file changed, 811 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index 0ea2f19d471b..2ed17baf50d3 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -4,6 +4,7 @@
> * Copyright (c) 2022, Linaro Limited
> */
>
> +#include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
> #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
> #include <dt-bindings/clock/qcom,rpmh.h>
> #include <dt-bindings/interconnect/qcom,osm-l3.h>
> @@ -2097,6 +2098,42 @@ usb_1_qmpphy: phy@8903000 {
> status = "disabled";
> };
>
> + mdss1_dp0_phy: phy@8909a00 {
> + compatible = "qcom,sc8280xp-dp-phy";
> + reg = <0 0x08909a00 0 0x19c>,
> + <0 0x08909200 0 0xec>,
> + <0 0x08909600 0 0xec>,
> + <0 0x08909000 0 0x1c8>;
> +
> + clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>,
> + <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
> + clock-names = "aux", "cfg_ahb";
> + power-domains = <&rpmhpd SC8280XP_MX>;
> +
> + #clock-cells = <1>;
> + #phy-cells = <0>;
> +
> + status = "disabled";
> + };
> +
> + mdss1_dp1_phy: phy@890ca00 {
> + compatible = "qcom,sc8280xp-dp-phy";
> + reg = <0 0x0890ca00 0 0x19c>,
> + <0 0x0890c200 0 0xec>,
> + <0 0x0890c600 0 0xec>,
> + <0 0x0890c000 0 0x1c8>;
> +
> + clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>,
> + <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
> + clock-names = "aux", "cfg_ahb";
> + power-domains = <&rpmhpd SC8280XP_MX>;
> +
> + #clock-cells = <1>;
> + #phy-cells = <0>;
> +
> + status = "disabled";
> + };
> +
> pmu@9091000 {
> compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
> reg = <0 0x9091000 0 0x1000>;
> @@ -2303,6 +2340,314 @@ usb_1_dwc3: usb@a800000 {
> };
> };
>
> + mdss0: display-subsystem@ae00000 {
> + compatible = "qcom,sc8280xp-mdss";
> + reg = <0 0x0ae00000 0 0x1000>;
> + reg-names = "mdss";
> +
> + clocks = <&gcc GCC_DISP_AHB_CLK>,
> + <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc0 DISP_CC_MDSS_MDP_CLK>;
> + clock-names = "iface",
> + "ahb",
> + "core";
> + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
> + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "mdp0-mem", "mdp1-mem";
> + iommus = <&apps_smmu 0x1000 0x402>;
> + power-domains = <&dispcc0 MDSS_GDSC>;
> + resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>;
> +
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + status = "disabled";
> +
> + mdss0_mdp: display-controller@ae01000 {
> + compatible = "qcom,sc8280xp-dpu";
> + reg = <0 0x0ae01000 0 0x8f000>,
> + <0 0x0aeb0000 0 0x2008>;
> + reg-names = "mdp", "vbif";
> +
> + clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
> + <&gcc GCC_DISP_SF_AXI_CLK>,
> + <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>,
> + <&dispcc0 DISP_CC_MDSS_MDP_CLK>,
> + <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
> + clock-names = "bus",
> + "nrt_bus",
> + "iface",
> + "lut",
> + "core",
> + "vsync";
> + interrupt-parent = <&mdss0>;
> + interrupts = <0>;
> + power-domains = <&rpmhpd SC8280XP_MMCX>;
> +
> + assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
> + assigned-clock-rates = <19200000>;
> + operating-points-v2 = <&mdss0_mdp_opp_table>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@5 {
> + reg = <5>;
> + mdss0_intf5_out: endpoint {
> + remote-endpoint = <&mdss0_dp3_in>;
> + };
> + };
> +
> + port@6 {
> + reg = <6>;
> + mdss0_intf6_out: endpoint {
> + remote-endpoint = <&mdss0_dp2_in>;
> + };
> + };
> + };
> +
> + mdss0_mdp_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-200000000 {
> + opp-hz = /bits/ 64 <200000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-300000000 {
> + opp-hz = /bits/ 64 <300000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
> +
> + opp-375000000 {
> + opp-hz = /bits/ 64 <375000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + };
> +
> + opp-500000000 {
> + opp-hz = /bits/ 64 <500000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + };
> + opp-600000000 {
> + opp-hz = /bits/ 64 <600000000>;
> + required-opps = <&rpmhpd_opp_turbo_l1>;
> + };
> + };
> + };
> +
> + mdss0_dp2: displayport-controller@ae9a000 {
> + compatible = "qcom,sc8280xp-dp";
> + reg = <0 0xae9a000 0 0x200>,
> + <0 0xae9a200 0 0x200>,
> + <0 0xae9a400 0 0x600>,
> + <0 0xae9b000 0 0x400>;
> +
> + clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>,
> + <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>,
> + <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
> + <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
> + clock-names = "core_iface", "core_aux",
> + "ctrl_link",
> + "ctrl_link_iface", "stream_pixel";
> + interrupt-parent = <&mdss0>;
> + interrupts = <14>;
> + phys = <&mdss0_dp2_phy>;
> + phy-names = "dp";
> + power-domains = <&rpmhpd SC8280XP_MMCX>;
> +
> + assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
> + <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
> + assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>;
> + operating-points-v2 = <&mdss0_dp2_opp_table>;
> +
> + #sound-dai-cells = <0>;
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + mdss0_dp2_in: endpoint {
> + remote-endpoint = <&mdss0_intf6_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + };
> + };
> +
> + mdss0_dp2_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-160000000 {
> + opp-hz = /bits/ 64 <160000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-270000000 {
> + opp-hz = /bits/ 64 <270000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
> +
> + opp-540000000 {
> + opp-hz = /bits/ 64 <540000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + };
> +
> + opp-810000000 {
> + opp-hz = /bits/ 64 <810000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + };
> + };
> + };
> +
> + mdss0_dp3: displayport-controller@aea0000 {
> + compatible = "qcom,sc8280xp-dp";
> + reg = <0 0xaea0000 0 0x200>,
> + <0 0xaea0200 0 0x200>,
> + <0 0xaea0400 0 0x600>,
> + <0 0xaea1000 0 0x400>;
> +
> + clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>,
> + <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK>,
> + <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>,
> + <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>;
> + clock-names = "core_iface", "core_aux",
> + "ctrl_link",
> + "ctrl_link_iface", "stream_pixel";
> + interrupt-parent = <&mdss0>;
> + interrupts = <15>;
> + phys = <&mdss0_dp3_phy>;
> + phy-names = "dp";
> + power-domains = <&dispcc0 MDSS_GDSC>;
> +
> + assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
> + <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>;
> + assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>;
> + operating-points-v2 = <&mdss0_dp3_opp_table>;
> +
> + #sound-dai-cells = <0>;
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + mdss0_dp3_in: endpoint {
> + remote-endpoint = <&mdss0_intf5_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + };
> + };
> +
> + mdss0_dp3_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-160000000 {
> + opp-hz = /bits/ 64 <160000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-270000000 {
> + opp-hz = /bits/ 64 <270000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
> +
> + opp-540000000 {
> + opp-hz = /bits/ 64 <540000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + };
> +
> + opp-810000000 {
> + opp-hz = /bits/ 64 <810000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + };
> + };
> + };
> + };
> +
> + mdss0_dp2_phy: phy@aec2a00 {
> + compatible = "qcom,sc8280xp-dp-phy";
> + reg = <0 0x0aec2a00 0 0x19c>,
> + <0 0x0aec2200 0 0xec>,
> + <0 0x0aec2600 0 0xec>,
> + <0 0x0aec2000 0 0x1c8>;
> +
> + clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>,
> + <&dispcc0 DISP_CC_MDSS_AHB_CLK>;
> + clock-names = "aux", "cfg_ahb";
> + power-domains = <&rpmhpd SC8280XP_MX>;
> +
> + #clock-cells = <1>;
> + #phy-cells = <0>;
> +
> + status = "disabled";
> + };
> +
> + mdss0_dp3_phy: phy@aec5a00 {
> + compatible = "qcom,sc8280xp-dp-phy";
> + reg = <0 0x0aec5a00 0 0x19c>,
> + <0 0x0aec5200 0 0xec>,
> + <0 0x0aec5600 0 0xec>,
> + <0 0x0aec5000 0 0x1c8>;
> +
> + clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>,
> + <&dispcc0 DISP_CC_MDSS_AHB_CLK>;
> + clock-names = "aux", "cfg_ahb";
> + power-domains = <&rpmhpd SC8280XP_MX>;
> +
> + #clock-cells = <1>;
> + #phy-cells = <0>;
> +
> + status = "disabled";
> + };
> +
> + dispcc0: clock-controller@af00000 {
> + compatible = "qcom,sc8280xp-dispcc0";
> + reg = <0 0x0af00000 0 0x20000>;
> +
> + clocks = <&gcc GCC_DISP_AHB_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>,
> + <&sleep_clk>,
> + <0>,
> + <0>,
> + <0>,
> + <0>,
> + <&mdss0_dp2_phy 0>,
> + <&mdss0_dp2_phy 1>,
> + <&mdss0_dp3_phy 0>,
> + <&mdss0_dp3_phy 1>,
> + <0>,
> + <0>,
> + <0>,
> + <0>;
> + power-domains = <&rpmhpd SC8280XP_MMCX>;
> +
> + #clock-cells = <1>;
> + #power-domain-cells = <1>;
> + #reset-cells = <1>;
> +
> + status = "disabled";
> + };
> +
> pdc: interrupt-controller@b220000 {
> compatible = "qcom,sc8280xp-pdc", "qcom,pdc";
> reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
> @@ -2925,6 +3270,472 @@ IPCC_MPROC_SIGNAL_GLINK_QMP
> qcom,remote-pid = <12>;
> };
> };
> +
> + mdss1: display-subsystem@22000000 {
> + compatible = "qcom,sc8280xp-mdss";
> + reg = <0 0x22000000 0 0x1000>;
> + reg-names = "mdss";
> +
> + clocks = <&gcc GCC_DISP_AHB_CLK>,
> + <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc1 DISP_CC_MDSS_MDP_CLK>;
> + clock-names = "iface",
> + "ahb",
> + "core";
> + interconnects = <&mmss_noc MASTER_MDP_CORE1_0 0 &mc_virt SLAVE_EBI1 0>,
> + <&mmss_noc MASTER_MDP_CORE1_1 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "mdp0-mem", "mdp1-mem";
> + interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> +
> + iommus = <&apps_smmu 0x1800 0x402>;
> + power-domains = <&dispcc1 MDSS_GDSC>;
> + resets = <&dispcc1 DISP_CC_MDSS_CORE_BCR>;
> +
> + #interrupt-cells = <1>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + status = "disabled";
> +
> + mdss1_mdp: display-controller@22001000 {
> + compatible = "qcom,sc8280xp-dpu";
> + reg = <0 0x22001000 0 0x8f000>,
> + <0 0x220b0000 0 0x2008>;
> + reg-names = "mdp", "vbif";
> +
> + clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
> + <&gcc GCC_DISP_SF_AXI_CLK>,
> + <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc1 DISP_CC_MDSS_MDP_LUT_CLK>,
> + <&dispcc1 DISP_CC_MDSS_MDP_CLK>,
> + <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>;
> + clock-names = "bus",
> + "nrt_bus",
> + "iface",
> + "lut",
> + "core",
> + "vsync";
> + interrupt-parent = <&mdss1>;
> + interrupts = <0>;
> + power-domains = <&rpmhpd SC8280XP_MMCX>;
> +
> + assigned-clocks = <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>;
> + assigned-clock-rates = <19200000>;
> + operating-points-v2 = <&mdss1_mdp_opp_table>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + mdss1_intf0_out: endpoint {
> + remote-endpoint = <&mdss1_dp0_in>;
> + };
> + };
> +
> + port@4 {
> + reg = <4>;
> + mdss1_intf4_out: endpoint {
> + remote-endpoint = <&mdss1_dp1_in>;
> + };
> + };
> +
> + port@5 {
> + reg = <5>;
> + mdss1_intf5_out: endpoint {
> + remote-endpoint = <&mdss1_dp3_in>;
> + };
> + };
> +
> + port@6 {
> + reg = <6>;
> + mdss1_intf6_out: endpoint {
> + remote-endpoint = <&mdss1_dp2_in>;
> + };
> + };
> + };
> +
> + mdss1_mdp_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-200000000 {
> + opp-hz = /bits/ 64 <200000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-300000000 {
> + opp-hz = /bits/ 64 <300000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
> +
> + opp-375000000 {
> + opp-hz = /bits/ 64 <375000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + };
> +
> + opp-500000000 {
> + opp-hz = /bits/ 64 <500000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + };
> + opp-600000000 {
> + opp-hz = /bits/ 64 <600000000>;
> + required-opps = <&rpmhpd_opp_turbo_l1>;
> + };
> + };
> + };
> +
> + mdss1_dp0: displayport-controller@22090000 {
> + compatible = "qcom,sc8280xp-dp";
> + reg = <0 0x22090000 0 0x200>,
> + <0 0x22090200 0 0x200>,
> + <0 0x22090400 0 0x600>,
> + <0 0x22091000 0 0x400>;
> +
> + clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>,
> + <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK>,
> + <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
> + <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
> + clock-names = "core_iface", "core_aux",
> + "ctrl_link",
> + "ctrl_link_iface", "stream_pixel";
> + interrupt-parent = <&mdss1>;
> + interrupts = <12>;
> + phys = <&mdss1_dp0_phy>;
> + phy-names = "dp";
> + power-domains = <&rpmhpd SC8280XP_MMCX>;
> +
> + assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
> + <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
> + assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>;
> + operating-points-v2 = <&mdss1_dp0_opp_table>;
> +
> + #sound-dai-cells = <0>;
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + mdss1_dp0_in: endpoint {
> + remote-endpoint = <&mdss1_intf0_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + };
> + };
> +
> + mdss1_dp0_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-160000000 {
> + opp-hz = /bits/ 64 <160000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-270000000 {
> + opp-hz = /bits/ 64 <270000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
> +
> + opp-540000000 {
> + opp-hz = /bits/ 64 <540000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + };
> +
> + opp-810000000 {
> + opp-hz = /bits/ 64 <810000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + };
> + };
> +
> + };
> +
> + mdss1_dp1: displayport-controller@22098000 {
> + compatible = "qcom,sc8280xp-dp";
> + reg = <0 0x22098000 0 0x200>,
> + <0 0x22098200 0 0x200>,
> + <0 0x22098400 0 0x600>,
> + <0 0x22099000 0 0x400>;
> +
> + clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>,
> + <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK>,
> + <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
> + <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
> + clock-names = "core_iface", "core_aux",
> + "ctrl_link",
> + "ctrl_link_iface", "stream_pixel";
> + interrupt-parent = <&mdss1>;
> + interrupts = <13>;
> + phys = <&mdss1_dp1_phy>;
> + phy-names = "dp";
> + power-domains = <&rpmhpd SC8280XP_MMCX>;
> +
> + assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
> + <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
> + assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>;
> + operating-points-v2 = <&mdss1_dp1_opp_table>;
> +
> + #sound-dai-cells = <0>;
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + mdss1_dp1_in: endpoint {
> + remote-endpoint = <&mdss1_intf4_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + };
> + };
> +
> + mdss1_dp1_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-160000000 {
> + opp-hz = /bits/ 64 <160000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-270000000 {
> + opp-hz = /bits/ 64 <270000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
> +
> + opp-540000000 {
> + opp-hz = /bits/ 64 <540000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + };
> +
> + opp-810000000 {
> + opp-hz = /bits/ 64 <810000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + };
> + };
> + };
> +
> + mdss1_dp2: displayport-controller@2209a000 {
> + compatible = "qcom,sc8280xp-dp";
> + reg = <0 0x2209a000 0 0x200>,
> + <0 0x2209a200 0 0x200>,
> + <0 0x2209a400 0 0x600>,
> + <0 0x2209b000 0 0x400>;
> +
> + clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>,
> + <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK>,
> + <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
> + <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
> + clock-names = "core_iface", "core_aux",
> + "ctrl_link",
> + "ctrl_link_iface", "stream_pixel";
> + interrupt-parent = <&mdss1>;
> + interrupts = <14>;
> + phys = <&mdss1_dp2_phy>;
> + phy-names = "dp";
> + power-domains = <&rpmhpd SC8280XP_MMCX>;
> +
> + assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
> + <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
> + assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>;
> + operating-points-v2 = <&mdss1_dp2_opp_table>;
> +
> + #sound-dai-cells = <0>;
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + mdss1_dp2_in: endpoint {
> + remote-endpoint = <&mdss1_intf6_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + };
> + };
> +
> + mdss1_dp2_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-160000000 {
> + opp-hz = /bits/ 64 <160000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-270000000 {
> + opp-hz = /bits/ 64 <270000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
> +
> + opp-540000000 {
> + opp-hz = /bits/ 64 <540000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + };
> +
> + opp-810000000 {
> + opp-hz = /bits/ 64 <810000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + };
> + };
> + };
> +
> + mdss1_dp3: displayport-controller@220a0000 {
> + compatible = "qcom,sc8280xp-dp";
> + reg = <0 0x220a0000 0 0x200>,
> + <0 0x220a0200 0 0x200>,
> + <0 0x220a0400 0 0x600>,
> + <0 0x220a1000 0 0x400>;
> +
> + clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>,
> + <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK>,
> + <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>,
> + <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>;
> + clock-names = "core_iface", "core_aux",
> + "ctrl_link",
> + "ctrl_link_iface", "stream_pixel";
> + interrupt-parent = <&mdss1>;
> + interrupts = <15>;
> + phys = <&mdss1_dp3_phy>;
> + phy-names = "dp";
> + power-domains = <&rpmhpd SC8280XP_MMCX>;
> +
> + assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
> + <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>;
> + assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>;
> + operating-points-v2 = <&mdss1_dp3_opp_table>;
> +
> + #sound-dai-cells = <0>;
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + mdss1_dp3_in: endpoint {
> + remote-endpoint = <&mdss1_intf5_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + };
> + };
> +
> + mdss1_dp3_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-160000000 {
> + opp-hz = /bits/ 64 <160000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-270000000 {
> + opp-hz = /bits/ 64 <270000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
> +
> + opp-540000000 {
> + opp-hz = /bits/ 64 <540000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + };
> +
> + opp-810000000 {
> + opp-hz = /bits/ 64 <810000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + };
> + };
> + };
> + };
> +
> + mdss1_dp2_phy: phy@220c2a00 {
> + compatible = "qcom,sc8280xp-dp-phy";
> + reg = <0 0x220c2a00 0 0x19c>,
> + <0 0x220c2200 0 0xec>,
> + <0 0x220c2600 0 0xec>,
> + <0 0x220c2000 0 0x1c8>;
> +
> + clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>,
> + <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
> + clock-names = "aux", "cfg_ahb";
> + power-domains = <&rpmhpd SC8280XP_MX>;
> +
> + #clock-cells = <1>;
> + #phy-cells = <0>;
> +
> + status = "disabled";
> + };
> +
> + mdss1_dp3_phy: phy@220c5a00 {
> + compatible = "qcom,sc8280xp-dp-phy";
> + reg = <0 0x220c5a00 0 0x19c>,
> + <0 0x220c5200 0 0xec>,
> + <0 0x220c5600 0 0xec>,
> + <0 0x220c5000 0 0x1c8>;
> +
> + clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>,
> + <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
> + clock-names = "aux", "cfg_ahb";
> + power-domains = <&rpmhpd SC8280XP_MX>;
> +
> + #clock-cells = <1>;
> + #phy-cells = <0>;
> +
> + status = "disabled";
> + };
> +
> + dispcc1: clock-controller@22100000 {
> + compatible = "qcom,sc8280xp-dispcc1";
> + reg = <0 0x22100000 0 0x20000>;
> +
> + clocks = <&gcc GCC_DISP_AHB_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>,
> + <0>,
> + <&mdss1_dp0_phy 0>,
> + <&mdss1_dp0_phy 1>,
> + <&mdss1_dp1_phy 0>,
> + <&mdss1_dp1_phy 1>,
> + <&mdss1_dp2_phy 0>,
> + <&mdss1_dp2_phy 1>,
> + <&mdss1_dp3_phy 0>,
> + <&mdss1_dp3_phy 1>,
> + <0>,
> + <0>,
> + <0>,
> + <0>;
> + power-domains = <&rpmhpd SC8280XP_MMCX>;
> +
> + #clock-cells = <1>;
> + #power-domain-cells = <1>;
> + #reset-cells = <1>;
> +
> + status = "disabled";
> + };
> };
>
> sound: sound {
On 11.01.2023 04:59, Bjorn Andersson wrote:
> From: Bjorn Andersson <[email protected]>
>
> The SC8280XP CRD has a EDP display on MDSS0 DP3, enable relevant nodes
> and link it together with the backlight control.
>
> Signed-off-by: Bjorn Andersson <[email protected]>
> Signed-off-by: Bjorn Andersson <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
>
> Changes since v6:
> - None
>
> arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 73 ++++++++++++++++++++++-
> 1 file changed, 72 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> index 551768f97729..db12d8678861 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> @@ -20,7 +20,7 @@ aliases {
> serial0 = &qup2_uart17;
> };
>
> - backlight {
> + backlight: backlight {
> compatible = "pwm-backlight";
> pwms = <&pmc8280c_lpg 3 1000000>;
> enable-gpios = <&pmc8280_1_gpios 8 GPIO_ACTIVE_HIGH>;
> @@ -34,6 +34,22 @@ chosen {
> stdout-path = "serial0:115200n8";
> };
>
> + vreg_edp_3p3: regulator-edp-3p3 {
> + compatible = "regulator-fixed";
> +
> + regulator-name = "VREG_EDP_3P3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +
> + gpio = <&tlmm 25 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&edp_reg_en>;
> +
> + regulator-boot-on;
> + };
> +
> vreg_edp_bl: regulator-edp-bl {
> compatible = "regulator-fixed";
>
> @@ -228,6 +244,55 @@ vreg_l9d: ldo9 {
> };
> };
>
> +&dispcc0 {
> + status = "okay";
> +};
> +
> +&mdss0 {
> + status = "okay";
> +};
> +
> +&mdss0_dp3 {
> + compatible = "qcom,sc8280xp-edp";
> +
> + data-lanes = <0 1 2 3>;
> +
> + status = "okay";
> +
> + aux-bus {
> + panel {
> + compatible = "edp-panel";
> + power-supply = <&vreg_edp_3p3>;
> +
> + backlight = <&backlight>;
> +
> + ports {
> + port {
> + edp_panel_in: endpoint {
> + remote-endpoint = <&mdss0_dp3_out>;
> + };
> + };
> + };
> + };
> + };
> +
> + ports {
> + port@1 {
> + reg = <1>;
> + mdss0_dp3_out: endpoint {
> + remote-endpoint = <&edp_panel_in>;
> + };
> + };
> + };
> +};
> +
> +&mdss0_dp3_phy {
> + vdda-phy-supply = <&vreg_l6b>;
> + vdda-pll-supply = <&vreg_l3b>;
> +
> + status = "okay";
> +};
> +
> &pcie2a {
> perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
> wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
> @@ -494,6 +559,12 @@ hastings_reg_en: hastings-reg-en-state {
> &tlmm {
> gpio-reserved-ranges = <74 6>, <83 4>, <125 2>, <128 2>, <154 7>;
>
> + edp_reg_en: edp-reg-en-state {
> + pins = "gpio25";
> + function = "gpio";
> + drive-strength = <16>;
> + };
> +
> kybd_default: kybd-default-state {
> disable-pins {
> pins = "gpio102";
On Tue, Jan 10, 2023 at 07:59:03PM -0800, Bjorn Andersson wrote:
> From: Bjorn Andersson <[email protected]>
>
> Define the display clock controllers, the MDSS instances, the DP phys
> and connect these together.
>
> Signed-off-by: Bjorn Andersson <[email protected]>
> Signed-off-by: Bjorn Andersson <[email protected]>
> ---
>
> Changes since v6:
> - Dropped assigned-clock-rate on MDP_CLK
> - Rearranged the properties in all nodes
>
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 811 +++++++++++++++++++++++++
> 1 file changed, 811 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index 0ea2f19d471b..2ed17baf50d3 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> + mdss0_mdp: display-controller@ae01000 {
> + compatible = "qcom,sc8280xp-dpu";
> + reg = <0 0x0ae01000 0 0x8f000>,
> + <0 0x0aeb0000 0 0x2008>;
> + reg-names = "mdp", "vbif";
> +
> + clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
> + <&gcc GCC_DISP_SF_AXI_CLK>,
> + <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>,
> + <&dispcc0 DISP_CC_MDSS_MDP_CLK>,
> + <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
> + clock-names = "bus",
> + "nrt_bus",
> + "iface",
> + "lut",
> + "core",
> + "vsync";
> + interrupt-parent = <&mdss0>;
> + interrupts = <0>;
> + power-domains = <&rpmhpd SC8280XP_MMCX>;
> +
> + assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
> + assigned-clock-rates = <19200000>;
Nit: Shouldn't these come after the clock-names property as they did in
v5 so that the clock properties are grouped?
> + operating-points-v2 = <&mdss0_mdp_opp_table>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@5 {
> + reg = <5>;
> + mdss0_intf5_out: endpoint {
> + remote-endpoint = <&mdss0_dp3_in>;
> + };
> + };
> +
> + port@6 {
> + reg = <6>;
> + mdss0_intf6_out: endpoint {
> + remote-endpoint = <&mdss0_dp2_in>;
> + };
> + };
> + };
> + mdss0_dp2: displayport-controller@ae9a000 {
> + compatible = "qcom,sc8280xp-dp";
> + reg = <0 0xae9a000 0 0x200>,
> + <0 0xae9a200 0 0x200>,
> + <0 0xae9a400 0 0x600>,
> + <0 0xae9b000 0 0x400>;
> +
> + clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>,
> + <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>,
> + <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
> + <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
> + clock-names = "core_iface", "core_aux",
> + "ctrl_link",
> + "ctrl_link_iface", "stream_pixel";
> + interrupt-parent = <&mdss0>;
> + interrupts = <14>;
> + phys = <&mdss0_dp2_phy>;
> + phy-names = "dp";
> + power-domains = <&rpmhpd SC8280XP_MMCX>;
> +
> + assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
> + <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
> + assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>;
Same here.
> + operating-points-v2 = <&mdss0_dp2_opp_table>;
> +
> + #sound-dai-cells = <0>;
> +
> + status = "disabled";
> + mdss0_dp3: displayport-controller@aea0000 {
> + compatible = "qcom,sc8280xp-dp";
> + reg = <0 0xaea0000 0 0x200>,
> + <0 0xaea0200 0 0x200>,
> + <0 0xaea0400 0 0x600>,
> + <0 0xaea1000 0 0x400>;
> +
> + clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>,
> + <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK>,
> + <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>,
> + <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>;
> + clock-names = "core_iface", "core_aux",
> + "ctrl_link",
> + "ctrl_link_iface", "stream_pixel";
> + interrupt-parent = <&mdss0>;
> + interrupts = <15>;
> + phys = <&mdss0_dp3_phy>;
> + phy-names = "dp";
> + power-domains = <&dispcc0 MDSS_GDSC>;
> +
> + assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
> + <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>;
> + assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>;
And here.
> + operating-points-v2 = <&mdss0_dp3_opp_table>;
> +
> + #sound-dai-cells = <0>;
> +
> + status = "disabled";
> + mdss1: display-subsystem@22000000 {
> + compatible = "qcom,sc8280xp-mdss";
> + reg = <0 0x22000000 0 0x1000>;
> + reg-names = "mdss";
> +
> + clocks = <&gcc GCC_DISP_AHB_CLK>,
> + <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc1 DISP_CC_MDSS_MDP_CLK>;
> + clock-names = "iface",
> + "ahb",
> + "core";
> + interconnects = <&mmss_noc MASTER_MDP_CORE1_0 0 &mc_virt SLAVE_EBI1 0>,
> + <&mmss_noc MASTER_MDP_CORE1_1 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "mdp0-mem", "mdp1-mem";
> + interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
This is a provider property so perhaps it should go before
'#interrupt-cells' as it did above?
> +
> + iommus = <&apps_smmu 0x1800 0x402>;
> + power-domains = <&dispcc1 MDSS_GDSC>;
> + resets = <&dispcc1 DISP_CC_MDSS_CORE_BCR>;
> +
> + #interrupt-cells = <1>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + status = "disabled";
> +
> + mdss1_mdp: display-controller@22001000 {
> + compatible = "qcom,sc8280xp-dpu";
> + reg = <0 0x22001000 0 0x8f000>,
> + <0 0x220b0000 0 0x2008>;
> + reg-names = "mdp", "vbif";
> +
> + clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
> + <&gcc GCC_DISP_SF_AXI_CLK>,
> + <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc1 DISP_CC_MDSS_MDP_LUT_CLK>,
> + <&dispcc1 DISP_CC_MDSS_MDP_CLK>,
> + <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>;
> + clock-names = "bus",
> + "nrt_bus",
> + "iface",
> + "lut",
> + "core",
> + "vsync";
> + interrupt-parent = <&mdss1>;
> + interrupts = <0>;
> + power-domains = <&rpmhpd SC8280XP_MMCX>;
> +
> + assigned-clocks = <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>;
> + assigned-clock-rates = <19200000>;
Move after 'clock-names'?
There are a few more instances like this below.
Johan
On Tue, Jan 10, 2023 at 07:59:04PM -0800, Bjorn Andersson wrote:
> From: Bjorn Andersson <[email protected]>
>
> The SC8280XP CRD has a EDP display on MDSS0 DP3, enable relevant nodes
> and link it together with the backlight control.
>
> Signed-off-by: Bjorn Andersson <[email protected]>
> Signed-off-by: Bjorn Andersson <[email protected]>
> ---
>
> Changes since v6:
> - None
>
> arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 73 ++++++++++++++++++++++-
> 1 file changed, 72 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> index 551768f97729..db12d8678861 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> @@ -20,7 +20,7 @@ aliases {
> serial0 = &qup2_uart17;
> };
>
> - backlight {
> + backlight: backlight {
> compatible = "pwm-backlight";
> pwms = <&pmc8280c_lpg 3 1000000>;
> enable-gpios = <&pmc8280_1_gpios 8 GPIO_ACTIVE_HIGH>;
> @@ -34,6 +34,22 @@ chosen {
> stdout-path = "serial0:115200n8";
> };
>
> + vreg_edp_3p3: regulator-edp-3p3 {
> + compatible = "regulator-fixed";
> +
> + regulator-name = "VREG_EDP_3P3";
Looks like you forgot to change this to "VCC3LCD" which should be the
net name.
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +
> + gpio = <&tlmm 25 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&edp_reg_en>;
> +
> + regulator-boot-on;
> + };
> +
> vreg_edp_bl: regulator-edp-bl {
> compatible = "regulator-fixed";
> @@ -494,6 +559,12 @@ hastings_reg_en: hastings-reg-en-state {
> &tlmm {
> gpio-reserved-ranges = <74 6>, <83 4>, <125 2>, <128 2>, <154 7>;
>
> + edp_reg_en: edp-reg-en-state {
> + pins = "gpio25";
> + function = "gpio";
> + drive-strength = <16>;
'bias-disable' as well?
> + };
> +
> kybd_default: kybd-default-state {
> disable-pins {
> pins = "gpio102";
Looks good otherwise,
Reviewed-by: Johan Hovold <[email protected]>
Johan
On Wed, Jan 11, 2023 at 02:24:54PM +0100, Johan Hovold wrote:
> On Tue, Jan 10, 2023 at 07:59:04PM -0800, Bjorn Andersson wrote:
> > From: Bjorn Andersson <[email protected]>
> >
> > The SC8280XP CRD has a EDP display on MDSS0 DP3, enable relevant nodes
> > and link it together with the backlight control.
> >
> > Signed-off-by: Bjorn Andersson <[email protected]>
> > Signed-off-by: Bjorn Andersson <[email protected]>
> > ---
> >
> > Changes since v6:
> > - None
> >
> > arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 73 ++++++++++++++++++++++-
> > 1 file changed, 72 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> > index 551768f97729..db12d8678861 100644
> > --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> > +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> > @@ -20,7 +20,7 @@ aliases {
> > serial0 = &qup2_uart17;
> > };
> >
> > - backlight {
> > + backlight: backlight {
> > compatible = "pwm-backlight";
> > pwms = <&pmc8280c_lpg 3 1000000>;
> > enable-gpios = <&pmc8280_1_gpios 8 GPIO_ACTIVE_HIGH>;
> > @@ -34,6 +34,22 @@ chosen {
> > stdout-path = "serial0:115200n8";
> > };
> >
> > + vreg_edp_3p3: regulator-edp-3p3 {
> > + compatible = "regulator-fixed";
> > +
> > + regulator-name = "VREG_EDP_3P3";
>
> Looks like you forgot to change this to "VCC3LCD" which should be the
> net name.
>
That's because it's not called VCC3LCD on the CRD.
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > +
> > + gpio = <&tlmm 25 GPIO_ACTIVE_HIGH>;
> > + enable-active-high;
> > +
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&edp_reg_en>;
> > +
> > + regulator-boot-on;
> > + };
> > +
> > vreg_edp_bl: regulator-edp-bl {
> > compatible = "regulator-fixed";
>
> > @@ -494,6 +559,12 @@ hastings_reg_en: hastings-reg-en-state {
> > &tlmm {
> > gpio-reserved-ranges = <74 6>, <83 4>, <125 2>, <128 2>, <154 7>;
> >
> > + edp_reg_en: edp-reg-en-state {
> > + pins = "gpio25";
> > + function = "gpio";
> > + drive-strength = <16>;
>
> 'bias-disable' as well?
>
Sound like a good idea, adding that as I'm picking up the patches.
Regards,
Bjorn
> > + };
> > +
> > kybd_default: kybd-default-state {
> > disable-pins {
> > pins = "gpio102";
>
> Looks good otherwise,
>
> Reviewed-by: Johan Hovold <[email protected]>
>
> Johan
On Tue, 10 Jan 2023 19:59:02 -0800, Bjorn Andersson wrote:
> The display subsystem and display port drivers for SC8280XP has been merged, so
> they are dropped from this series.
>
> The necessary defconfig update is also added to the series.
>
> Bjorn Andersson (4):
> arm64: dts: qcom: sc8280xp: Define some of the display blocks
> arm64: dts: qcom: sc8280xp-crd: Enable EDP
> arm64: dts: qcom: sa8295-adp: Enable DP instances
> arm64: defconfig: Enable SC8280XP Display Clock Controller
>
> [...]
Applied, thanks!
[4/4] arm64: defconfig: Enable SC8280XP Display Clock Controller
commit: 41ddfbda83f23a7b007cf307409a17e3ece177c6
Best regards,
--
Bjorn Andersson <[email protected]>