This patchset adds USB controller and PHYs support to SM8550 platform
and enables them on the MTP board.
The v1 was here:
https://lore.kernel.org/all/[email protected]/
Changes since v1:
* fixed the clocks and clock-names of qmpphy to be aligned with sc8280xp
* dropped the child node from the phy nodes, like Johan suggested,
and updated to use the sc8280xp binding scheme
* moved status property last everywhere needed
* dropped the newline for phy-names, like Konrad suggested
* decided to move #address-cells, #size-cells and ranges properties
in such a way to be aligned with sc8280xp
Abel Vesa (2):
arm64: dts: qcom: sm8550: Add USB PHYs and controller nodes
arm64: dts: qcom: sm8550-mtp: Add USB PHYs and HC nodes
arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 22 ++++++
arch/arm64/boot/dts/qcom/sm8550.dtsi | 92 ++++++++++++++++++++++++-
2 files changed, 113 insertions(+), 1 deletion(-)
--
2.34.1
Enable USB HC and PHYs nodes on SM8550 MTP board.
Signed-off-by: Abel Vesa <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
index b69ded9c4b57..219001473f79 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
@@ -447,6 +447,28 @@ &ufs_mem_phy {
status = "okay";
};
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3 {
+ dr_mode = "peripheral";
+};
+
+&usb_1_hsphy {
+ vdd-supply = <&vreg_l1e_0p88>;
+ vdda12-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&usb_dp_qmpphy {
+ vdda-phy-supply = <&vreg_l3e_1p2>;
+ vdda-pll-supply = <&vreg_l3f_0p91>;
+
+ status = "okay";
+};
+
&xo_board {
clock-frequency = <76800000>;
};
--
2.34.1
Add USB host controller and PHY nodes.
Signed-off-by: Abel Vesa <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 92 +++++++++++++++++++++++++++-
1 file changed, 91 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index a78068cbf95f..bdbf5bf8aa7d 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -13,6 +13,7 @@
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/thermal/thermal.h>
/ {
@@ -652,7 +653,7 @@ gcc: clock-controller@100000 {
<&ufs_mem_phy 0>,
<&ufs_mem_phy 1>,
<&ufs_mem_phy 2>,
- <0>;
+ <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
};
ipcc: mailbox@408000 {
@@ -1934,6 +1935,95 @@ opp-202000000 {
};
};
+ usb_1_hsphy: phy@88e3000 {
+ compatible = "qcom,sm8550-snps-eusb2-phy";
+ reg = <0x0 0x088e3000 0x0 0x154>;
+ #phy-cells = <0>;
+
+ clocks = <&tcsr TCSR_USB2_CLKREF_EN>;
+ clock-names = "ref";
+
+ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+
+ status = "disabled";
+ };
+
+ usb_dp_qmpphy: phy@88e8000 {
+ compatible = "qcom,sm8550-qmp-usb3-dp-phy";
+ reg = <0x0 0x088e8000 0x0 0x3000>;
+
+ clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+ clock-names = "aux", "ref", "com_aux", "usb3_pipe";
+
+ power-domains = <&gcc USB3_PHY_GDSC>;
+
+ resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
+ <&gcc GCC_USB3_PHY_PRIM_BCR>;
+ reset-names = "phy", "common";
+
+ #clock-cells = <1>;
+ #phy-cells = <1>;
+
+ status = "disabled";
+ };
+
+ usb_1: usb@a6f8800 {
+ compatible = "qcom,sm8550-dwc3", "qcom,dwc3";
+ reg = <0x0 0x0a6f8800 0x0 0x400>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+ <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+ <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+ <&tcsr TCSR_USB3_CLKREF_EN>;
+ clock-names = "cfg_noc",
+ "core",
+ "iface",
+ "sleep",
+ "mock_utmi",
+ "xo";
+
+ assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <200000000>;
+
+ interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 15 IRQ_TYPE_EDGE_RISING>,
+ <&pdc 14 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "hs_phy_irq",
+ "ss_phy_irq",
+ "dm_hs_phy_irq",
+ "dp_hs_phy_irq";
+
+ power-domains = <&gcc USB30_PRIM_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
+
+ resets = <&gcc GCC_USB30_PRIM_BCR>;
+
+ status = "disabled";
+
+ usb_1_dwc3: usb@a600000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x0a600000 0x0 0xcd00>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&apps_smmu 0x40 0x0>;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ snps,usb3_lpm_capable;
+ phys = <&usb_1_hsphy>,
+ <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>;
+ phy-names = "usb2-phy", "usb3-phy";
+ };
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,sm8550-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
--
2.34.1
On Thu, 19 Jan 2023 02:45:31 +0200, Abel Vesa wrote:
> This patchset adds USB controller and PHYs support to SM8550 platform
> and enables them on the MTP board.
>
> The v1 was here:
> https://lore.kernel.org/all/[email protected]/
>
> Changes since v1:
> * fixed the clocks and clock-names of qmpphy to be aligned with sc8280xp
> * dropped the child node from the phy nodes, like Johan suggested,
> and updated to use the sc8280xp binding scheme
> * moved status property last everywhere needed
> * dropped the newline for phy-names, like Konrad suggested
> * decided to move #address-cells, #size-cells and ranges properties
> in such a way to be aligned with sc8280xp
>
> [...]
Applied, thanks!
[1/2] arm64: dts: qcom: sm8550: Add USB PHYs and controller nodes
commit: 7f7e5c1b037fc38dfc4f9530fcdb6fa8bd9fd01c
[2/2] arm64: dts: qcom: sm8550-mtp: Add USB PHYs and HC nodes
commit: 772e6bc4a0a9c426385115d720743bae7804d499
Best regards,
--
Bjorn Andersson <[email protected]>