Make various small changes to allow compile-testing on other arches.
This is helpful to allow testing changes to 32-bit arm drivers in the
same build.
The primary changes is to use macros for 64-bit divisions and shifts,
but we also need some other fixes to deal with larger constants and
differences in includes.
Signed-off-by: Sean Anderson <[email protected]>
---
Changes in v3:
- Include io.h for readl/writel
Changes in v2:
- Use BIT_ULL
drivers/gpu/drm/hisilicon/kirin/Kconfig | 2 +-
drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c | 10 +++++-----
drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h | 2 ++
drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h | 2 +-
4 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/hisilicon/kirin/Kconfig b/drivers/gpu/drm/hisilicon/kirin/Kconfig
index c5265675bf0c..0772f79567ef 100644
--- a/drivers/gpu/drm/hisilicon/kirin/Kconfig
+++ b/drivers/gpu/drm/hisilicon/kirin/Kconfig
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
config DRM_HISI_KIRIN
tristate "DRM Support for Hisilicon Kirin series SoCs Platform"
- depends on DRM && OF && ARM64
+ depends on DRM && OF && (ARM64 || COMPILE_TEST)
select DRM_KMS_HELPER
select DRM_GEM_DMA_HELPER
select DRM_MIPI_DSI
diff --git a/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c b/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
index d9978b79828c..1cfeffefd4b4 100644
--- a/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
+++ b/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
@@ -157,8 +157,8 @@ static u32 dsi_calc_phy_rate(u32 req_kHz, struct mipi_phy_params *phy)
q_pll = 0x10 >> (7 - phy->hstx_ckg_sel);
temp = f_kHz * (u64)q_pll * (u64)ref_clk_ps;
- m_n_int = temp / (u64)1000000000;
- m_n = (temp % (u64)1000000000) / (u64)100000000;
+ m_n_int = div_u64_rem(temp, 1000000000, &m_n);
+ m_n /= 100000000;
if (m_n_int % 2 == 0) {
if (m_n * 6 >= 50) {
@@ -229,8 +229,8 @@ static u32 dsi_calc_phy_rate(u32 req_kHz, struct mipi_phy_params *phy)
phy->pll_fbd_div5f = 1;
}
- f_kHz = (u64)1000000000 * (u64)m_pll /
- ((u64)ref_clk_ps * (u64)n_pll * (u64)q_pll);
+ f_kHz = div64_u64((u64)1000000000 * (u64)m_pll,
+ (u64)ref_clk_ps * (u64)n_pll * (u64)q_pll);
if (f_kHz >= req_kHz)
break;
@@ -490,7 +490,7 @@ static void dsi_set_mode_timing(void __iomem *base,
hsa_time = (hsw * lane_byte_clk_kHz) / pixel_clk_kHz;
hbp_time = (hbp * lane_byte_clk_kHz) / pixel_clk_kHz;
tmp = (u64)htot * (u64)lane_byte_clk_kHz;
- hline_time = DIV_ROUND_UP(tmp, pixel_clk_kHz);
+ hline_time = DIV64_U64_ROUND_UP(tmp, pixel_clk_kHz);
/* all specified in byte-lane clocks */
writel(hsa_time, base + VID_HSA_TIME);
diff --git a/drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h b/drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h
index d79fc031e53d..a87d1135856f 100644
--- a/drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h
+++ b/drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h
@@ -7,6 +7,8 @@
#ifndef __DW_DSI_REG_H__
#define __DW_DSI_REG_H__
+#include <linux/io.h>
+
#define MASK(x) (BIT(x) - 1)
/*
diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h b/drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h
index be9e789c2d04..36f923cc7594 100644
--- a/drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h
+++ b/drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h
@@ -10,7 +10,7 @@
/*
* ADE Registers
*/
-#define MASK(x) (BIT(x) - 1)
+#define MASK(x) (BIT_ULL(x) - 1)
#define ADE_CTRL 0x0004
#define FRM_END_START_OFST 0
--
2.35.1.1320.gc452695387.dirty
On Thu, Jan 19, 2023 at 11:01 AM Sean Anderson <[email protected]> wrote:
>
> Make various small changes to allow compile-testing on other arches.
> This is helpful to allow testing changes to 32-bit arm drivers in the
> same build.
>
> The primary changes is to use macros for 64-bit divisions and shifts,
> but we also need some other fixes to deal with larger constants and
> differences in includes.
>
> Signed-off-by: Sean Anderson <[email protected]>
No objection from me (though I'm not sure I really see the benefit of
test building this driver on 32bit).
I no longer have hardware to test with, so adding YongQin and Amit.
So maybe a tentative Acked-by: John Stultz <[email protected]>
thanks
-john
> ---
>
> Changes in v3:
> - Include io.h for readl/writel
>
> Changes in v2:
> - Use BIT_ULL
>
> drivers/gpu/drm/hisilicon/kirin/Kconfig | 2 +-
> drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c | 10 +++++-----
> drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h | 2 ++
> drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h | 2 +-
> 4 files changed, 9 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/hisilicon/kirin/Kconfig b/drivers/gpu/drm/hisilicon/kirin/Kconfig
> index c5265675bf0c..0772f79567ef 100644
> --- a/drivers/gpu/drm/hisilicon/kirin/Kconfig
> +++ b/drivers/gpu/drm/hisilicon/kirin/Kconfig
> @@ -1,7 +1,7 @@
> # SPDX-License-Identifier: GPL-2.0-only
> config DRM_HISI_KIRIN
> tristate "DRM Support for Hisilicon Kirin series SoCs Platform"
> - depends on DRM && OF && ARM64
> + depends on DRM && OF && (ARM64 || COMPILE_TEST)
> select DRM_KMS_HELPER
> select DRM_GEM_DMA_HELPER
> select DRM_MIPI_DSI
> diff --git a/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c b/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
> index d9978b79828c..1cfeffefd4b4 100644
> --- a/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
> +++ b/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
> @@ -157,8 +157,8 @@ static u32 dsi_calc_phy_rate(u32 req_kHz, struct mipi_phy_params *phy)
> q_pll = 0x10 >> (7 - phy->hstx_ckg_sel);
>
> temp = f_kHz * (u64)q_pll * (u64)ref_clk_ps;
> - m_n_int = temp / (u64)1000000000;
> - m_n = (temp % (u64)1000000000) / (u64)100000000;
> + m_n_int = div_u64_rem(temp, 1000000000, &m_n);
> + m_n /= 100000000;
>
> if (m_n_int % 2 == 0) {
> if (m_n * 6 >= 50) {
> @@ -229,8 +229,8 @@ static u32 dsi_calc_phy_rate(u32 req_kHz, struct mipi_phy_params *phy)
> phy->pll_fbd_div5f = 1;
> }
>
> - f_kHz = (u64)1000000000 * (u64)m_pll /
> - ((u64)ref_clk_ps * (u64)n_pll * (u64)q_pll);
> + f_kHz = div64_u64((u64)1000000000 * (u64)m_pll,
> + (u64)ref_clk_ps * (u64)n_pll * (u64)q_pll);
>
> if (f_kHz >= req_kHz)
> break;
> @@ -490,7 +490,7 @@ static void dsi_set_mode_timing(void __iomem *base,
> hsa_time = (hsw * lane_byte_clk_kHz) / pixel_clk_kHz;
> hbp_time = (hbp * lane_byte_clk_kHz) / pixel_clk_kHz;
> tmp = (u64)htot * (u64)lane_byte_clk_kHz;
> - hline_time = DIV_ROUND_UP(tmp, pixel_clk_kHz);
> + hline_time = DIV64_U64_ROUND_UP(tmp, pixel_clk_kHz);
>
> /* all specified in byte-lane clocks */
> writel(hsa_time, base + VID_HSA_TIME);
> diff --git a/drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h b/drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h
> index d79fc031e53d..a87d1135856f 100644
> --- a/drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h
> +++ b/drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h
> @@ -7,6 +7,8 @@
> #ifndef __DW_DSI_REG_H__
> #define __DW_DSI_REG_H__
>
> +#include <linux/io.h>
> +
> #define MASK(x) (BIT(x) - 1)
>
> /*
> diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h b/drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h
> index be9e789c2d04..36f923cc7594 100644
> --- a/drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h
> +++ b/drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h
> @@ -10,7 +10,7 @@
> /*
> * ADE Registers
> */
> -#define MASK(x) (BIT(x) - 1)
> +#define MASK(x) (BIT_ULL(x) - 1)
>
> #define ADE_CTRL 0x0004
> #define FRM_END_START_OFST 0
> --
> 2.35.1.1320.gc452695387.dirty
>