The uniphier-sd controller needs to control some siginals from the SD
interface logic to transition to UHS mode.
This series adds UHS mode support to the controller driver
to refer to and control the interface logic registers, which include
mode selector and SDR speed selector.
Kunihiko Hayashi (5):
dt-bindings: mmc: uniphier-sd: Add socionext,syscon-uhs-mode property
mmc: uniphier-sd: Add control of UHS mode using SD interface logic
mmc: uniphier-sd: Add control to switch UHS speed
ARM: dts: uniphier: Add syscon-uhs-mode to SD node
arm64: dts: uniphier: Add syscon-uhs-mode to SD node
.../bindings/mmc/socionext,uniphier-sd.yaml | 10 +++
arch/arm/boot/dts/uniphier-ld4.dtsi | 3 +-
arch/arm/boot/dts/uniphier-pro4.dtsi | 3 +-
arch/arm/boot/dts/uniphier-pro5.dtsi | 3 +-
arch/arm/boot/dts/uniphier-pxs2.dtsi | 3 +-
arch/arm/boot/dts/uniphier-sld8.dtsi | 3 +-
.../boot/dts/socionext/uniphier-ld20.dtsi | 3 +-
.../boot/dts/socionext/uniphier-pxs3.dtsi | 3 +-
drivers/mmc/host/uniphier-sd.c | 83 +++++++++++++++++--
9 files changed, 102 insertions(+), 12 deletions(-)
--
2.25.1
UHS mode control is included in the interface logic represented
by syscon. To refer this, add new property "socionext,syscon-uhs-mode".
Signed-off-by: Kunihiko Hayashi <[email protected]>
---
.../devicetree/bindings/mmc/socionext,uniphier-sd.yaml | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/socionext,uniphier-sd.yaml b/Documentation/devicetree/bindings/mmc/socionext,uniphier-sd.yaml
index a586fad0a46b..313621d0d9f5 100644
--- a/Documentation/devicetree/bindings/mmc/socionext,uniphier-sd.yaml
+++ b/Documentation/devicetree/bindings/mmc/socionext,uniphier-sd.yaml
@@ -55,6 +55,16 @@ properties:
minItems: 1
maxItems: 3
+ socionext,syscon-uhs-mode:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to syscon that configures uhs mode
+ - description: ID of SD instance
+ description:
+ A phandle to syscon with one argument that configures uhs mode.
+ The argument is the ID of SD instance.
+
allOf:
- $ref: mmc-controller.yaml
--
2.25.1
SD interface logic has the register to switch UHS speed.
The default is up to SDR25 and to support SDR50 or faster,
add uniphier_sd_speed_switch() function to switch the speed mode.
Signed-off-by: Kunihiko Hayashi <[email protected]>
---
drivers/mmc/host/uniphier-sd.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/drivers/mmc/host/uniphier-sd.c b/drivers/mmc/host/uniphier-sd.c
index c9766d6a690f..61acd69fac0e 100644
--- a/drivers/mmc/host/uniphier-sd.c
+++ b/drivers/mmc/host/uniphier-sd.c
@@ -54,6 +54,7 @@
#define UNIPHIER_SDCTRL_CHOFFSET 0x200
#define UNIPHIER_SDCTRL_MODE 0x30
#define UNIPHIER_SDCTRL_MODE_UHS1MOD BIT(15)
+#define UNIPHIER_SDCTRL_MODE_SDRSEL BIT(14)
/*
* IP is extended to support various features: built-in DMA engine,
@@ -429,6 +430,25 @@ static void uniphier_sd_hw_reset(struct mmc_host *mmc)
usleep_range(300, 1000);
}
+static void uniphier_sd_speed_switch(struct tmio_mmc_host *host)
+{
+ struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
+ unsigned int offset;
+ u32 val = 0;
+
+ if (!(host->mmc->caps & MMC_CAP_UHS))
+ return;
+
+ if (host->mmc->ios.timing == MMC_TIMING_UHS_SDR50 ||
+ host->mmc->ios.timing == MMC_TIMING_UHS_SDR104)
+ val = UNIPHIER_SDCTRL_MODE_SDRSEL;
+
+ offset = UNIPHIER_SDCTRL_CHOFFSET * priv->sdctrl_ch
+ + UNIPHIER_SDCTRL_MODE;
+ regmap_write_bits(priv->sdctrl_regmap, offset,
+ UNIPHIER_SDCTRL_MODE_SDRSEL, val);
+}
+
static void uniphier_sd_uhs_enable(struct tmio_mmc_host *host, bool uhs_en)
{
struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
@@ -459,6 +479,8 @@ static void uniphier_sd_set_clock(struct tmio_mmc_host *host,
tmp &= ~CLK_CTL_SCLKEN;
writel(tmp, host->ctl + (CTL_SD_CARD_CLK_CTL << 1));
+ uniphier_sd_speed_switch(host);
+
if (clock == 0)
return;
--
2.25.1
Add sociopnext,syscon-uhs-mode prpperty to the SD node to refer the handle
of the control logic node.
Signed-off-by: Kunihiko Hayashi <[email protected]>
---
arch/arm/boot/dts/uniphier-ld4.dtsi | 3 ++-
arch/arm/boot/dts/uniphier-pro4.dtsi | 3 ++-
arch/arm/boot/dts/uniphier-pro5.dtsi | 3 ++-
arch/arm/boot/dts/uniphier-pxs2.dtsi | 3 ++-
arch/arm/boot/dts/uniphier-sld8.dtsi | 3 ++-
5 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi
index 9dceff12a633..78cb3f5f514c 100644
--- a/arch/arm/boot/dts/uniphier-ld4.dtsi
+++ b/arch/arm/boot/dts/uniphier-ld4.dtsi
@@ -207,7 +207,7 @@ smpctrl@59801000 {
reg = <0x59801000 0x400>;
};
- mioctrl@59810000 {
+ mioctrl: mioctrl@59810000 {
compatible = "socionext,uniphier-ld4-mioctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x800>;
@@ -272,6 +272,7 @@ sd: mmc@5a400000 {
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
+ socionext,syscon-uhs-mode = <&mioctrl 0>;
};
emmc: mmc@5a500000 {
diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi
index a309e64c57c8..2c7434574bc6 100644
--- a/arch/arm/boot/dts/uniphier-pro4.dtsi
+++ b/arch/arm/boot/dts/uniphier-pro4.dtsi
@@ -241,7 +241,7 @@ smpctrl@59801000 {
reg = <0x59801000 0x400>;
};
- mioctrl@59810000 {
+ mioctrl: mioctrl@59810000 {
compatible = "socionext,uniphier-pro4-mioctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x800>;
@@ -307,6 +307,7 @@ sd: mmc@5a400000 {
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
+ socionext,syscon-uhs-mode = <&mioctrl 0>;
};
emmc: mmc@5a500000 {
diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi
index 100edd7438d8..2ac78c3ebd17 100644
--- a/arch/arm/boot/dts/uniphier-pro5.dtsi
+++ b/arch/arm/boot/dts/uniphier-pro5.dtsi
@@ -341,7 +341,7 @@ smpctrl@59801000 {
reg = <0x59801000 0x400>;
};
- sdctrl@59810000 {
+ sdctrl: sdctrl@59810000 {
compatible = "socionext,uniphier-pro5-sdctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x400>;
@@ -696,6 +696,7 @@ sd: mmc@68800000 {
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
+ socionext,syscon-uhs-mode = <&sdctrl 0>;
};
};
};
diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi
index ca4dccf56a67..13331eb1caa3 100644
--- a/arch/arm/boot/dts/uniphier-pxs2.dtsi
+++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi
@@ -422,7 +422,7 @@ smpctrl@59801000 {
reg = <0x59801000 0x400>;
};
- sdctrl@59810000 {
+ sdctrl: sdctrl@59810000 {
compatible = "socionext,uniphier-pxs2-sdctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x400>;
@@ -486,6 +486,7 @@ sd: mmc@5a400000 {
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
+ socionext,syscon-uhs-mode = <&sdctrl 0>;
};
soc_glue: soc-glue@5f800000 {
diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi
index 67b12dfe513b..af7488e2eb16 100644
--- a/arch/arm/boot/dts/uniphier-sld8.dtsi
+++ b/arch/arm/boot/dts/uniphier-sld8.dtsi
@@ -211,7 +211,7 @@ smpctrl@59801000 {
reg = <0x59801000 0x400>;
};
- mioctrl@59810000 {
+ mioctrl: mioctrl@59810000 {
compatible = "socionext,uniphier-sld8-mioctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x800>;
@@ -276,6 +276,7 @@ sd: mmc@5a400000 {
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
+ socionext,syscon-uhs-mode = <&mioctrl 0>;
};
emmc: mmc@5a500000 {
--
2.25.1
Transition of UHS mode needs to control the register in SD interface
logic. Add access to the register in the logic using the regmap from
"socionext,syscon-uhs-mode" property.
Define the start_signal_voltage_switch function only if UHS mode is
available.
Signed-off-by: Kunihiko Hayashi <[email protected]>
---
drivers/mmc/host/uniphier-sd.c | 61 +++++++++++++++++++++++++++++++---
1 file changed, 56 insertions(+), 5 deletions(-)
diff --git a/drivers/mmc/host/uniphier-sd.c b/drivers/mmc/host/uniphier-sd.c
index 3a8defdcca77..c9766d6a690f 100644
--- a/drivers/mmc/host/uniphier-sd.c
+++ b/drivers/mmc/host/uniphier-sd.c
@@ -8,6 +8,7 @@
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
+#include <linux/mfd/syscon.h>
#include <linux/mfd/tmio.h>
#include <linux/mmc/host.h>
#include <linux/module.h>
@@ -15,6 +16,7 @@
#include <linux/of_device.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
+#include <linux/regmap.h>
#include <linux/reset.h>
#include "tmio_mmc.h"
@@ -48,6 +50,11 @@
#define UNIPHIER_SD_DMA_ADDR_L 0x440
#define UNIPHIER_SD_DMA_ADDR_H 0x444
+/* SD control */
+#define UNIPHIER_SDCTRL_CHOFFSET 0x200
+#define UNIPHIER_SDCTRL_MODE 0x30
+#define UNIPHIER_SDCTRL_MODE_UHS1MOD BIT(15)
+
/*
* IP is extended to support various features: built-in DMA engine,
* 1/1024 divisor, etc.
@@ -66,6 +73,8 @@ struct uniphier_sd_priv {
struct reset_control *rst_hw;
struct dma_chan *chan;
enum dma_data_direction dma_dir;
+ struct regmap *sdctrl_regmap;
+ u32 sdctrl_ch;
unsigned long clk_rate;
unsigned long caps;
};
@@ -420,6 +429,23 @@ static void uniphier_sd_hw_reset(struct mmc_host *mmc)
usleep_range(300, 1000);
}
+static void uniphier_sd_uhs_enable(struct tmio_mmc_host *host, bool uhs_en)
+{
+ struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
+ unsigned int offset;
+ u32 val;
+
+ if (!(host->mmc->caps & MMC_CAP_UHS))
+ return;
+
+ val = (uhs_en) ? UNIPHIER_SDCTRL_MODE_UHS1MOD : 0;
+
+ offset = UNIPHIER_SDCTRL_CHOFFSET * priv->sdctrl_ch
+ + UNIPHIER_SDCTRL_MODE;
+ regmap_write_bits(priv->sdctrl_regmap, offset,
+ UNIPHIER_SDCTRL_MODE_UHS1MOD, val);
+}
+
static void uniphier_sd_set_clock(struct tmio_mmc_host *host,
unsigned int clock)
{
@@ -500,14 +526,17 @@ static int uniphier_sd_start_signal_voltage_switch(struct mmc_host *mmc,
struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
struct pinctrl_state *pinstate = NULL;
u32 val, tmp;
+ bool uhs_en;
switch (ios->signal_voltage) {
case MMC_SIGNAL_VOLTAGE_330:
val = UNIPHIER_SD_VOLT_330;
+ uhs_en = false;
break;
case MMC_SIGNAL_VOLTAGE_180:
val = UNIPHIER_SD_VOLT_180;
pinstate = priv->pinstate_uhs;
+ uhs_en = true;
break;
default:
return -ENOTSUPP;
@@ -523,12 +552,19 @@ static int uniphier_sd_start_signal_voltage_switch(struct mmc_host *mmc,
else
pinctrl_select_default_state(mmc_dev(mmc));
+ uniphier_sd_uhs_enable(host, uhs_en);
+
return 0;
}
-static int uniphier_sd_uhs_init(struct tmio_mmc_host *host,
- struct uniphier_sd_priv *priv)
+static int uniphier_sd_uhs_init(struct tmio_mmc_host *host)
{
+ struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
+ struct device *dev = &host->pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct of_phandle_args args;
+ int ret;
+
priv->pinctrl = devm_pinctrl_get(mmc_dev(host->mmc));
if (IS_ERR(priv->pinctrl))
return PTR_ERR(priv->pinctrl);
@@ -537,8 +573,20 @@ static int uniphier_sd_uhs_init(struct tmio_mmc_host *host,
if (IS_ERR(priv->pinstate_uhs))
return PTR_ERR(priv->pinstate_uhs);
- host->ops.start_signal_voltage_switch =
- uniphier_sd_start_signal_voltage_switch;
+ ret = of_parse_phandle_with_fixed_args(np,
+ "socionext,syscon-uhs-mode",
+ 1, 0, &args);
+ if (ret) {
+ dev_err(dev, "Can't get syscon-uhs-mode property\n");
+ return ret;
+ }
+ priv->sdctrl_regmap = syscon_node_to_regmap(args.np);
+ of_node_put(args.np);
+ if (IS_ERR(priv->sdctrl_regmap)) {
+ dev_err(dev, "Can't map syscon-uhs-mode\n");
+ return PTR_ERR(priv->sdctrl_regmap);
+ }
+ priv->sdctrl_ch = args.args[0];
return 0;
}
@@ -601,12 +649,15 @@ static int uniphier_sd_probe(struct platform_device *pdev)
}
if (host->mmc->caps & MMC_CAP_UHS) {
- ret = uniphier_sd_uhs_init(host, priv);
+ ret = uniphier_sd_uhs_init(host);
if (ret) {
dev_warn(dev,
"failed to setup UHS (error %d). Disabling UHS.",
ret);
host->mmc->caps &= ~MMC_CAP_UHS;
+ } else {
+ host->ops.start_signal_voltage_switch =
+ uniphier_sd_start_signal_voltage_switch;
}
}
--
2.25.1
Add sociopnext,syscon-uhs-mode prpperty to the SD node to refer the handle
of the control logic node.
Signed-off-by: Kunihiko Hayashi <[email protected]>
---
arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 3 ++-
arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
index 9308458f9611..687a29c9d459 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
@@ -548,7 +548,7 @@ smpctrl@59801000 {
reg = <0x59801000 0x400>;
};
- sdctrl@59810000 {
+ sdctrl: sdctrl@59810000 {
compatible = "socionext,uniphier-ld20-sdctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x400>;
@@ -611,6 +611,7 @@ sd: mmc@5a400000 {
resets = <&sd_rst 0>;
bus-width = <4>;
cap-sd-highspeed;
+ socionext,syscon-uhs-mode = <&sdctrl 0>;
};
soc_glue: soc-glue@5f800000 {
diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
index b0c29510a7da..4c18f54abb15 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
@@ -370,7 +370,7 @@ smpctrl@59801000 {
reg = <0x59801000 0x400>;
};
- sdctrl@59810000 {
+ sdctrl: sdctrl@59810000 {
compatible = "socionext,uniphier-pxs3-sdctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x400>;
@@ -437,6 +437,7 @@ sd: mmc@5a400000 {
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
+ socionext,syscon-uhs-mode = <&sdctrl 0>;
};
soc_glue: soc-glue@5f800000 {
--
2.25.1
On 25/01/2023 02:01, Kunihiko Hayashi wrote:
> UHS mode control is included in the interface logic represented
> by syscon. To refer this, add new property "socionext,syscon-uhs-mode".
>
> Signed-off-by: Kunihiko Hayashi <[email protected]>
> ---
> .../devicetree/bindings/mmc/socionext,uniphier-sd.yaml | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mmc/socionext,uniphier-sd.yaml b/Documentation/devicetree/bindings/mmc/socionext,uniphier-sd.yaml
> index a586fad0a46b..313621d0d9f5 100644
> --- a/Documentation/devicetree/bindings/mmc/socionext,uniphier-sd.yaml
> +++ b/Documentation/devicetree/bindings/mmc/socionext,uniphier-sd.yaml
> @@ -55,6 +55,16 @@ properties:
> minItems: 1
> maxItems: 3
>
> + socionext,syscon-uhs-mode:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + items:
> + - items:
> + - description: phandle to syscon that configures uhs mode
s/uhs/UHS/
> + - description: ID of SD instance
> + description:
> + A phandle to syscon with one argument that configures uhs mode.
s/uhs/UHS/
Acked-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On Wed, 25 Jan 2023 at 02:02, Kunihiko Hayashi
<[email protected]> wrote:
>
> The uniphier-sd controller needs to control some siginals from the SD
> interface logic to transition to UHS mode.
>
> This series adds UHS mode support to the controller driver
> to refer to and control the interface logic registers, which include
> mode selector and SDR speed selector.
>
> Kunihiko Hayashi (5):
> dt-bindings: mmc: uniphier-sd: Add socionext,syscon-uhs-mode property
> mmc: uniphier-sd: Add control of UHS mode using SD interface logic
> mmc: uniphier-sd: Add control to switch UHS speed
> ARM: dts: uniphier: Add syscon-uhs-mode to SD node
> arm64: dts: uniphier: Add syscon-uhs-mode to SD node
>
> .../bindings/mmc/socionext,uniphier-sd.yaml | 10 +++
> arch/arm/boot/dts/uniphier-ld4.dtsi | 3 +-
> arch/arm/boot/dts/uniphier-pro4.dtsi | 3 +-
> arch/arm/boot/dts/uniphier-pro5.dtsi | 3 +-
> arch/arm/boot/dts/uniphier-pxs2.dtsi | 3 +-
> arch/arm/boot/dts/uniphier-sld8.dtsi | 3 +-
> .../boot/dts/socionext/uniphier-ld20.dtsi | 3 +-
> .../boot/dts/socionext/uniphier-pxs3.dtsi | 3 +-
> drivers/mmc/host/uniphier-sd.c | 83 +++++++++++++++++--
> 9 files changed, 102 insertions(+), 12 deletions(-)
>
Patch 1 to 3 applied for next (I fixed up the comments from Krzysztof
when I applied), thanks!
Kind regards
Uffe
Hi Ulf,
On 2023/01/27 19:57, Ulf Hansson wrote:
> On Wed, 25 Jan 2023 at 02:02, Kunihiko Hayashi
> <[email protected]> wrote:
>>
>> The uniphier-sd controller needs to control some siginals from the SD
>> interface logic to transition to UHS mode.
>>
>> This series adds UHS mode support to the controller driver
>> to refer to and control the interface logic registers, which include
>> mode selector and SDR speed selector.
>>
>> Kunihiko Hayashi (5):
>> dt-bindings: mmc: uniphier-sd: Add socionext,syscon-uhs-mode property
>> mmc: uniphier-sd: Add control of UHS mode using SD interface logic
>> mmc: uniphier-sd: Add control to switch UHS speed
>> ARM: dts: uniphier: Add syscon-uhs-mode to SD node
>> arm64: dts: uniphier: Add syscon-uhs-mode to SD node
>>
>> .../bindings/mmc/socionext,uniphier-sd.yaml | 10 +++
>> arch/arm/boot/dts/uniphier-ld4.dtsi | 3 +-
>> arch/arm/boot/dts/uniphier-pro4.dtsi | 3 +-
>> arch/arm/boot/dts/uniphier-pro5.dtsi | 3 +-
>> arch/arm/boot/dts/uniphier-pxs2.dtsi | 3 +-
>> arch/arm/boot/dts/uniphier-sld8.dtsi | 3 +-
>> .../boot/dts/socionext/uniphier-ld20.dtsi | 3 +-
>> .../boot/dts/socionext/uniphier-pxs3.dtsi | 3 +-
>> drivers/mmc/host/uniphier-sd.c | 83 +++++++++++++++++--
>> 9 files changed, 102 insertions(+), 12 deletions(-)
>>
>
> Patch 1 to 3 applied for next (I fixed up the comments from Krzysztof
> when I applied), thanks!
Thank you for fixing up and applying. I'll send patch 4 and 5 (related to
the devicetree sources) as other requests for the SoC.
Thank you,
---
Best Regards
Kunihiko Hayashi