From: Nick Hawkins <[email protected]>
Document compatibility string to support I2C controller
in GXP.
Signed-off-by: Nick Hawkins <[email protected]>
---
v4:
*Provide even greater description with the use
of Phandle
*Reorder properties so they match the required
order
v3:
*Provide better description with use of Phandle
v2:
*Removed uneccessary size-cells and address-cells
*Removed phandle from hpe,sysreg-phandle
*Changed hpe,i2c-max-bus-freq to clock-frequency
---
.../devicetree/bindings/i2c/hpe,gxp-i2c.yaml | 59 +++++++++++++++++++
1 file changed, 59 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i2c/hpe,gxp-i2c.yaml
diff --git a/Documentation/devicetree/bindings/i2c/hpe,gxp-i2c.yaml b/Documentation/devicetree/bindings/i2c/hpe,gxp-i2c.yaml
new file mode 100644
index 000000000000..6604dcd47251
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/hpe,gxp-i2c.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/hpe,gxp-i2c.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: HPE GXP SoC I2C Controller
+
+maintainers:
+ - Nick Hawkins <[email protected]>
+
+allOf:
+ - $ref: /schemas/i2c/i2c-controller.yaml#
+
+properties:
+ compatible:
+ const: hpe,gxp-i2c
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clock-frequency:
+ default: 100000
+
+ hpe,sysreg:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the global status and enable interrupt registers shared
+ between each I2C engine controller instance. It enables the I2C
+ engine controller to act as both a master or slave by being able to
+ arm and respond to interrupts from its engine. Each bit in the
+ registers represent the respective bit position.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ i2c@2600 {
+ compatible = "hpe,gxp-i2c";
+ reg = <0x2500 0x70>;
+ interrupts = <9>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ hpe,sysreg = <&sysreg_system_controller>;
+ clock-frequency = <10000>;
+
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
+ };
--
2.17.1
On Wed, Jan 25, 2023 at 12:44:35PM -0600, [email protected] wrote:
> From: Nick Hawkins <[email protected]>
>
> Document compatibility string to support I2C controller
> in GXP.
>
> Signed-off-by: Nick Hawkins <[email protected]>
>
> ---
> v4:
> *Provide even greater description with the use
> of Phandle
> *Reorder properties so they match the required
> order
> v3:
> *Provide better description with use of Phandle
> v2:
> *Removed uneccessary size-cells and address-cells
> *Removed phandle from hpe,sysreg-phandle
> *Changed hpe,i2c-max-bus-freq to clock-frequency
> ---
> .../devicetree/bindings/i2c/hpe,gxp-i2c.yaml | 59 +++++++++++++++++++
> 1 file changed, 59 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/i2c/hpe,gxp-i2c.yaml
>
> diff --git a/Documentation/devicetree/bindings/i2c/hpe,gxp-i2c.yaml b/Documentation/devicetree/bindings/i2c/hpe,gxp-i2c.yaml
> new file mode 100644
> index 000000000000..6604dcd47251
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/i2c/hpe,gxp-i2c.yaml
> @@ -0,0 +1,59 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/i2c/hpe,gxp-i2c.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: HPE GXP SoC I2C Controller
> +
> +maintainers:
> + - Nick Hawkins <[email protected]>
> +
> +allOf:
> + - $ref: /schemas/i2c/i2c-controller.yaml#
> +
> +properties:
> + compatible:
> + const: hpe,gxp-i2c
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + clock-frequency:
> + default: 100000
> +
> + hpe,sysreg:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + Phandle to the global status and enable interrupt registers shared
> + between each I2C engine controller instance. It enables the I2C
> + engine controller to act as both a master or slave by being able to
> + arm and respond to interrupts from its engine. Each bit in the
> + registers represent the respective bit position.
Each bit represents the bit position?
AIUI, each I2C instance has a bit in it needs to control. How does the
driver know what instance (and therefore the correct bit)? Typically you
would have a 2nd cell here with that information.
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + i2c@2600 {
> + compatible = "hpe,gxp-i2c";
> + reg = <0x2500 0x70>;
> + interrupts = <9>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + hpe,sysreg = <&sysreg_system_controller>;
> + clock-frequency = <10000>;
> +
> + eeprom@50 {
> + compatible = "atmel,24c128";
> + reg = <0x50>;
> + };
> + };
> --
> 2.17.1
>
> > + hpe,sysreg:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + description:
> > + Phandle to the global status and enable interrupt registers shared
> > + between each I2C engine controller instance. It enables the I2C
> > + engine controller to act as both a master or slave by being able to
> > + arm and respond to interrupts from its engine. Each bit in the
> > + registers represent the respective bit position.
> Each bit represents the bit position?
Yes what I mean here is that bit 0 represents engine 0, bit 1 represents
engine 1 and so on. I will reword this how you have below.
> AIUI, each I2C instance has a bit in it needs to control. How does the
> driver know what instance (and therefore the correct bit)? Typically you
> would have a 2nd cell here with that information.
We are currently using the memory area designated reg to determine
which engine we are on.
Here is a snippet from patch 1 of this patchset that introduces the driver:
/* Use physical memory address to determine which I2C engine this is. */
+ drvdata->engine = ((u32)drvdata->base & 0xf00) >> 8;
This works because each engine is 0x100 apart.
I would however like to conform to a standard to designate the engine.
Is there an existing property I can leverage?
Thanks for your feedback,
-Nick Hawkins
On Wed, Jan 25, 2023 at 3:32 PM Hawkins, Nick <[email protected]> wrote:
>
> > > + hpe,sysreg:
> > > + $ref: /schemas/types.yaml#/definitions/phandle
> > > + description:
> > > + Phandle to the global status and enable interrupt registers shared
> > > + between each I2C engine controller instance. It enables the I2C
> > > + engine controller to act as both a master or slave by being able to
> > > + arm and respond to interrupts from its engine. Each bit in the
> > > + registers represent the respective bit position.
>
>
> > Each bit represents the bit position?
>
> Yes what I mean here is that bit 0 represents engine 0, bit 1 represents
> engine 1 and so on. I will reword this how you have below.
>
> > AIUI, each I2C instance has a bit in it needs to control. How does the
> > driver know what instance (and therefore the correct bit)? Typically you
> > would have a 2nd cell here with that information.
>
> We are currently using the memory area designated reg to determine
> which engine we are on.
>
> Here is a snippet from patch 1 of this patchset that introduces the driver:
> /* Use physical memory address to determine which I2C engine this is. */
> + drvdata->engine = ((u32)drvdata->base & 0xf00) >> 8;
>
> This works because each engine is 0x100 apart.
Ah, that works fine then.
Reviewed-by: Rob Herring <[email protected]>