From: Nick Hawkins <[email protected]>
The GXP SoC has a large range of registers. This patch will expand the
registers available to SoC by modifying its device tree file. Initially
this change was planned to be part of a larger set but feedback
indicated it should be submitted separately. In the device tree file
there is a large gap in the ranges of registers available because they
are reserved.
Nick Hawkins (1):
ARM: dts: hpe: Correct GXP register ranges
arch/arm/boot/dts/hpe-gxp.dtsi | 41 +++++++++++++++++-----------------
1 file changed, 20 insertions(+), 21 deletions(-)
--
2.17.1
From: Nick Hawkins <[email protected]>
Correct memory ranges on GXP to include host registers. This corrects a
issue where the host interrupt controller is not available. Additionally
there is a large gap of reserved registers that will not be used. To avoid
this area two ranges are used.
Signed-off-by: Nick Hawkins <[email protected]>
---
arch/arm/boot/dts/hpe-gxp.dtsi | 41 +++++++++++++++++-----------------
1 file changed, 20 insertions(+), 21 deletions(-)
diff --git a/arch/arm/boot/dts/hpe-gxp.dtsi b/arch/arm/boot/dts/hpe-gxp.dtsi
index cf735b3c4f35..30ed921f83ac 100644
--- a/arch/arm/boot/dts/hpe-gxp.dtsi
+++ b/arch/arm/boot/dts/hpe-gxp.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Device Tree file for HPE GXP
+ * Device Tree for HPE
*/
/dts-v1/;
@@ -43,7 +43,6 @@
#address-cells = <1>;
#size-cells = <1>;
ranges;
- dma-ranges;
L2: cache-controller@b0040000 {
compatible = "arm,pl310-cache";
@@ -52,73 +51,73 @@
cache-level = <2>;
};
- ahb@c0000000 {
+ ahb@80000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0x0 0xc0000000 0x30000000>;
- dma-ranges;
+ ranges = <0x0 0x80000000 0x20000000>,
+ <0x40000000 0xc0000000 0x3fff0000>;
- vic0: interrupt-controller@eff0000 {
+ vic0: interrupt-controller@4eff0000 {
compatible = "arm,pl192-vic";
- reg = <0xeff0000 0x1000>;
+ reg = <0x4eff0000 0x1000>;
interrupt-controller;
#interrupt-cells = <1>;
};
- vic1: interrupt-controller@80f00000 {
+ vic1: interrupt-controller@f00000 {
compatible = "arm,pl192-vic";
- reg = <0x80f00000 0x1000>;
+ reg = <0xf00000 0x1000>;
interrupt-controller;
#interrupt-cells = <1>;
};
- uarta: serial@e0 {
+ uarta: serial@400000e0 {
compatible = "ns16550a";
- reg = <0xe0 0x8>;
+ reg = <0x400000e0 0x8>;
interrupts = <17>;
interrupt-parent = <&vic0>;
clock-frequency = <1846153>;
reg-shift = <0>;
};
- uartb: serial@e8 {
+ uartb: serial@400000e8 {
compatible = "ns16550a";
- reg = <0xe8 0x8>;
+ reg = <0x400000e8 0x8>;
interrupts = <18>;
interrupt-parent = <&vic0>;
clock-frequency = <1846153>;
reg-shift = <0>;
};
- uartc: serial@f0 {
+ uartc: serial@400000f0 {
compatible = "ns16550a";
- reg = <0xf0 0x8>;
+ reg = <0x400000f0 0x8>;
interrupts = <19>;
interrupt-parent = <&vic0>;
clock-frequency = <1846153>;
reg-shift = <0>;
};
- usb0: usb@efe0000 {
+ usb0: usb@4efe0000 {
compatible = "hpe,gxp-ehci", "generic-ehci";
- reg = <0xefe0000 0x100>;
+ reg = <0x4efe0000 0x100>;
interrupts = <7>;
interrupt-parent = <&vic0>;
};
- st: timer@80 {
+ st: timer@40000080 {
compatible = "hpe,gxp-timer";
- reg = <0x80 0x16>;
+ reg = <0x40000080 0x16>;
interrupts = <0>;
interrupt-parent = <&vic0>;
clocks = <&iopclk>;
clock-names = "iop";
};
- usb1: usb@efe0100 {
+ usb1: usb@4efe0100 {
compatible = "hpe,gxp-ohci", "generic-ohci";
- reg = <0xefe0100 0x110>;
+ reg = <0x4efe0100 0x110>;
interrupts = <6>;
interrupt-parent = <&vic0>;
};
--
2.17.1