Changes in v3:
- Added commit to export register/unregister/parse FHCTL functions
to allow building clock drivers using FHCTL as modules
Changes in v2:
- Rebased over v4 of my clock drivers cleanups series [1]
This series adds support for Frequency Hopping (FHCTL) on more MediaTek
SoCs, specifically, MT6795, MT8173, MT8192 and MT8195.
In order to support older platforms like MT6795 and MT8173 it was
necessary to add a new register layout that is ever-so-slightly
different from the one that was previously introduced for MT8186.
Since the new layout refers to older SoCs, the one valid for MT8186
and newer SoCs was renamed to be a "v2" layout, while the new one
for older chips gets the "v1" name.
Note: These commits won't change any behavior unless FHCTL gets
explicitly enabled and configured in devicetrees.
[1]: https://patchwork.kernel.org/project/linux-mediatek/list/?series=714059
AngeloGioacchino Del Regno (7):
clk: mediatek: fhctl: Add support for older fhctl register layout
clk: mediatek: clk-pllfh: Export register/unregister/parse functions
dt-bindings: clock: mediatek,mt8186-fhctl: Support MT6795,
MT8173/92/95
clk: mediatek: mt6795: Add support for frequency hopping through FHCTL
clk: mediatek: mt8173: Add support for frequency hopping through FHCTL
clk: mediatek: mt8192: Add support for frequency hopping through FHCTL
clk: mediatek: mt8195: Add support for frequency hopping through FHCTL
.../bindings/clock/mediatek,mt8186-fhctl.yaml | 7 +-
drivers/clk/mediatek/clk-fhctl.c | 26 ++++++-
drivers/clk/mediatek/clk-fhctl.h | 9 ++-
drivers/clk/mediatek/clk-mt6795-apmixedsys.c | 63 ++++++++++++++++-
drivers/clk/mediatek/clk-mt8173-apmixedsys.c | 65 ++++++++++++++++-
drivers/clk/mediatek/clk-mt8186-apmixedsys.c | 2 +
drivers/clk/mediatek/clk-mt8192.c | 67 +++++++++++++++++-
drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 69 ++++++++++++++++++-
drivers/clk/mediatek/clk-pllfh.c | 26 +++++--
drivers/clk/mediatek/clk-pllfh.h | 1 +
10 files changed, 314 insertions(+), 21 deletions(-)
--
2.39.1
Add FHCTL parameters and register PLLs through FHCTL to add support
for frequency hopping and SSC. FHCTL will be enabled only on PLLs
specified in devicetree.
This commit brings functional changes only upon addition of
devicetree configuration.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
---
drivers/clk/mediatek/clk-mt6795-apmixedsys.c | 63 +++++++++++++++++++-
1 file changed, 60 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt6795-apmixedsys.c b/drivers/clk/mediatek/clk-mt6795-apmixedsys.c
index 59761c72d3bc..03fa30527868 100644
--- a/drivers/clk/mediatek/clk-mt6795-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt6795-apmixedsys.c
@@ -7,8 +7,10 @@
#include <dt-bindings/clock/mediatek,mt6795-clk.h>
#include <linux/module.h>
#include <linux/platform_device.h>
+#include "clk-fhctl.h"
#include "clk-mtk.h"
#include "clk-pll.h"
+#include "clk-pllfh.h"
#define REG_REF2USB 0x8
#define REG_AP_PLL_CON7 0x1c
@@ -58,6 +60,56 @@ static const struct mtk_pll_data plls[] = {
PLL(CLK_APMIXED_APLL2, "apll2", 0x2b4, 0x2c4, 0, 0, 31, 0x2b4, 4, 0x2bc, 0x2b8, 0),
};
+enum fh_pll_id {
+ FH_CA53PLL_LL,
+ FH_CA53PLL_BL,
+ FH_MAINPLL,
+ FH_MPLL,
+ FH_MSDCPLL,
+ FH_MMPLL,
+ FH_VENCPLL,
+ FH_TVDPLL,
+ FH_VCODECPLL,
+ FH_NR_FH,
+};
+
+#define _FH(_pllid, _fhid, _slope, _offset) { \
+ .data = { \
+ .pll_id = _pllid, \
+ .fh_id = _fhid, \
+ .fh_ver = FHCTL_PLLFH_V1, \
+ .fhx_offset = _offset, \
+ .dds_mask = GENMASK(21, 0), \
+ .slope0_value = _slope, \
+ .slope1_value = _slope, \
+ .sfstrx_en = BIT(2), \
+ .frddsx_en = BIT(1), \
+ .fhctlx_en = BIT(0), \
+ .tgl_org = BIT(31), \
+ .dvfs_tri = BIT(31), \
+ .pcwchg = BIT(31), \
+ .dt_val = 0x0, \
+ .df_val = 0x9, \
+ .updnlmt_shft = 16, \
+ .msk_frddsx_dys = GENMASK(23, 20), \
+ .msk_frddsx_dts = GENMASK(19, 16), \
+ }, \
+ }
+
+#define FH(_pllid, _fhid, _offset) _FH(_pllid, _fhid, 0x6003c97, _offset)
+#define FH_M(_pllid, _fhid, _offset) _FH(_pllid, _fhid, 0x6000140, _offset)
+
+static struct mtk_pllfh_data pllfhs[] = {
+ FH(CLK_APMIXED_ARMCA53PLL, FH_CA53PLL_BL, 0x38),
+ FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x60),
+ FH_M(CLK_APMIXED_MPLL, FH_MPLL, 0x74),
+ FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x88),
+ FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0x9c),
+ FH(CLK_APMIXED_VENCPLL, FH_VENCPLL, 0xb0),
+ FH(CLK_APMIXED_TVDPLL, FH_TVDPLL, 0xc4),
+ FH(CLK_APMIXED_VCODECPLL, FH_VCODECPLL, 0xd8),
+};
+
static void clk_mt6795_apmixed_setup_md1(void __iomem *base)
{
void __iomem *reg = base + REG_AP_PLL_CON7;
@@ -85,6 +137,7 @@ static int clk_mt6795_apmixed_probe(struct platform_device *pdev)
struct clk_hw_onecell_data *clk_data;
struct device *dev = &pdev->dev;
struct device_node *node = dev->of_node;
+ const u8 *fhctl_node = "mediatek,mt6795-fhctl";
void __iomem *base;
struct clk_hw *hw;
int ret;
@@ -97,7 +150,9 @@ static int clk_mt6795_apmixed_probe(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
- ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+ fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
+ ret = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls),
+ pllfhs, ARRAY_SIZE(pllfhs), clk_data);
if (ret)
goto free_clk_data;
@@ -124,7 +179,8 @@ static int clk_mt6795_apmixed_probe(struct platform_device *pdev)
unregister_ref2usb:
mtk_clk_unregister_ref2usb_tx(clk_data->hws[CLK_APMIXED_REF2USB_TX]);
unregister_plls:
- mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
+ mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
+ ARRAY_SIZE(pllfhs), clk_data);
free_clk_data:
mtk_free_clk_data(clk_data);
return ret;
@@ -137,7 +193,8 @@ static int clk_mt6795_apmixed_remove(struct platform_device *pdev)
of_clk_del_provider(node);
mtk_clk_unregister_ref2usb_tx(clk_data->hws[CLK_APMIXED_REF2USB_TX]);
- mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
+ mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
+ ARRAY_SIZE(pllfhs), clk_data);
mtk_free_clk_data(clk_data);
return 0;
--
2.39.1
Add FHCTL parameters and register PLLs through FHCTL to add support
for frequency hopping and SSC. FHCTL will be enabled only on PLLs
specified in devicetree.
This commit brings functional changes only upon addition of
devicetree configuration.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
---
drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 69 +++++++++++++++++++-
1 file changed, 66 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c
index 1bc917f2667e..c0db31ce0741 100644
--- a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c
@@ -3,9 +3,11 @@
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>
+#include "clk-fhctl.h"
#include "clk-gate.h"
#include "clk-mtk.h"
#include "clk-pll.h"
+#include "clk-pllfh.h"
#include <dt-bindings/clock/mt8195-clk.h>
#include <linux/of_device.h>
@@ -105,6 +107,61 @@ static const struct mtk_pll_data plls[] = {
0, 0, 22, 0x0158, 24, 0, 0, 0, 0x0158, 0, 0x0158, 0, 9),
};
+enum fh_pll_id {
+ FH_ARMPLL_LL,
+ FH_ARMPLL_BL,
+ FH_MEMPLL,
+ FH_ADSPPLL,
+ FH_NNAPLL,
+ FH_CCIPLL,
+ FH_MFGPLL,
+ FH_TVDPLL2,
+ FH_MPLL,
+ FH_MMPLL,
+ FH_MAINPLL,
+ FH_MSDCPLL,
+ FH_IMGPLL,
+ FH_VDECPLL,
+ FH_TVDPLL1,
+ FH_NR_FH,
+};
+
+#define FH(_pllid, _fhid, _offset) { \
+ .data = { \
+ .pll_id = _pllid, \
+ .fh_id = _fhid, \
+ .fh_ver = FHCTL_PLLFH_V2, \
+ .fhx_offset = _offset, \
+ .dds_mask = GENMASK(21, 0), \
+ .slope0_value = 0x6003c97, \
+ .slope1_value = 0x6003c97, \
+ .sfstrx_en = BIT(2), \
+ .frddsx_en = BIT(1), \
+ .fhctlx_en = BIT(0), \
+ .tgl_org = BIT(31), \
+ .dvfs_tri = BIT(31), \
+ .pcwchg = BIT(31), \
+ .dt_val = 0x0, \
+ .df_val = 0x9, \
+ .updnlmt_shft = 16, \
+ .msk_frddsx_dys = GENMASK(23, 20), \
+ .msk_frddsx_dts = GENMASK(19, 16), \
+ }, \
+ }
+
+static struct mtk_pllfh_data pllfhs[] = {
+ FH(CLK_APMIXED_ADSPPLL, FH_ADSPPLL, 0x78),
+ FH(CLK_APMIXED_NNAPLL, FH_NNAPLL, 0x8c),
+ FH(CLK_APMIXED_MFGPLL, FH_MFGPLL, 0xb4),
+ FH(CLK_APMIXED_TVDPLL2, FH_TVDPLL2, 0xc8),
+ FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0xf0),
+ FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x104),
+ FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x118),
+ FH(CLK_APMIXED_IMGPLL, FH_IMGPLL, 0x12c),
+ FH(CLK_APMIXED_VDECPLL, FH_VDECPLL, 0x140),
+ FH(CLK_APMIXED_TVDPLL2, FH_TVDPLL1, 0x154),
+};
+
static const struct of_device_id of_match_clk_mt8195_apmixed[] = {
{ .compatible = "mediatek,mt8195-apmixedsys", },
{}
@@ -114,13 +171,17 @@ static int clk_mt8195_apmixed_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
+ const u8 *fhctl_node = "mediatek,mt8195-fhctl";
int r;
clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
if (!clk_data)
return -ENOMEM;
- r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+ fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
+
+ r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls),
+ pllfhs, ARRAY_SIZE(pllfhs), clk_data);
if (r)
goto free_apmixed_data;
@@ -140,7 +201,8 @@ static int clk_mt8195_apmixed_probe(struct platform_device *pdev)
unregister_gates:
mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
unregister_plls:
- mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
+ mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
+ ARRAY_SIZE(pllfhs), clk_data);
free_apmixed_data:
mtk_free_clk_data(clk_data);
return r;
@@ -153,7 +215,8 @@ static int clk_mt8195_apmixed_remove(struct platform_device *pdev)
of_clk_del_provider(node);
mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
- mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
+ mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
+ ARRAY_SIZE(pllfhs), clk_data);
mtk_free_clk_data(clk_data);
return 0;
--
2.39.1
Add FHCTL parameters and register PLLs through FHCTL to add support
for frequency hopping and SSC. FHCTL will be enabled only on PLLs
specified in devicetree.
This commit brings functional changes only upon addition of
devicetree configuration.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
---
drivers/clk/mediatek/clk-mt8173-apmixedsys.c | 65 +++++++++++++++++++-
1 file changed, 62 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt8173-apmixedsys.c b/drivers/clk/mediatek/clk-mt8173-apmixedsys.c
index a56c5845d07a..0084203e67ad 100644
--- a/drivers/clk/mediatek/clk-mt8173-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt8173-apmixedsys.c
@@ -9,8 +9,10 @@
#include <linux/of_address.h>
#include <linux/module.h>
#include <linux/platform_device.h>
+#include "clk-fhctl.h"
#include "clk-mtk.h"
#include "clk-pll.h"
+#include "clk-pllfh.h"
#define REGOFF_REF2USB 0x8
#define REGOFF_HDMI_REF 0x40
@@ -77,6 +79,58 @@ static const struct mtk_pll_data plls[] = {
PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x2f0, 0x2fc, 0, 0, 21, 0x2f0, 4, 0x0, 0x2f4, 0),
};
+enum fh_pll_id {
+ FH_ARMCA7PLL,
+ FH_ARMCA15PLL,
+ FH_MAINPLL,
+ FH_MPLL,
+ FH_MSDCPLL,
+ FH_MMPLL,
+ FH_VENCPLL,
+ FH_TVDPLL,
+ FH_VCODECPLL,
+ FH_LVDSPLL,
+ FH_MSDC2PLL,
+ FH_NR_FH,
+};
+
+#define FH(_pllid, _fhid, _offset) { \
+ .data = { \
+ .pll_id = _pllid, \
+ .fh_id = _fhid, \
+ .fh_ver = FHCTL_PLLFH_V1, \
+ .fhx_offset = _offset, \
+ .dds_mask = GENMASK(21, 0), \
+ .slope0_value = 0x6003c97, \
+ .slope1_value = 0x6003c97, \
+ .sfstrx_en = BIT(2), \
+ .frddsx_en = BIT(1), \
+ .fhctlx_en = BIT(0), \
+ .tgl_org = BIT(31), \
+ .dvfs_tri = BIT(31), \
+ .pcwchg = BIT(31), \
+ .dt_val = 0x0, \
+ .df_val = 0x9, \
+ .updnlmt_shft = 16, \
+ .msk_frddsx_dys = GENMASK(23, 20), \
+ .msk_frddsx_dts = GENMASK(19, 16), \
+ }, \
+ }
+
+static struct mtk_pllfh_data pllfhs[] = {
+ FH(CLK_APMIXED_ARMCA7PLL, FH_ARMCA7PLL, 0x38),
+ FH(CLK_APMIXED_ARMCA15PLL, FH_ARMCA15PLL, 0x4c),
+ FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x60),
+ FH(CLK_APMIXED_MPLL, FH_MPLL, 0x74),
+ FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x88),
+ FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0x9c),
+ FH(CLK_APMIXED_VENCPLL, FH_VENCPLL, 0xb0),
+ FH(CLK_APMIXED_TVDPLL, FH_TVDPLL, 0xc4),
+ FH(CLK_APMIXED_VCODECPLL, FH_VCODECPLL, 0xd8),
+ FH(CLK_APMIXED_LVDSPLL, FH_LVDSPLL, 0xec),
+ FH(CLK_APMIXED_MSDCPLL2, FH_MSDC2PLL, 0x100),
+};
+
static const struct of_device_id of_match_clk_mt8173_apmixed[] = {
{ .compatible = "mediatek,mt8173-apmixedsys" },
{ /* sentinel */ }
@@ -84,6 +138,7 @@ static const struct of_device_id of_match_clk_mt8173_apmixed[] = {
static int clk_mt8173_apmixed_probe(struct platform_device *pdev)
{
+ const u8 *fhctl_node = "mediatek,mt8173-fhctl";
struct device_node *node = pdev->dev.of_node;
struct clk_hw_onecell_data *clk_data;
void __iomem *base;
@@ -98,7 +153,9 @@ static int clk_mt8173_apmixed_probe(struct platform_device *pdev)
if (IS_ERR_OR_NULL(clk_data))
return -ENOMEM;
- r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+ fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
+ r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls),
+ pllfhs, ARRAY_SIZE(pllfhs), clk_data);
if (r)
goto free_clk_data;
@@ -124,7 +181,8 @@ static int clk_mt8173_apmixed_probe(struct platform_device *pdev)
unregister_ref2usb:
mtk_clk_unregister_ref2usb_tx(clk_data->hws[CLK_APMIXED_REF2USB_TX]);
unregister_plls:
- mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
+ mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
+ ARRAY_SIZE(pllfhs), clk_data);
free_clk_data:
mtk_free_clk_data(clk_data);
return r;
@@ -137,7 +195,8 @@ static int clk_mt8173_apmixed_remove(struct platform_device *pdev)
of_clk_del_provider(node);
mtk_clk_unregister_ref2usb_tx(clk_data->hws[CLK_APMIXED_REF2USB_TX]);
- mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
+ mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
+ ARRAY_SIZE(pllfhs), clk_data);
mtk_free_clk_data(clk_data);
return 0;
--
2.39.1
Add FHCTL parameters and register PLLs through FHCTL to add support
for frequency hopping and SSC. FHCTL will be enabled only on PLLs
specified in devicetree.
This commit brings functional changes only upon addition of
devicetree configuration.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
---
drivers/clk/mediatek/clk-mt8192.c | 67 ++++++++++++++++++++++++++++++-
1 file changed, 65 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-mt8192.c
index 61299960d28a..0f9f10172148 100644
--- a/drivers/clk/mediatek/clk-mt8192.c
+++ b/drivers/clk/mediatek/clk-mt8192.c
@@ -12,10 +12,12 @@
#include <linux/platform_device.h>
#include <linux/slab.h>
+#include "clk-fhctl.h"
#include "clk-gate.h"
#include "clk-mtk.h"
#include "clk-mux.h"
#include "clk-pll.h"
+#include "clk-pllfh.h"
#include <dt-bindings/clock/mt8192-clk.h>
#include <dt-bindings/reset/mt8192-resets.h>
@@ -1042,6 +1044,57 @@ static const struct mtk_pll_data plls[] = {
0, 0, 32, 0x0330, 24, 0, 0, 0, 0x0334, 0),
};
+enum fh_pll_id {
+ FH_ARMPLL_LL,
+ FH_ARMPLL_BL0,
+ FH_ARMPLL_BL1,
+ FH_ARMPLL_BL2,
+ FH_ARMPLL_BL3,
+ FH_CCIPLL,
+ FH_MFGPLL,
+ FH_MEMPLL,
+ FH_MPLL,
+ FH_MMPLL,
+ FH_MAINPLL,
+ FH_MSDCPLL,
+ FH_ADSPPLL,
+ FH_APUPLL,
+ FH_TVDPLL,
+ FH_NR_FH,
+};
+
+#define FH(_pllid, _fhid, _offset) { \
+ .data = { \
+ .pll_id = _pllid, \
+ .fh_id = _fhid, \
+ .fh_ver = FHCTL_PLLFH_V2, \
+ .fhx_offset = _offset, \
+ .dds_mask = GENMASK(21, 0), \
+ .slope0_value = 0x6003c97, \
+ .slope1_value = 0x6003c97, \
+ .sfstrx_en = BIT(2), \
+ .frddsx_en = BIT(1), \
+ .fhctlx_en = BIT(0), \
+ .tgl_org = BIT(31), \
+ .dvfs_tri = BIT(31), \
+ .pcwchg = BIT(31), \
+ .dt_val = 0x0, \
+ .df_val = 0x9, \
+ .updnlmt_shft = 16, \
+ .msk_frddsx_dys = GENMASK(23, 20), \
+ .msk_frddsx_dts = GENMASK(19, 16), \
+ }, \
+ }
+
+static struct mtk_pllfh_data pllfhs[] = {
+ FH(CLK_APMIXED_MFGPLL, FH_MFGPLL, 0xb4),
+ FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0xf0),
+ FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x104),
+ FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x118),
+ FH(CLK_APMIXED_ADSPPLL, FH_ADSPPLL, 0x12c),
+ FH(CLK_APMIXED_TVDPLL, FH_TVDPLL, 0x154),
+};
+
/* Register mux notifier for MFG mux */
static int clk_mt8192_reg_mfg_mux_notifier(struct device *dev, struct clk *clk)
{
@@ -1068,17 +1121,24 @@ static int clk_mt8192_apmixed_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
+ const u8 *fhctl_node = "mediatek,mt8192-fhctl";
int r;
clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
if (!clk_data)
return -ENOMEM;
- mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+ fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
+
+ r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls),
+ pllfhs, ARRAY_SIZE(pllfhs), clk_data);
+ if (r)
+ goto free_clk_data;
+
r = mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
ARRAY_SIZE(apmixed_clks), clk_data);
if (r)
- goto free_clk_data;
+ goto unregister_plls;
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
@@ -1088,6 +1148,9 @@ static int clk_mt8192_apmixed_probe(struct platform_device *pdev)
unregister_gates:
mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
+unregister_plls:
+ mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
+ ARRAY_SIZE(pllfhs), clk_data);
free_clk_data:
mtk_free_clk_data(clk_data);
return r;
--
2.39.1
On Mon, Feb 6, 2023 at 6:01 PM AngeloGioacchino Del Regno
<[email protected]> wrote:
>
> Add FHCTL parameters and register PLLs through FHCTL to add support
> for frequency hopping and SSC. FHCTL will be enabled only on PLLs
> specified in devicetree.
>
> This commit brings functional changes only upon addition of
> devicetree configuration.
>
> Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
> ---
> drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 69 +++++++++++++++++++-
> 1 file changed, 66 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c
> index 1bc917f2667e..c0db31ce0741 100644
> --- a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c
> +++ b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c
> @@ -3,9 +3,11 @@
> // Copyright (c) 2021 MediaTek Inc.
> // Author: Chun-Jie Chen <[email protected]>
>
> +#include "clk-fhctl.h"
> #include "clk-gate.h"
> #include "clk-mtk.h"
> #include "clk-pll.h"
> +#include "clk-pllfh.h"
>
> #include <dt-bindings/clock/mt8195-clk.h>
> #include <linux/of_device.h>
> @@ -105,6 +107,61 @@ static const struct mtk_pll_data plls[] = {
> 0, 0, 22, 0x0158, 24, 0, 0, 0, 0x0158, 0, 0x0158, 0, 9),
> };
>
> +enum fh_pll_id {
> + FH_ARMPLL_LL,
> + FH_ARMPLL_BL,
> + FH_MEMPLL,
> + FH_ADSPPLL,
> + FH_NNAPLL,
> + FH_CCIPLL,
> + FH_MFGPLL,
> + FH_TVDPLL2,
> + FH_MPLL,
> + FH_MMPLL,
> + FH_MAINPLL,
> + FH_MSDCPLL,
> + FH_IMGPLL,
> + FH_VDECPLL,
> + FH_TVDPLL1,
> + FH_NR_FH,
> +};
> +
> +#define FH(_pllid, _fhid, _offset) { \
> + .data = { \
> + .pll_id = _pllid, \
> + .fh_id = _fhid, \
> + .fh_ver = FHCTL_PLLFH_V2, \
> + .fhx_offset = _offset, \
> + .dds_mask = GENMASK(21, 0), \
> + .slope0_value = 0x6003c97, \
> + .slope1_value = 0x6003c97, \
Are these
> + .sfstrx_en = BIT(2), \
> + .frddsx_en = BIT(1), \
> + .fhctlx_en = BIT(0), \
> + .tgl_org = BIT(31), \
> + .dvfs_tri = BIT(31), \
> + .pcwchg = BIT(31), \
> + .dt_val = 0x0, \
> + .df_val = 0x9, \
and these just copied from MT8186?
> + .updnlmt_shft = 16, \
> + .msk_frddsx_dys = GENMASK(23, 20), \
> + .msk_frddsx_dts = GENMASK(19, 16), \
> + }, \
> + }
> +
> +static struct mtk_pllfh_data pllfhs[] = {
> + FH(CLK_APMIXED_ADSPPLL, FH_ADSPPLL, 0x78),
> + FH(CLK_APMIXED_NNAPLL, FH_NNAPLL, 0x8c),
> + FH(CLK_APMIXED_MFGPLL, FH_MFGPLL, 0xb4),
> + FH(CLK_APMIXED_TVDPLL2, FH_TVDPLL2, 0xc8),
> + FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0xf0),
> + FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x104),
> + FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x118),
> + FH(CLK_APMIXED_IMGPLL, FH_IMGPLL, 0x12c),
> + FH(CLK_APMIXED_VDECPLL, FH_VDECPLL, 0x140),
> + FH(CLK_APMIXED_TVDPLL2, FH_TVDPLL1, 0x154),
> +};
> +
> static const struct of_device_id of_match_clk_mt8195_apmixed[] = {
> { .compatible = "mediatek,mt8195-apmixedsys", },
> {}
> @@ -114,13 +171,17 @@ static int clk_mt8195_apmixed_probe(struct platform_device *pdev)
> {
> struct clk_hw_onecell_data *clk_data;
> struct device_node *node = pdev->dev.of_node;
> + const u8 *fhctl_node = "mediatek,mt8195-fhctl";
> int r;
>
> clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
> if (!clk_data)
> return -ENOMEM;
>
> - r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
> + fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
> +
> + r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls),
> + pllfhs, ARRAY_SIZE(pllfhs), clk_data);
> if (r)
> goto free_apmixed_data;
>
> @@ -140,7 +201,8 @@ static int clk_mt8195_apmixed_probe(struct platform_device *pdev)
> unregister_gates:
> mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
> unregister_plls:
> - mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
> + mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
> + ARRAY_SIZE(pllfhs), clk_data);
Nit: I think this could be squeezed into one line.
> free_apmixed_data:
> mtk_free_clk_data(clk_data);
> return r;
> @@ -153,7 +215,8 @@ static int clk_mt8195_apmixed_remove(struct platform_device *pdev)
>
> of_clk_del_provider(node);
> mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
> - mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
> + mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
> + ARRAY_SIZE(pllfhs), clk_data);
Same here.
ChenYu
> mtk_free_clk_data(clk_data);
>
> return 0;
> --
> 2.39.1
>
Il 07/03/23 05:43, Chen-Yu Tsai ha scritto:
> On Mon, Feb 6, 2023 at 6:01 PM AngeloGioacchino Del Regno
> <[email protected]> wrote:
>>
>> Add FHCTL parameters and register PLLs through FHCTL to add support
>> for frequency hopping and SSC. FHCTL will be enabled only on PLLs
>> specified in devicetree.
>>
>> This commit brings functional changes only upon addition of
>> devicetree configuration.
>>
>> Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
>> ---
>> drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 69 +++++++++++++++++++-
>> 1 file changed, 66 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c
>> index 1bc917f2667e..c0db31ce0741 100644
>> --- a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c
>> +++ b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c
>> @@ -3,9 +3,11 @@
>> // Copyright (c) 2021 MediaTek Inc.
>> // Author: Chun-Jie Chen <[email protected]>
>>
>> +#include "clk-fhctl.h"
>> #include "clk-gate.h"
>> #include "clk-mtk.h"
>> #include "clk-pll.h"
>> +#include "clk-pllfh.h"
>>
>> #include <dt-bindings/clock/mt8195-clk.h>
>> #include <linux/of_device.h>
>> @@ -105,6 +107,61 @@ static const struct mtk_pll_data plls[] = {
>> 0, 0, 22, 0x0158, 24, 0, 0, 0, 0x0158, 0, 0x0158, 0, 9),
>> };
>>
>> +enum fh_pll_id {
>> + FH_ARMPLL_LL,
>> + FH_ARMPLL_BL,
>> + FH_MEMPLL,
>> + FH_ADSPPLL,
>> + FH_NNAPLL,
>> + FH_CCIPLL,
>> + FH_MFGPLL,
>> + FH_TVDPLL2,
>> + FH_MPLL,
>> + FH_MMPLL,
>> + FH_MAINPLL,
>> + FH_MSDCPLL,
>> + FH_IMGPLL,
>> + FH_VDECPLL,
>> + FH_TVDPLL1,
>> + FH_NR_FH,
>> +};
>> +
>> +#define FH(_pllid, _fhid, _offset) { \
>> + .data = { \
>> + .pll_id = _pllid, \
>> + .fh_id = _fhid, \
>> + .fh_ver = FHCTL_PLLFH_V2, \
>> + .fhx_offset = _offset, \
>> + .dds_mask = GENMASK(21, 0), \
>
>> + .slope0_value = 0x6003c97, \
>> + .slope1_value = 0x6003c97, \
>
> Are these
>
>> + .sfstrx_en = BIT(2), \
>> + .frddsx_en = BIT(1), \
>> + .fhctlx_en = BIT(0), \
>> + .tgl_org = BIT(31), \
>> + .dvfs_tri = BIT(31), \
>> + .pcwchg = BIT(31), \
>
>> + .dt_val = 0x0, \
>> + .df_val = 0x9, \
>
> and these just copied from MT8186?
Yes, and that's because they're really the same.
>
>> + .updnlmt_shft = 16, \
>> + .msk_frddsx_dys = GENMASK(23, 20), \
>> + .msk_frddsx_dts = GENMASK(19, 16), \
>> + }, \
>> + }
>> +
>> +static struct mtk_pllfh_data pllfhs[] = {
>> + FH(CLK_APMIXED_ADSPPLL, FH_ADSPPLL, 0x78),
>> + FH(CLK_APMIXED_NNAPLL, FH_NNAPLL, 0x8c),
>> + FH(CLK_APMIXED_MFGPLL, FH_MFGPLL, 0xb4),
>> + FH(CLK_APMIXED_TVDPLL2, FH_TVDPLL2, 0xc8),
>> + FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0xf0),
>> + FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x104),
>> + FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x118),
>> + FH(CLK_APMIXED_IMGPLL, FH_IMGPLL, 0x12c),
>> + FH(CLK_APMIXED_VDECPLL, FH_VDECPLL, 0x140),
>> + FH(CLK_APMIXED_TVDPLL2, FH_TVDPLL1, 0x154),
>> +};
>> +
>> static const struct of_device_id of_match_clk_mt8195_apmixed[] = {
>> { .compatible = "mediatek,mt8195-apmixedsys", },
>> {}
>> @@ -114,13 +171,17 @@ static int clk_mt8195_apmixed_probe(struct platform_device *pdev)
>> {
>> struct clk_hw_onecell_data *clk_data;
>> struct device_node *node = pdev->dev.of_node;
>> + const u8 *fhctl_node = "mediatek,mt8195-fhctl";
>> int r;
>>
>> clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
>> if (!clk_data)
>> return -ENOMEM;
>>
>> - r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
>> + fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
>> +
>> + r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls),
>> + pllfhs, ARRAY_SIZE(pllfhs), clk_data);
>> if (r)
>> goto free_apmixed_data;
>>
>> @@ -140,7 +201,8 @@ static int clk_mt8195_apmixed_probe(struct platform_device *pdev)
>> unregister_gates:
>> mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
>> unregister_plls:
>> - mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
>> + mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
>> + ARRAY_SIZE(pllfhs), clk_data);
>
> Nit: I think this could be squeezed into one line.
>
>> free_apmixed_data:
>> mtk_free_clk_data(clk_data);
>> return r;
>> @@ -153,7 +215,8 @@ static int clk_mt8195_apmixed_remove(struct platform_device *pdev)
>>
>> of_clk_del_provider(node);
>> mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
>> - mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
>> + mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
>> + ARRAY_SIZE(pllfhs), clk_data);
>
> Same here.
>
That's the same on the others as well, but if I compress those lines I will have
to rebase the clocks cleanup series again and send the 54 patches again.. I'd like
to avoid that noise.
If you really want though, I can do that... what should I do?
Regards,
Angelo
On Tue, Mar 7, 2023 at 5:27 PM AngeloGioacchino Del Regno
<[email protected]> wrote:
>
> Il 07/03/23 05:43, Chen-Yu Tsai ha scritto:
> > On Mon, Feb 6, 2023 at 6:01 PM AngeloGioacchino Del Regno
> > <[email protected]> wrote:
> >>
> >> Add FHCTL parameters and register PLLs through FHCTL to add support
> >> for frequency hopping and SSC. FHCTL will be enabled only on PLLs
> >> specified in devicetree.
> >>
> >> This commit brings functional changes only upon addition of
> >> devicetree configuration.
> >>
> >> Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
> >> ---
> >> drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 69 +++++++++++++++++++-
> >> 1 file changed, 66 insertions(+), 3 deletions(-)
> >>
> >> diff --git a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c
> >> index 1bc917f2667e..c0db31ce0741 100644
> >> --- a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c
> >> +++ b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c
> >> @@ -3,9 +3,11 @@
> >> // Copyright (c) 2021 MediaTek Inc.
> >> // Author: Chun-Jie Chen <[email protected]>
> >>
> >> +#include "clk-fhctl.h"
> >> #include "clk-gate.h"
> >> #include "clk-mtk.h"
> >> #include "clk-pll.h"
> >> +#include "clk-pllfh.h"
> >>
> >> #include <dt-bindings/clock/mt8195-clk.h>
> >> #include <linux/of_device.h>
> >> @@ -105,6 +107,61 @@ static const struct mtk_pll_data plls[] = {
> >> 0, 0, 22, 0x0158, 24, 0, 0, 0, 0x0158, 0, 0x0158, 0, 9),
> >> };
> >>
> >> +enum fh_pll_id {
> >> + FH_ARMPLL_LL,
> >> + FH_ARMPLL_BL,
> >> + FH_MEMPLL,
> >> + FH_ADSPPLL,
> >> + FH_NNAPLL,
> >> + FH_CCIPLL,
> >> + FH_MFGPLL,
> >> + FH_TVDPLL2,
> >> + FH_MPLL,
> >> + FH_MMPLL,
> >> + FH_MAINPLL,
> >> + FH_MSDCPLL,
> >> + FH_IMGPLL,
> >> + FH_VDECPLL,
> >> + FH_TVDPLL1,
> >> + FH_NR_FH,
> >> +};
> >> +
> >> +#define FH(_pllid, _fhid, _offset) { \
> >> + .data = { \
> >> + .pll_id = _pllid, \
> >> + .fh_id = _fhid, \
> >> + .fh_ver = FHCTL_PLLFH_V2, \
> >> + .fhx_offset = _offset, \
> >> + .dds_mask = GENMASK(21, 0), \
> >
> >> + .slope0_value = 0x6003c97, \
> >> + .slope1_value = 0x6003c97, \
> >
> > Are these
> >
> >> + .sfstrx_en = BIT(2), \
> >> + .frddsx_en = BIT(1), \
> >> + .fhctlx_en = BIT(0), \
> >> + .tgl_org = BIT(31), \
> >> + .dvfs_tri = BIT(31), \
> >> + .pcwchg = BIT(31), \
> >
> >> + .dt_val = 0x0, \
> >> + .df_val = 0x9, \
> >
> > and these just copied from MT8186?
>
> Yes, and that's because they're really the same.
Just to be safe, I asked MediaTek to take a look at the parameters.
> >
> >> + .updnlmt_shft = 16, \
> >> + .msk_frddsx_dys = GENMASK(23, 20), \
> >> + .msk_frddsx_dts = GENMASK(19, 16), \
> >> + }, \
> >> + }
> >> +
> >> +static struct mtk_pllfh_data pllfhs[] = {
> >> + FH(CLK_APMIXED_ADSPPLL, FH_ADSPPLL, 0x78),
> >> + FH(CLK_APMIXED_NNAPLL, FH_NNAPLL, 0x8c),
> >> + FH(CLK_APMIXED_MFGPLL, FH_MFGPLL, 0xb4),
> >> + FH(CLK_APMIXED_TVDPLL2, FH_TVDPLL2, 0xc8),
> >> + FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0xf0),
> >> + FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x104),
> >> + FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x118),
> >> + FH(CLK_APMIXED_IMGPLL, FH_IMGPLL, 0x12c),
> >> + FH(CLK_APMIXED_VDECPLL, FH_VDECPLL, 0x140),
> >> + FH(CLK_APMIXED_TVDPLL2, FH_TVDPLL1, 0x154),
> >> +};
> >> +
> >> static const struct of_device_id of_match_clk_mt8195_apmixed[] = {
> >> { .compatible = "mediatek,mt8195-apmixedsys", },
> >> {}
> >> @@ -114,13 +171,17 @@ static int clk_mt8195_apmixed_probe(struct platform_device *pdev)
> >> {
> >> struct clk_hw_onecell_data *clk_data;
> >> struct device_node *node = pdev->dev.of_node;
> >> + const u8 *fhctl_node = "mediatek,mt8195-fhctl";
> >> int r;
> >>
> >> clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
> >> if (!clk_data)
> >> return -ENOMEM;
> >>
> >> - r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
> >> + fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
> >> +
> >> + r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls),
> >> + pllfhs, ARRAY_SIZE(pllfhs), clk_data);
> >> if (r)
> >> goto free_apmixed_data;
> >>
> >> @@ -140,7 +201,8 @@ static int clk_mt8195_apmixed_probe(struct platform_device *pdev)
> >> unregister_gates:
> >> mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
> >> unregister_plls:
> >> - mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
> >> + mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
> >> + ARRAY_SIZE(pllfhs), clk_data);
> >
> > Nit: I think this could be squeezed into one line.
> >
> >> free_apmixed_data:
> >> mtk_free_clk_data(clk_data);
> >> return r;
> >> @@ -153,7 +215,8 @@ static int clk_mt8195_apmixed_remove(struct platform_device *pdev)
> >>
> >> of_clk_del_provider(node);
> >> mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
> >> - mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
> >> + mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
> >> + ARRAY_SIZE(pllfhs), clk_data);
> >
> > Same here.
> >
>
> That's the same on the others as well, but if I compress those lines I will have
> to rebase the clocks cleanup series again and send the 54 patches again.. I'd like
> to avoid that noise.
>
> If you really want though, I can do that... what should I do?
I see. Let's keep it the way it is then.
Il 07/03/23 10:29, Chen-Yu Tsai ha scritto:
> On Tue, Mar 7, 2023 at 5:27 PM AngeloGioacchino Del Regno
> <[email protected]> wrote:
>>
>> Il 07/03/23 05:43, Chen-Yu Tsai ha scritto:
>>> On Mon, Feb 6, 2023 at 6:01 PM AngeloGioacchino Del Regno
>>> <[email protected]> wrote:
>>>>
>>>> Add FHCTL parameters and register PLLs through FHCTL to add support
>>>> for frequency hopping and SSC. FHCTL will be enabled only on PLLs
>>>> specified in devicetree.
>>>>
>>>> This commit brings functional changes only upon addition of
>>>> devicetree configuration.
>>>>
>>>> Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
>>>> ---
>>>> drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 69 +++++++++++++++++++-
>>>> 1 file changed, 66 insertions(+), 3 deletions(-)
>>>>
>>>> diff --git a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c
>>>> index 1bc917f2667e..c0db31ce0741 100644
>>>> --- a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c
>>>> +++ b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c
>>>> @@ -3,9 +3,11 @@
>>>> // Copyright (c) 2021 MediaTek Inc.
>>>> // Author: Chun-Jie Chen <[email protected]>
>>>>
>>>> +#include "clk-fhctl.h"
>>>> #include "clk-gate.h"
>>>> #include "clk-mtk.h"
>>>> #include "clk-pll.h"
>>>> +#include "clk-pllfh.h"
>>>>
>>>> #include <dt-bindings/clock/mt8195-clk.h>
>>>> #include <linux/of_device.h>
>>>> @@ -105,6 +107,61 @@ static const struct mtk_pll_data plls[] = {
>>>> 0, 0, 22, 0x0158, 24, 0, 0, 0, 0x0158, 0, 0x0158, 0, 9),
>>>> };
>>>>
>>>> +enum fh_pll_id {
>>>> + FH_ARMPLL_LL,
>>>> + FH_ARMPLL_BL,
>>>> + FH_MEMPLL,
>>>> + FH_ADSPPLL,
>>>> + FH_NNAPLL,
>>>> + FH_CCIPLL,
>>>> + FH_MFGPLL,
>>>> + FH_TVDPLL2,
>>>> + FH_MPLL,
>>>> + FH_MMPLL,
>>>> + FH_MAINPLL,
>>>> + FH_MSDCPLL,
>>>> + FH_IMGPLL,
>>>> + FH_VDECPLL,
>>>> + FH_TVDPLL1,
>>>> + FH_NR_FH,
>>>> +};
>>>> +
>>>> +#define FH(_pllid, _fhid, _offset) { \
>>>> + .data = { \
>>>> + .pll_id = _pllid, \
>>>> + .fh_id = _fhid, \
>>>> + .fh_ver = FHCTL_PLLFH_V2, \
>>>> + .fhx_offset = _offset, \
>>>> + .dds_mask = GENMASK(21, 0), \
>>>
>>>> + .slope0_value = 0x6003c97, \
>>>> + .slope1_value = 0x6003c97, \
>>>
>>> Are these
>>>
>>>> + .sfstrx_en = BIT(2), \
>>>> + .frddsx_en = BIT(1), \
>>>> + .fhctlx_en = BIT(0), \
>>>> + .tgl_org = BIT(31), \
>>>> + .dvfs_tri = BIT(31), \
>>>> + .pcwchg = BIT(31), \
>>>
>>>> + .dt_val = 0x0, \
>>>> + .df_val = 0x9, \
>>>
>>> and these just copied from MT8186?
>>
>> Yes, and that's because they're really the same.
>
> Just to be safe, I asked MediaTek to take a look at the parameters.
>
Cool. Let's see what they say then!
>>>
>>>> + .updnlmt_shft = 16, \
>>>> + .msk_frddsx_dys = GENMASK(23, 20), \
>>>> + .msk_frddsx_dts = GENMASK(19, 16), \
>>>> + }, \
>>>> + }
>>>> +
>>>> +static struct mtk_pllfh_data pllfhs[] = {
>>>> + FH(CLK_APMIXED_ADSPPLL, FH_ADSPPLL, 0x78),
>>>> + FH(CLK_APMIXED_NNAPLL, FH_NNAPLL, 0x8c),
>>>> + FH(CLK_APMIXED_MFGPLL, FH_MFGPLL, 0xb4),
>>>> + FH(CLK_APMIXED_TVDPLL2, FH_TVDPLL2, 0xc8),
>>>> + FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0xf0),
>>>> + FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x104),
>>>> + FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x118),
>>>> + FH(CLK_APMIXED_IMGPLL, FH_IMGPLL, 0x12c),
>>>> + FH(CLK_APMIXED_VDECPLL, FH_VDECPLL, 0x140),
>>>> + FH(CLK_APMIXED_TVDPLL2, FH_TVDPLL1, 0x154),
>>>> +};
>>>> +
>>>> static const struct of_device_id of_match_clk_mt8195_apmixed[] = {
>>>> { .compatible = "mediatek,mt8195-apmixedsys", },
>>>> {}
>>>> @@ -114,13 +171,17 @@ static int clk_mt8195_apmixed_probe(struct platform_device *pdev)
>>>> {
>>>> struct clk_hw_onecell_data *clk_data;
>>>> struct device_node *node = pdev->dev.of_node;
>>>> + const u8 *fhctl_node = "mediatek,mt8195-fhctl";
>>>> int r;
>>>>
>>>> clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
>>>> if (!clk_data)
>>>> return -ENOMEM;
>>>>
>>>> - r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
>>>> + fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
>>>> +
>>>> + r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls),
>>>> + pllfhs, ARRAY_SIZE(pllfhs), clk_data);
>>>> if (r)
>>>> goto free_apmixed_data;
>>>>
>>>> @@ -140,7 +201,8 @@ static int clk_mt8195_apmixed_probe(struct platform_device *pdev)
>>>> unregister_gates:
>>>> mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
>>>> unregister_plls:
>>>> - mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
>>>> + mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
>>>> + ARRAY_SIZE(pllfhs), clk_data);
>>>
>>> Nit: I think this could be squeezed into one line.
>>>
>>>> free_apmixed_data:
>>>> mtk_free_clk_data(clk_data);
>>>> return r;
>>>> @@ -153,7 +215,8 @@ static int clk_mt8195_apmixed_remove(struct platform_device *pdev)
>>>>
>>>> of_clk_del_provider(node);
>>>> mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
>>>> - mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
>>>> + mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
>>>> + ARRAY_SIZE(pllfhs), clk_data);
>>>
>>> Same here.
>>>
>>
>> That's the same on the others as well, but if I compress those lines I will have
>> to rebase the clocks cleanup series again and send the 54 patches again.. I'd like
>> to avoid that noise.
>>
>> If you really want though, I can do that... what should I do?
>
> I see. Let's keep it the way it is then.
>
Great. We can always do a small cleanup later, if needed.
Angelo
On Mon, Feb 6, 2023 at 6:01 PM AngeloGioacchino Del Regno
<[email protected]> wrote:
>
> Changes in v3:
> - Added commit to export register/unregister/parse FHCTL functions
> to allow building clock drivers using FHCTL as modules
>
> Changes in v2:
> - Rebased over v4 of my clock drivers cleanups series [1]
>
> This series adds support for Frequency Hopping (FHCTL) on more MediaTek
> SoCs, specifically, MT6795, MT8173, MT8192 and MT8195.
>
> In order to support older platforms like MT6795 and MT8173 it was
> necessary to add a new register layout that is ever-so-slightly
> different from the one that was previously introduced for MT8186.
>
> Since the new layout refers to older SoCs, the one valid for MT8186
> and newer SoCs was renamed to be a "v2" layout, while the new one
> for older chips gets the "v1" name.
>
> Note: These commits won't change any behavior unless FHCTL gets
> explicitly enabled and configured in devicetrees.
>
> [1]: https://patchwork.kernel.org/project/linux-mediatek/list/?series=714059
> AngeloGioacchino Del Regno (7):
> clk: mediatek: fhctl: Add support for older fhctl register layout
> clk: mediatek: clk-pllfh: Export register/unregister/parse functions
> dt-bindings: clock: mediatek,mt8186-fhctl: Support MT6795,
> MT8173/92/95
> clk: mediatek: mt6795: Add support for frequency hopping through FHCTL
> clk: mediatek: mt8173: Add support for frequency hopping through FHCTL
> clk: mediatek: mt8192: Add support for frequency hopping through FHCTL
> clk: mediatek: mt8195: Add support for frequency hopping through FHCTL
The changes look good to me overall. I've asked MediaTek to take a look
at the various parameters used is this series, as I don't have the register
definitions for the old version, and from what I've been told, the slope
and other parameters depend on the chip design as well as manufacturing
process used.
So, code wise this series is
Reviewed-by: Chen-Yu Tsai <[email protected]>
Quoting AngeloGioacchino Del Regno (2023-02-06 02:01:03)
> Add FHCTL parameters and register PLLs through FHCTL to add support
> for frequency hopping and SSC. FHCTL will be enabled only on PLLs
> specified in devicetree.
>
> This commit brings functional changes only upon addition of
> devicetree configuration.
>
> Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
> ---
Applied to clk-next
Quoting AngeloGioacchino Del Regno (2023-02-06 02:01:02)
> Add FHCTL parameters and register PLLs through FHCTL to add support
> for frequency hopping and SSC. FHCTL will be enabled only on PLLs
> specified in devicetree.
>
> This commit brings functional changes only upon addition of
> devicetree configuration.
>
> Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
> ---
Applied to clk-next
Quoting AngeloGioacchino Del Regno (2023-02-06 02:01:04)
> Add FHCTL parameters and register PLLs through FHCTL to add support
> for frequency hopping and SSC. FHCTL will be enabled only on PLLs
> specified in devicetree.
>
> This commit brings functional changes only upon addition of
> devicetree configuration.
>
> Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
> ---
Applied to clk-next
Quoting AngeloGioacchino Del Regno (2023-02-06 02:01:05)
> Add FHCTL parameters and register PLLs through FHCTL to add support
> for frequency hopping and SSC. FHCTL will be enabled only on PLLs
> specified in devicetree.
>
> This commit brings functional changes only upon addition of
> devicetree configuration.
>
> Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
> ---
Applied to clk-next