Update devicetree sources for UniPhier SoCs to align node names
to generic, add missing properties and compatible strings,
and add SD UHS property.
The SD UHS mode patches are related to the series:
https://lore.kernel.org/lkml/[email protected]/
Kunihiko Hayashi (8):
ARM: dts: uniphier: Align node names for SoC-dependent controller and
PHYs with bindings
ARM: dts: uniphier: Add missing reg properties for glue layer
ARM: dts: uniphier: Add syscon compatible string to soc-glue-debug
ARM: dts: uniphier: Add syscon-uhs-mode to SD node
arm64: dts: uniphier: Align node names for SoC-dependent controller
and PHYs with bindings
arm64: dts: uniphier: Add missing reg properties for glue layer nodes
arm64: dts: uniphier: Add syscon compatible string to soc-glue-debug
arm64: dts: uniphier: Add syscon-uhs-mode to SD node
arch/arm/boot/dts/uniphier-ld4.dtsi | 25 +++++-----
arch/arm/boot/dts/uniphier-pro4.dtsi | 44 ++++++++++-------
arch/arm/boot/dts/uniphier-pro5.dtsi | 42 +++++++++-------
arch/arm/boot/dts/uniphier-pxs2.dtsi | 49 ++++++++++---------
arch/arm/boot/dts/uniphier-sld8.dtsi | 26 +++++-----
.../boot/dts/socionext/uniphier-ld11.dtsi | 35 ++++++-------
.../boot/dts/socionext/uniphier-ld20.dtsi | 45 +++++++++--------
.../boot/dts/socionext/uniphier-pxs3.dtsi | 48 ++++++++++--------
8 files changed, 171 insertions(+), 143 deletions(-)
--
2.25.1
The nodes for glue layers should include "reg" property.
Add the property according to the DT schema.
Signed-off-by: Kunihiko Hayashi <[email protected]>
---
arch/arm/boot/dts/uniphier-ld4.dtsi | 1 +
arch/arm/boot/dts/uniphier-pro4.dtsi | 5 +++++
arch/arm/boot/dts/uniphier-pro5.dtsi | 3 +++
arch/arm/boot/dts/uniphier-pxs2.dtsi | 4 ++++
arch/arm/boot/dts/uniphier-sld8.dtsi | 1 +
5 files changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi
index 06b9571345a2..da2e3e0ffafd 100644
--- a/arch/arm/boot/dts/uniphier-ld4.dtsi
+++ b/arch/arm/boot/dts/uniphier-ld4.dtsi
@@ -347,6 +347,7 @@ pinctrl: pinctrl {
syscon@5f900000 {
compatible = "socionext,uniphier-ld4-soc-glue-debug",
"simple-mfd";
+ reg = <0x5f900000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x5f900000 0x2000>;
diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi
index 064f98b61525..048f4606fbae 100644
--- a/arch/arm/boot/dts/uniphier-pro4.dtsi
+++ b/arch/arm/boot/dts/uniphier-pro4.dtsi
@@ -421,6 +421,7 @@ sg_clk: clock-controller {
syscon@5f900000 {
compatible = "socionext,uniphier-pro4-soc-glue-debug",
"simple-mfd";
+ reg = <0x5f900000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x5f900000 0x2000>;
@@ -535,6 +536,7 @@ ahci0: sata@65600000 {
sata-controller@65700000 {
compatible = "socionext,uniphier-pxs2-ahci-glue",
"simple-mfd";
+ reg = <0x65700000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65700000 0x100>;
@@ -581,6 +583,7 @@ ahci1: sata@65800000 {
sata-controller@65900000 {
compatible = "socionext,uniphier-pro4-ahci-glue",
"simple-mfd";
+ reg = <0x65900000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65900000 0x100>;
@@ -629,6 +632,7 @@ usb0: usb@65a00000 {
usb-controller@65b00000 {
compatible = "socionext,uniphier-pro4-dwc3-glue",
"simple-mfd";
+ reg = <0x65b00000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65b00000 0x100>;
@@ -683,6 +687,7 @@ usb1: usb@65c00000 {
usb-controller@65d00000 {
compatible = "socionext,uniphier-pro4-dwc3-glue",
"simple-mfd";
+ reg = <0x65d00000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65d00000 0x100>;
diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi
index 2af4fa19bf14..f4c87a100095 100644
--- a/arch/arm/boot/dts/uniphier-pro5.dtsi
+++ b/arch/arm/boot/dts/uniphier-pro5.dtsi
@@ -386,6 +386,7 @@ pinctrl: pinctrl {
syscon@5f900000 {
compatible = "socionext,uniphier-pro5-soc-glue-debug",
"simple-mfd";
+ reg = <0x5f900000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x5f900000 0x2000>;
@@ -489,6 +490,7 @@ usb0: usb@65a00000 {
usb-controller@65b00000 {
compatible = "socionext,uniphier-pro5-dwc3-glue",
"simple-mfd";
+ reg = <0x65b00000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65b00000 0x400>;
@@ -553,6 +555,7 @@ usb1: usb@65c00000 {
usb-controller@65d00000 {
compatible = "socionext,uniphier-pro5-dwc3-glue",
"simple-mfd";
+ reg = <0x65d00000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65d00000 0x400>;
diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi
index 050e9b7c83f1..1442320747ec 100644
--- a/arch/arm/boot/dts/uniphier-pxs2.dtsi
+++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi
@@ -501,6 +501,7 @@ pinctrl: pinctrl {
syscon@5f900000 {
compatible = "socionext,uniphier-pxs2-soc-glue-debug",
"simple-mfd";
+ reg = <0x5f900000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x5f900000 0x2000>;
@@ -614,6 +615,7 @@ ahci: sata@65600000 {
sata-controller@65700000 {
compatible = "socionext,uniphier-pxs2-ahci-glue",
"simple-mfd";
+ reg = <0x65700000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65700000 0x100>;
@@ -658,6 +660,7 @@ usb0: usb@65a00000 {
usb-controller@65b00000 {
compatible = "socionext,uniphier-pxs2-dwc3-glue",
"simple-mfd";
+ reg = <0x65b00000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65b00000 0x400>;
@@ -753,6 +756,7 @@ usb1: usb@65c00000 {
usb-controller@65d00000 {
compatible = "socionext,uniphier-pxs2-dwc3-glue",
"simple-mfd";
+ reg = <0x65d00000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65d00000 0x400>;
diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi
index b4453f9fe981..c79c9bfef3ec 100644
--- a/arch/arm/boot/dts/uniphier-sld8.dtsi
+++ b/arch/arm/boot/dts/uniphier-sld8.dtsi
@@ -351,6 +351,7 @@ pinctrl: pinctrl {
syscon@5f900000 {
compatible = "socionext,uniphier-sld8-soc-glue-debug",
"simple-mfd";
+ reg = <0x5f900000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x5f900000 0x2000>;
--
2.25.1
The node names for SoC-dependent controllers and PHYs should be
generic ones according to the DT schemas.
Signed-off-by: Kunihiko Hayashi <[email protected]>
---
arch/arm/boot/dts/uniphier-ld4.dtsi | 22 +++++++--------
arch/arm/boot/dts/uniphier-pro4.dtsi | 36 ++++++++++++------------
arch/arm/boot/dts/uniphier-pro5.dtsi | 36 ++++++++++++------------
arch/arm/boot/dts/uniphier-pxs2.dtsi | 42 ++++++++++++++--------------
arch/arm/boot/dts/uniphier-sld8.dtsi | 22 +++++++--------
5 files changed, 79 insertions(+), 79 deletions(-)
diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi
index 9dceff12a633..06b9571345a2 100644
--- a/arch/arm/boot/dts/uniphier-ld4.dtsi
+++ b/arch/arm/boot/dts/uniphier-ld4.dtsi
@@ -207,33 +207,33 @@ smpctrl@59801000 {
reg = <0x59801000 0x400>;
};
- mioctrl@59810000 {
+ syscon@59810000 {
compatible = "socionext,uniphier-ld4-mioctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x800>;
- mio_clk: clock {
+ mio_clk: clock-controller {
compatible = "socionext,uniphier-ld4-mio-clock";
#clock-cells = <1>;
};
- mio_rst: reset {
+ mio_rst: reset-controller {
compatible = "socionext,uniphier-ld4-mio-reset";
#reset-cells = <1>;
};
};
- perictrl@59820000 {
+ syscon@59820000 {
compatible = "socionext,uniphier-ld4-perictrl",
"simple-mfd", "syscon";
reg = <0x59820000 0x200>;
- peri_clk: clock {
+ peri_clk: clock-controller {
compatible = "socionext,uniphier-ld4-peri-clock";
#clock-cells = <1>;
};
- peri_rst: reset {
+ peri_rst: reset-controller {
compatible = "socionext,uniphier-ld4-peri-reset";
#reset-cells = <1>;
};
@@ -334,7 +334,7 @@ usb2: usb@5a820100 {
has-transaction-translator;
};
- soc-glue@5f800000 {
+ syscon@5f800000 {
compatible = "socionext,uniphier-ld4-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
@@ -344,7 +344,7 @@ pinctrl: pinctrl {
};
};
- soc-glue@5f900000 {
+ syscon@5f900000 {
compatible = "socionext,uniphier-ld4-soc-glue-debug",
"simple-mfd";
#address-cells = <1>;
@@ -393,17 +393,17 @@ aidet: interrupt-controller@61830000 {
#interrupt-cells = <2>;
};
- sysctrl@61840000 {
+ syscon@61840000 {
compatible = "socionext,uniphier-ld4-sysctrl",
"simple-mfd", "syscon";
reg = <0x61840000 0x10000>;
- sys_clk: clock {
+ sys_clk: clock-controller {
compatible = "socionext,uniphier-ld4-clock";
#clock-cells = <1>;
};
- sys_rst: reset {
+ sys_rst: reset-controller {
compatible = "socionext,uniphier-ld4-reset";
#reset-cells = <1>;
};
diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi
index a309e64c57c8..064f98b61525 100644
--- a/arch/arm/boot/dts/uniphier-pro4.dtsi
+++ b/arch/arm/boot/dts/uniphier-pro4.dtsi
@@ -241,33 +241,33 @@ smpctrl@59801000 {
reg = <0x59801000 0x400>;
};
- mioctrl@59810000 {
+ syscon@59810000 {
compatible = "socionext,uniphier-pro4-mioctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x800>;
- mio_clk: clock {
+ mio_clk: clock-controller {
compatible = "socionext,uniphier-pro4-mio-clock";
#clock-cells = <1>;
};
- mio_rst: reset {
+ mio_rst: reset-controller {
compatible = "socionext,uniphier-pro4-mio-reset";
#reset-cells = <1>;
};
};
- perictrl@59820000 {
+ syscon@59820000 {
compatible = "socionext,uniphier-pro4-perictrl",
"simple-mfd", "syscon";
reg = <0x59820000 0x200>;
- peri_clk: clock {
+ peri_clk: clock-controller {
compatible = "socionext,uniphier-pro4-peri-clock";
#clock-cells = <1>;
};
- peri_rst: reset {
+ peri_rst: reset-controller {
compatible = "socionext,uniphier-pro4-peri-reset";
#reset-cells = <1>;
};
@@ -375,7 +375,7 @@ usb3: usb@5a810100 {
has-transaction-translator;
};
- soc_glue: soc-glue@5f800000 {
+ soc_glue: syscon@5f800000 {
compatible = "socionext,uniphier-pro4-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
@@ -384,7 +384,7 @@ pinctrl: pinctrl {
compatible = "socionext,uniphier-pro4-pinctrl";
};
- usb-controller {
+ usb-hub {
compatible = "socionext,uniphier-pro4-usb2-phy";
#address-cells = <1>;
#size-cells = <0>;
@@ -412,13 +412,13 @@ usb_phy3: phy@3 {
};
};
- sg_clk: clock {
+ sg_clk: clock-controller {
compatible = "socionext,uniphier-pro4-sg-clock";
#clock-cells = <1>;
};
};
- soc-glue@5f900000 {
+ syscon@5f900000 {
compatible = "socionext,uniphier-pro4-soc-glue-debug",
"simple-mfd";
#address-cells = <1>;
@@ -480,17 +480,17 @@ intc: interrupt-controller@60001000 {
interrupt-controller;
};
- sysctrl@61840000 {
+ syscon@61840000 {
compatible = "socionext,uniphier-pro4-sysctrl",
"simple-mfd", "syscon";
reg = <0x61840000 0x10000>;
- sys_clk: clock {
+ sys_clk: clock-controller {
compatible = "socionext,uniphier-pro4-clock";
#clock-cells = <1>;
};
- sys_rst: reset {
+ sys_rst: reset-controller {
compatible = "socionext,uniphier-pro4-reset";
#reset-cells = <1>;
};
@@ -549,7 +549,7 @@ ahci0_rst: reset-controller@0 {
#reset-cells = <1>;
};
- ahci0_phy: sata-phy@10 {
+ ahci0_phy: phy@10 {
compatible = "socionext,uniphier-pro4-ahci-phy";
reg = <0x10 0x40>;
clock-names = "link", "gio";
@@ -595,7 +595,7 @@ ahci1_rst: reset-controller@0 {
#reset-cells = <1>;
};
- ahci1_phy: sata-phy@10 {
+ ahci1_phy: phy@10 {
compatible = "socionext,uniphier-pro4-ahci-phy";
reg = <0x10 0x40>;
clock-names = "link", "gio";
@@ -642,7 +642,7 @@ usb0_vbus: regulator@0 {
resets = <&sys_rst 12>, <&sys_rst 14>;
};
- usb0_ssphy: ss-phy@10 {
+ usb0_ssphy: phy@10 {
compatible = "socionext,uniphier-pro4-usb3-ssphy";
reg = <0x10 0x10>;
#phy-cells = <0>;
@@ -653,7 +653,7 @@ usb0_ssphy: ss-phy@10 {
vbus-supply = <&usb0_vbus>;
};
- usb0_rst: reset@40 {
+ usb0_rst: reset-controller@40 {
compatible = "socionext,uniphier-pro4-usb3-reset";
reg = <0x40 0x4>;
#reset-cells = <1>;
@@ -696,7 +696,7 @@ usb1_vbus: regulator@0 {
resets = <&sys_rst 12>, <&sys_rst 15>;
};
- usb1_rst: reset@40 {
+ usb1_rst: reset-controller@40 {
compatible = "socionext,uniphier-pro4-usb3-reset";
reg = <0x40 0x4>;
#reset-cells = <1>;
diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi
index 100edd7438d8..2af4fa19bf14 100644
--- a/arch/arm/boot/dts/uniphier-pro5.dtsi
+++ b/arch/arm/boot/dts/uniphier-pro5.dtsi
@@ -341,39 +341,39 @@ smpctrl@59801000 {
reg = <0x59801000 0x400>;
};
- sdctrl@59810000 {
+ syscon@59810000 {
compatible = "socionext,uniphier-pro5-sdctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x400>;
- sd_clk: clock {
+ sd_clk: clock-controller {
compatible = "socionext,uniphier-pro5-sd-clock";
#clock-cells = <1>;
};
- sd_rst: reset {
+ sd_rst: reset-controller {
compatible = "socionext,uniphier-pro5-sd-reset";
#reset-cells = <1>;
};
};
- perictrl@59820000 {
+ syscon@59820000 {
compatible = "socionext,uniphier-pro5-perictrl",
"simple-mfd", "syscon";
reg = <0x59820000 0x200>;
- peri_clk: clock {
+ peri_clk: clock-controller {
compatible = "socionext,uniphier-pro5-peri-clock";
#clock-cells = <1>;
};
- peri_rst: reset {
+ peri_rst: reset-controller {
compatible = "socionext,uniphier-pro5-peri-reset";
#reset-cells = <1>;
};
};
- soc-glue@5f800000 {
+ syscon@5f800000 {
compatible = "socionext,uniphier-pro5-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
@@ -383,7 +383,7 @@ pinctrl: pinctrl {
};
};
- soc-glue@5f900000 {
+ syscon@5f900000 {
compatible = "socionext,uniphier-pro5-soc-glue-debug",
"simple-mfd";
#address-cells = <1>;
@@ -455,17 +455,17 @@ intc: interrupt-controller@60001000 {
interrupt-controller;
};
- sysctrl@61840000 {
+ syscon@61840000 {
compatible = "socionext,uniphier-pro5-sysctrl",
"simple-mfd", "syscon";
reg = <0x61840000 0x10000>;
- sys_clk: clock {
+ sys_clk: clock-controller {
compatible = "socionext,uniphier-pro5-clock";
#clock-cells = <1>;
};
- sys_rst: reset {
+ sys_rst: reset-controller {
compatible = "socionext,uniphier-pro5-reset";
#reset-cells = <1>;
};
@@ -493,7 +493,7 @@ usb-controller@65b00000 {
#size-cells = <1>;
ranges = <0 0x65b00000 0x400>;
- usb0_rst: reset@0 {
+ usb0_rst: reset-controller@0 {
compatible = "socionext,uniphier-pro5-usb3-reset";
reg = <0x0 0x4>;
#reset-cells = <1>;
@@ -512,7 +512,7 @@ usb0_vbus0: regulator@100 {
resets = <&sys_rst 12>, <&sys_rst 14>;
};
- usb0_hsphy0: hs-phy@280 {
+ usb0_hsphy0: phy@280 {
compatible = "socionext,uniphier-pro5-usb3-hsphy";
reg = <0x280 0x10>;
#phy-cells = <0>;
@@ -523,7 +523,7 @@ usb0_hsphy0: hs-phy@280 {
vbus-supply = <&usb0_vbus0>;
};
- usb0_ssphy0: ss-phy@380 {
+ usb0_ssphy0: phy@380 {
compatible = "socionext,uniphier-pro5-usb3-ssphy";
reg = <0x380 0x10>;
#phy-cells = <0>;
@@ -557,7 +557,7 @@ usb-controller@65d00000 {
#size-cells = <1>;
ranges = <0 0x65d00000 0x400>;
- usb1_rst: reset@0 {
+ usb1_rst: reset-controller@0 {
compatible = "socionext,uniphier-pro5-usb3-reset";
reg = <0x0 0x4>;
#reset-cells = <1>;
@@ -585,7 +585,7 @@ usb1_vbus1: regulator@110 {
resets = <&sys_rst 12>, <&sys_rst 15>;
};
- usb1_hsphy0: hs-phy@280 {
+ usb1_hsphy0: phy@280 {
compatible = "socionext,uniphier-pro5-usb3-hsphy";
reg = <0x280 0x10>;
#phy-cells = <0>;
@@ -596,7 +596,7 @@ usb1_hsphy0: hs-phy@280 {
vbus-supply = <&usb1_vbus0>;
};
- usb1_hsphy1: hs-phy@290 {
+ usb1_hsphy1: phy@290 {
compatible = "socionext,uniphier-pro5-usb3-hsphy";
reg = <0x290 0x10>;
#phy-cells = <0>;
@@ -607,7 +607,7 @@ usb1_hsphy1: hs-phy@290 {
vbus-supply = <&usb1_vbus1>;
};
- usb1_ssphy0: ss-phy@380 {
+ usb1_ssphy0: phy@380 {
compatible = "socionext,uniphier-pro5-usb3-ssphy";
reg = <0x380 0x10>;
#phy-cells = <0>;
diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi
index ca4dccf56a67..050e9b7c83f1 100644
--- a/arch/arm/boot/dts/uniphier-pxs2.dtsi
+++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi
@@ -422,33 +422,33 @@ smpctrl@59801000 {
reg = <0x59801000 0x400>;
};
- sdctrl@59810000 {
+ syscon@59810000 {
compatible = "socionext,uniphier-pxs2-sdctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x400>;
- sd_clk: clock {
+ sd_clk: clock-controller {
compatible = "socionext,uniphier-pxs2-sd-clock";
#clock-cells = <1>;
};
- sd_rst: reset {
+ sd_rst: reset-controller {
compatible = "socionext,uniphier-pxs2-sd-reset";
#reset-cells = <1>;
};
};
- perictrl@59820000 {
+ syscon@59820000 {
compatible = "socionext,uniphier-pxs2-perictrl",
"simple-mfd", "syscon";
reg = <0x59820000 0x200>;
- peri_clk: clock {
+ peri_clk: clock-controller {
compatible = "socionext,uniphier-pxs2-peri-clock";
#clock-cells = <1>;
};
- peri_rst: reset {
+ peri_rst: reset-controller {
compatible = "socionext,uniphier-pxs2-peri-reset";
#reset-cells = <1>;
};
@@ -488,7 +488,7 @@ sd: mmc@5a400000 {
sd-uhs-sdr50;
};
- soc_glue: soc-glue@5f800000 {
+ soc_glue: syscon@5f800000 {
compatible = "socionext,uniphier-pxs2-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
@@ -498,7 +498,7 @@ pinctrl: pinctrl {
};
};
- soc-glue@5f900000 {
+ syscon@5f900000 {
compatible = "socionext,uniphier-pxs2-soc-glue-debug",
"simple-mfd";
#address-cells = <1>;
@@ -555,17 +555,17 @@ intc: interrupt-controller@60001000 {
interrupt-controller;
};
- sysctrl@61840000 {
+ syscon@61840000 {
compatible = "socionext,uniphier-pxs2-sysctrl",
"simple-mfd", "syscon";
reg = <0x61840000 0x10000>;
- sys_clk: clock {
+ sys_clk: clock-controller {
compatible = "socionext,uniphier-pxs2-clock";
#clock-cells = <1>;
};
- sys_rst: reset {
+ sys_rst: reset-controller {
compatible = "socionext,uniphier-pxs2-reset";
#reset-cells = <1>;
};
@@ -628,7 +628,7 @@ ahci_rst: reset-controller@0 {
#reset-cells = <1>;
};
- ahci_phy: sata-phy@10 {
+ ahci_phy: phy@10 {
compatible = "socionext,uniphier-pxs2-ahci-phy";
reg = <0x10 0x10>;
clock-names = "link";
@@ -662,7 +662,7 @@ usb-controller@65b00000 {
#size-cells = <1>;
ranges = <0 0x65b00000 0x400>;
- usb0_rst: reset@0 {
+ usb0_rst: reset-controller@0 {
compatible = "socionext,uniphier-pxs2-usb3-reset";
reg = <0x0 0x4>;
#reset-cells = <1>;
@@ -690,7 +690,7 @@ usb0_vbus1: regulator@110 {
resets = <&sys_rst 14>;
};
- usb0_hsphy0: hs-phy@200 {
+ usb0_hsphy0: phy@200 {
compatible = "socionext,uniphier-pxs2-usb3-hsphy";
reg = <0x200 0x10>;
#phy-cells = <0>;
@@ -701,7 +701,7 @@ usb0_hsphy0: hs-phy@200 {
vbus-supply = <&usb0_vbus0>;
};
- usb0_hsphy1: hs-phy@210 {
+ usb0_hsphy1: phy@210 {
compatible = "socionext,uniphier-pxs2-usb3-hsphy";
reg = <0x210 0x10>;
#phy-cells = <0>;
@@ -712,7 +712,7 @@ usb0_hsphy1: hs-phy@210 {
vbus-supply = <&usb0_vbus1>;
};
- usb0_ssphy0: ss-phy@300 {
+ usb0_ssphy0: phy@300 {
compatible = "socionext,uniphier-pxs2-usb3-ssphy";
reg = <0x300 0x10>;
#phy-cells = <0>;
@@ -723,7 +723,7 @@ usb0_ssphy0: ss-phy@300 {
vbus-supply = <&usb0_vbus0>;
};
- usb0_ssphy1: ss-phy@310 {
+ usb0_ssphy1: phy@310 {
compatible = "socionext,uniphier-pxs2-usb3-ssphy";
reg = <0x310 0x10>;
#phy-cells = <0>;
@@ -757,7 +757,7 @@ usb-controller@65d00000 {
#size-cells = <1>;
ranges = <0 0x65d00000 0x400>;
- usb1_rst: reset@0 {
+ usb1_rst: reset-controller@0 {
compatible = "socionext,uniphier-pxs2-usb3-reset";
reg = <0x0 0x4>;
#reset-cells = <1>;
@@ -785,7 +785,7 @@ usb1_vbus1: regulator@110 {
resets = <&sys_rst 15>;
};
- usb1_hsphy0: hs-phy@200 {
+ usb1_hsphy0: phy@200 {
compatible = "socionext,uniphier-pxs2-usb3-hsphy";
reg = <0x200 0x10>;
#phy-cells = <0>;
@@ -796,7 +796,7 @@ usb1_hsphy0: hs-phy@200 {
vbus-supply = <&usb1_vbus0>;
};
- usb1_hsphy1: hs-phy@210 {
+ usb1_hsphy1: phy@210 {
compatible = "socionext,uniphier-pxs2-usb3-hsphy";
reg = <0x210 0x10>;
#phy-cells = <0>;
@@ -807,7 +807,7 @@ usb1_hsphy1: hs-phy@210 {
vbus-supply = <&usb1_vbus1>;
};
- usb1_ssphy0: ss-phy@300 {
+ usb1_ssphy0: phy@300 {
compatible = "socionext,uniphier-pxs2-usb3-ssphy";
reg = <0x300 0x10>;
#phy-cells = <0>;
diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi
index 67b12dfe513b..b4453f9fe981 100644
--- a/arch/arm/boot/dts/uniphier-sld8.dtsi
+++ b/arch/arm/boot/dts/uniphier-sld8.dtsi
@@ -211,33 +211,33 @@ smpctrl@59801000 {
reg = <0x59801000 0x400>;
};
- mioctrl@59810000 {
+ syscon@59810000 {
compatible = "socionext,uniphier-sld8-mioctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x800>;
- mio_clk: clock {
+ mio_clk: clock-controller {
compatible = "socionext,uniphier-sld8-mio-clock";
#clock-cells = <1>;
};
- mio_rst: reset {
+ mio_rst: reset-controller {
compatible = "socionext,uniphier-sld8-mio-reset";
#reset-cells = <1>;
};
};
- perictrl@59820000 {
+ syscon@59820000 {
compatible = "socionext,uniphier-sld8-perictrl",
"simple-mfd", "syscon";
reg = <0x59820000 0x200>;
- peri_clk: clock {
+ peri_clk: clock-controller {
compatible = "socionext,uniphier-sld8-peri-clock";
#clock-cells = <1>;
};
- peri_rst: reset {
+ peri_rst: reset-controller {
compatible = "socionext,uniphier-sld8-peri-reset";
#reset-cells = <1>;
};
@@ -338,7 +338,7 @@ usb2: usb@5a820100 {
has-transaction-translator;
};
- soc-glue@5f800000 {
+ syscon@5f800000 {
compatible = "socionext,uniphier-sld8-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
@@ -348,7 +348,7 @@ pinctrl: pinctrl {
};
};
- soc-glue@5f900000 {
+ syscon@5f900000 {
compatible = "socionext,uniphier-sld8-soc-glue-debug",
"simple-mfd";
#address-cells = <1>;
@@ -397,17 +397,17 @@ aidet: interrupt-controller@61830000 {
#interrupt-cells = <2>;
};
- sysctrl@61840000 {
+ syscon@61840000 {
compatible = "socionext,uniphier-sld8-sysctrl",
"simple-mfd", "syscon";
reg = <0x61840000 0x10000>;
- sys_clk: clock {
+ sys_clk: clock-controller {
compatible = "socionext,uniphier-sld8-clock";
#clock-cells = <1>;
};
- sys_rst: reset {
+ sys_rst: reset-controller {
compatible = "socionext,uniphier-sld8-reset";
#reset-cells = <1>;
};
--
2.25.1
Add sociopnext,syscon-uhs-mode prpperty to the SD node to refer the handle
of the control logic node.
Signed-off-by: Kunihiko Hayashi <[email protected]>
---
arch/arm/boot/dts/uniphier-pro4.dtsi | 3 ++-
arch/arm/boot/dts/uniphier-pro5.dtsi | 3 ++-
arch/arm/boot/dts/uniphier-pxs2.dtsi | 3 ++-
arch/arm/boot/dts/uniphier-sld8.dtsi | 3 ++-
4 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi
index c28071a08e3a..ba55af30e904 100644
--- a/arch/arm/boot/dts/uniphier-pro4.dtsi
+++ b/arch/arm/boot/dts/uniphier-pro4.dtsi
@@ -241,7 +241,7 @@ smpctrl@59801000 {
reg = <0x59801000 0x400>;
};
- syscon@59810000 {
+ mioctrl: syscon@59810000 {
compatible = "socionext,uniphier-pro4-mioctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x800>;
@@ -307,6 +307,7 @@ sd: mmc@5a400000 {
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
+ socionext,syscon-uhs-mode = <&mioctrl 0>;
};
emmc: mmc@5a500000 {
diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi
index a2000cfe9272..2d8591cdddb8 100644
--- a/arch/arm/boot/dts/uniphier-pro5.dtsi
+++ b/arch/arm/boot/dts/uniphier-pro5.dtsi
@@ -341,7 +341,7 @@ smpctrl@59801000 {
reg = <0x59801000 0x400>;
};
- syscon@59810000 {
+ sdctrl: syscon@59810000 {
compatible = "socionext,uniphier-pro5-sdctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x400>;
@@ -699,6 +699,7 @@ sd: mmc@68800000 {
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
+ socionext,syscon-uhs-mode = <&sdctrl 0>;
};
};
};
diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi
index 55a298552bec..f97a57222101 100644
--- a/arch/arm/boot/dts/uniphier-pxs2.dtsi
+++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi
@@ -422,7 +422,7 @@ smpctrl@59801000 {
reg = <0x59801000 0x400>;
};
- syscon@59810000 {
+ sdctrl: syscon@59810000 {
compatible = "socionext,uniphier-pxs2-sdctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x400>;
@@ -486,6 +486,7 @@ sd: mmc@5a400000 {
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
+ socionext,syscon-uhs-mode = <&sdctrl 0>;
};
soc_glue: syscon@5f800000 {
diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi
index 27aa55bb7f32..f876282760e9 100644
--- a/arch/arm/boot/dts/uniphier-sld8.dtsi
+++ b/arch/arm/boot/dts/uniphier-sld8.dtsi
@@ -211,7 +211,7 @@ smpctrl@59801000 {
reg = <0x59801000 0x400>;
};
- syscon@59810000 {
+ mioctrl: syscon@59810000 {
compatible = "socionext,uniphier-sld8-mioctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x800>;
@@ -276,6 +276,7 @@ sd: mmc@5a400000 {
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
+ socionext,syscon-uhs-mode = <&mioctrl 0>;
};
emmc: mmc@5a500000 {
--
2.25.1
The nodes for some glue layers don't include necessary reg properties.
Add the properties according to the DT schema.
Signed-off-by: Kunihiko Hayashi <[email protected]>
---
arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 1 +
arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 2 ++
arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 5 +++++
3 files changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
index 148d9092572a..45004b0ae3eb 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
@@ -562,6 +562,7 @@ usb_phy2: phy@2 {
syscon@5f900000 {
compatible = "socionext,uniphier-ld11-soc-glue-debug",
"simple-mfd";
+ reg = <0x5f900000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x5f900000 0x2000>;
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
index c83265c9b520..d70929b26a2a 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
@@ -626,6 +626,7 @@ pinctrl: pinctrl {
syscon@5f900000 {
compatible = "socionext,uniphier-ld20-soc-glue-debug",
"simple-mfd";
+ reg = <0x5f900000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x5f900000 0x2000>;
@@ -778,6 +779,7 @@ usb: usb@65a00000 {
usb-controller@65b00000 {
compatible = "socionext,uniphier-ld20-dwc3-glue",
"simple-mfd";
+ reg = <0x65b00000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65b00000 0x400>;
diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
index dd60cc04d6fb..4d200fec23fe 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
@@ -452,6 +452,7 @@ pinctrl: pinctrl {
syscon@5f900000 {
compatible = "socionext,uniphier-pxs3-soc-glue-debug",
"simple-mfd";
+ reg = <0x5f900000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x5f900000 0x2000>;
@@ -619,6 +620,7 @@ ahci0: sata@65600000 {
sata-controller@65700000 {
compatible = "socionext,uniphier-pxs3-ahci-glue",
"simple-mfd";
+ reg = <0x65700000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65700000 0x100>;
@@ -659,6 +661,7 @@ ahci1: sata@65800000 {
sata-controller@65900000 {
compatible = "socionext,uniphier-pxs3-ahci-glue",
"simple-mfd";
+ reg = <0x65900000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65900000 0x100>;
@@ -703,6 +706,7 @@ usb0: usb@65a00000 {
usb-controller@65b00000 {
compatible = "socionext,uniphier-pxs3-dwc3-glue",
"simple-mfd";
+ reg = <0x65b00000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65b00000 0x400>;
@@ -805,6 +809,7 @@ usb1: usb@65c00000 {
usb-controller@65d00000 {
compatible = "socionext,uniphier-pxs3-dwc3-glue",
"simple-mfd";
+ reg = <0x65d00000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65d00000 0x400>;
--
2.25.1
Add "syscon" compatible string to the nodes for soc-glue-debug
according to the DT schema.
Signed-off-by: Kunihiko Hayashi <[email protected]>
---
arch/arm/boot/dts/uniphier-ld4.dtsi | 2 +-
arch/arm/boot/dts/uniphier-pro4.dtsi | 2 +-
arch/arm/boot/dts/uniphier-pro5.dtsi | 2 +-
arch/arm/boot/dts/uniphier-pxs2.dtsi | 2 +-
arch/arm/boot/dts/uniphier-sld8.dtsi | 2 +-
5 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi
index da2e3e0ffafd..df2de7a40211 100644
--- a/arch/arm/boot/dts/uniphier-ld4.dtsi
+++ b/arch/arm/boot/dts/uniphier-ld4.dtsi
@@ -346,7 +346,7 @@ pinctrl: pinctrl {
syscon@5f900000 {
compatible = "socionext,uniphier-ld4-soc-glue-debug",
- "simple-mfd";
+ "simple-mfd", "syscon";
reg = <0x5f900000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi
index 048f4606fbae..c28071a08e3a 100644
--- a/arch/arm/boot/dts/uniphier-pro4.dtsi
+++ b/arch/arm/boot/dts/uniphier-pro4.dtsi
@@ -420,7 +420,7 @@ sg_clk: clock-controller {
syscon@5f900000 {
compatible = "socionext,uniphier-pro4-soc-glue-debug",
- "simple-mfd";
+ "simple-mfd", "syscon";
reg = <0x5f900000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi
index f4c87a100095..a2000cfe9272 100644
--- a/arch/arm/boot/dts/uniphier-pro5.dtsi
+++ b/arch/arm/boot/dts/uniphier-pro5.dtsi
@@ -385,7 +385,7 @@ pinctrl: pinctrl {
syscon@5f900000 {
compatible = "socionext,uniphier-pro5-soc-glue-debug",
- "simple-mfd";
+ "simple-mfd", "syscon";
reg = <0x5f900000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi
index 1442320747ec..55a298552bec 100644
--- a/arch/arm/boot/dts/uniphier-pxs2.dtsi
+++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi
@@ -500,7 +500,7 @@ pinctrl: pinctrl {
syscon@5f900000 {
compatible = "socionext,uniphier-pxs2-soc-glue-debug",
- "simple-mfd";
+ "simple-mfd", "syscon";
reg = <0x5f900000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi
index c79c9bfef3ec..27aa55bb7f32 100644
--- a/arch/arm/boot/dts/uniphier-sld8.dtsi
+++ b/arch/arm/boot/dts/uniphier-sld8.dtsi
@@ -350,7 +350,7 @@ pinctrl: pinctrl {
syscon@5f900000 {
compatible = "socionext,uniphier-sld8-soc-glue-debug",
- "simple-mfd";
+ "simple-mfd", "syscon";
reg = <0x5f900000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
--
2.25.1
Add "syscon" compatible string to the nodes for soc-glue-debug
according to the DT schema.
Signed-off-by: Kunihiko Hayashi <[email protected]>
---
arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 2 +-
arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 2 +-
arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
index 45004b0ae3eb..7bb36b071475 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
@@ -561,7 +561,7 @@ usb_phy2: phy@2 {
syscon@5f900000 {
compatible = "socionext,uniphier-ld11-soc-glue-debug",
- "simple-mfd";
+ "simple-mfd", "syscon";
reg = <0x5f900000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
index d70929b26a2a..5dace1137cd1 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
@@ -625,7 +625,7 @@ pinctrl: pinctrl {
syscon@5f900000 {
compatible = "socionext,uniphier-ld20-soc-glue-debug",
- "simple-mfd";
+ "simple-mfd", "syscon";
reg = <0x5f900000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
index 4d200fec23fe..f62e3048d4dc 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
@@ -451,7 +451,7 @@ pinctrl: pinctrl {
syscon@5f900000 {
compatible = "socionext,uniphier-pxs3-soc-glue-debug",
- "simple-mfd";
+ "simple-mfd", "syscon";
reg = <0x5f900000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
--
2.25.1
The node names for SoC-dependent controllers and PHYs should be
generic ones according to the DT schemas.
Signed-off-by: Kunihiko Hayashi <[email protected]>
---
.../boot/dts/socionext/uniphier-ld11.dtsi | 32 +++++++--------
.../boot/dts/socionext/uniphier-ld20.dtsi | 40 +++++++++----------
.../boot/dts/socionext/uniphier-pxs3.dtsi | 40 +++++++++----------
3 files changed, 56 insertions(+), 56 deletions(-)
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
index 1c76b4375b2e..148d9092572a 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
@@ -313,12 +313,12 @@ evea_hp: endpoint {
};
};
- adamv@57920000 {
+ syscon@57920000 {
compatible = "socionext,uniphier-ld11-adamv",
"simple-mfd", "syscon";
reg = <0x57920000 0x1000>;
- adamv_rst: reset {
+ adamv_rst: reset-controller {
compatible = "socionext,uniphier-ld11-adamv-reset";
#reset-cells = <1>;
};
@@ -417,28 +417,28 @@ smpctrl@59801000 {
reg = <0x59801000 0x400>;
};
- sdctrl@59810000 {
+ syscon@59810000 {
compatible = "socionext,uniphier-ld11-sdctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x400>;
- sd_rst: reset {
+ sd_rst: reset-controller {
compatible = "socionext,uniphier-ld11-sd-reset";
#reset-cells = <1>;
};
};
- perictrl@59820000 {
+ syscon@59820000 {
compatible = "socionext,uniphier-ld11-perictrl",
"simple-mfd", "syscon";
reg = <0x59820000 0x200>;
- peri_clk: clock {
+ peri_clk: clock-controller {
compatible = "socionext,uniphier-ld11-peri-clock";
#clock-cells = <1>;
};
- peri_rst: reset {
+ peri_rst: reset-controller {
compatible = "socionext,uniphier-ld11-peri-reset";
#reset-cells = <1>;
};
@@ -511,24 +511,24 @@ usb2: usb@5a820100 {
has-transaction-translator;
};
- mioctrl@5b3e0000 {
+ syscon@5b3e0000 {
compatible = "socionext,uniphier-ld11-mioctrl",
"simple-mfd", "syscon";
reg = <0x5b3e0000 0x800>;
- mio_clk: clock {
+ mio_clk: clock-controller {
compatible = "socionext,uniphier-ld11-mio-clock";
#clock-cells = <1>;
};
- mio_rst: reset {
+ mio_rst: reset-controller {
compatible = "socionext,uniphier-ld11-mio-reset";
#reset-cells = <1>;
resets = <&sys_rst 7>;
};
};
- soc_glue: soc-glue@5f800000 {
+ soc_glue: syscon@5f800000 {
compatible = "socionext,uniphier-ld11-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
@@ -537,7 +537,7 @@ pinctrl: pinctrl {
compatible = "socionext,uniphier-ld11-pinctrl";
};
- usb-controller {
+ usb-hub {
compatible = "socionext,uniphier-ld11-usb2-phy";
#address-cells = <1>;
#size-cells = <0>;
@@ -559,7 +559,7 @@ usb_phy2: phy@2 {
};
};
- soc-glue@5f900000 {
+ syscon@5f900000 {
compatible = "socionext,uniphier-ld11-soc-glue-debug",
"simple-mfd";
#address-cells = <1>;
@@ -601,17 +601,17 @@ gic: interrupt-controller@5fe00000 {
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
- sysctrl@61840000 {
+ syscon@61840000 {
compatible = "socionext,uniphier-ld11-sysctrl",
"simple-mfd", "syscon";
reg = <0x61840000 0x10000>;
- sys_clk: clock {
+ sys_clk: clock-controller {
compatible = "socionext,uniphier-ld11-clock";
#clock-cells = <1>;
};
- sys_rst: reset {
+ sys_rst: reset-controller {
compatible = "socionext,uniphier-ld11-reset";
#reset-cells = <1>;
};
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
index 9308458f9611..c83265c9b520 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
@@ -444,12 +444,12 @@ evea_hp: endpoint {
};
};
- adamv@57920000 {
+ syscon@57920000 {
compatible = "socionext,uniphier-ld20-adamv",
"simple-mfd", "syscon";
reg = <0x57920000 0x1000>;
- adamv_rst: reset {
+ adamv_rst: reset-controller {
compatible = "socionext,uniphier-ld20-adamv-reset";
#reset-cells = <1>;
};
@@ -548,33 +548,33 @@ smpctrl@59801000 {
reg = <0x59801000 0x400>;
};
- sdctrl@59810000 {
+ syscon@59810000 {
compatible = "socionext,uniphier-ld20-sdctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x400>;
- sd_clk: clock {
+ sd_clk: clock-controller {
compatible = "socionext,uniphier-ld20-sd-clock";
#clock-cells = <1>;
};
- sd_rst: reset {
+ sd_rst: reset-controller {
compatible = "socionext,uniphier-ld20-sd-reset";
#reset-cells = <1>;
};
};
- perictrl@59820000 {
+ syscon@59820000 {
compatible = "socionext,uniphier-ld20-perictrl",
"simple-mfd", "syscon";
reg = <0x59820000 0x200>;
- peri_clk: clock {
+ peri_clk: clock-controller {
compatible = "socionext,uniphier-ld20-peri-clock";
#clock-cells = <1>;
};
- peri_rst: reset {
+ peri_rst: reset-controller {
compatible = "socionext,uniphier-ld20-peri-reset";
#reset-cells = <1>;
};
@@ -613,7 +613,7 @@ sd: mmc@5a400000 {
cap-sd-highspeed;
};
- soc_glue: soc-glue@5f800000 {
+ soc_glue: syscon@5f800000 {
compatible = "socionext,uniphier-ld20-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
@@ -623,7 +623,7 @@ pinctrl: pinctrl {
};
};
- soc-glue@5f900000 {
+ syscon@5f900000 {
compatible = "socionext,uniphier-ld20-soc-glue-debug",
"simple-mfd";
#address-cells = <1>;
@@ -709,17 +709,17 @@ gic: interrupt-controller@5fe00000 {
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
- sysctrl@61840000 {
+ syscon@61840000 {
compatible = "socionext,uniphier-ld20-sysctrl",
"simple-mfd", "syscon";
reg = <0x61840000 0x10000>;
- sys_clk: clock {
+ sys_clk: clock-controller {
compatible = "socionext,uniphier-ld20-clock";
#clock-cells = <1>;
};
- sys_rst: reset {
+ sys_rst: reset-controller {
compatible = "socionext,uniphier-ld20-reset";
#reset-cells = <1>;
};
@@ -782,7 +782,7 @@ usb-controller@65b00000 {
#size-cells = <1>;
ranges = <0 0x65b00000 0x400>;
- usb_rst: reset@0 {
+ usb_rst: reset-controller@0 {
compatible = "socionext,uniphier-ld20-usb3-reset";
reg = <0x0 0x4>;
#reset-cells = <1>;
@@ -828,7 +828,7 @@ usb_vbus3: regulator@130 {
resets = <&sys_rst 14>;
};
- usb_hsphy0: hs-phy@200 {
+ usb_hsphy0: phy@200 {
compatible = "socionext,uniphier-ld20-usb3-hsphy";
reg = <0x200 0x10>;
#phy-cells = <0>;
@@ -842,7 +842,7 @@ usb_hsphy0: hs-phy@200 {
<&usb_hs_i0>;
};
- usb_hsphy1: hs-phy@210 {
+ usb_hsphy1: phy@210 {
compatible = "socionext,uniphier-ld20-usb3-hsphy";
reg = <0x210 0x10>;
#phy-cells = <0>;
@@ -856,7 +856,7 @@ usb_hsphy1: hs-phy@210 {
<&usb_hs_i0>;
};
- usb_hsphy2: hs-phy@220 {
+ usb_hsphy2: phy@220 {
compatible = "socionext,uniphier-ld20-usb3-hsphy";
reg = <0x220 0x10>;
#phy-cells = <0>;
@@ -870,7 +870,7 @@ usb_hsphy2: hs-phy@220 {
<&usb_hs_i2>;
};
- usb_hsphy3: hs-phy@230 {
+ usb_hsphy3: phy@230 {
compatible = "socionext,uniphier-ld20-usb3-hsphy";
reg = <0x230 0x10>;
#phy-cells = <0>;
@@ -884,7 +884,7 @@ usb_hsphy3: hs-phy@230 {
<&usb_hs_i2>;
};
- usb_ssphy0: ss-phy@300 {
+ usb_ssphy0: phy@300 {
compatible = "socionext,uniphier-ld20-usb3-ssphy";
reg = <0x300 0x10>;
#phy-cells = <0>;
@@ -895,7 +895,7 @@ usb_ssphy0: ss-phy@300 {
vbus-supply = <&usb_vbus0>;
};
- usb_ssphy1: ss-phy@310 {
+ usb_ssphy1: phy@310 {
compatible = "socionext,uniphier-ld20-usb3-ssphy";
reg = <0x310 0x10>;
#phy-cells = <0>;
diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
index b0c29510a7da..dd60cc04d6fb 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
@@ -370,33 +370,33 @@ smpctrl@59801000 {
reg = <0x59801000 0x400>;
};
- sdctrl@59810000 {
+ syscon@59810000 {
compatible = "socionext,uniphier-pxs3-sdctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x400>;
- sd_clk: clock {
+ sd_clk: clock-controller {
compatible = "socionext,uniphier-pxs3-sd-clock";
#clock-cells = <1>;
};
- sd_rst: reset {
+ sd_rst: reset-controller {
compatible = "socionext,uniphier-pxs3-sd-reset";
#reset-cells = <1>;
};
};
- perictrl@59820000 {
+ syscon@59820000 {
compatible = "socionext,uniphier-pxs3-perictrl",
"simple-mfd", "syscon";
reg = <0x59820000 0x200>;
- peri_clk: clock {
+ peri_clk: clock-controller {
compatible = "socionext,uniphier-pxs3-peri-clock";
#clock-cells = <1>;
};
- peri_rst: reset {
+ peri_rst: reset-controller {
compatible = "socionext,uniphier-pxs3-peri-reset";
#reset-cells = <1>;
};
@@ -439,7 +439,7 @@ sd: mmc@5a400000 {
sd-uhs-sdr50;
};
- soc_glue: soc-glue@5f800000 {
+ soc_glue: syscon@5f800000 {
compatible = "socionext,uniphier-pxs3-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
@@ -449,7 +449,7 @@ pinctrl: pinctrl {
};
};
- soc-glue@5f900000 {
+ syscon@5f900000 {
compatible = "socionext,uniphier-pxs3-soc-glue-debug",
"simple-mfd";
#address-cells = <1>;
@@ -535,17 +535,17 @@ gic: interrupt-controller@5fe00000 {
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
- sysctrl@61840000 {
+ syscon@61840000 {
compatible = "socionext,uniphier-pxs3-sysctrl",
"simple-mfd", "syscon";
reg = <0x61840000 0x10000>;
- sys_clk: clock {
+ sys_clk: clock-controller {
compatible = "socionext,uniphier-pxs3-clock";
#clock-cells = <1>;
};
- sys_rst: reset {
+ sys_rst: reset-controller {
compatible = "socionext,uniphier-pxs3-reset";
#reset-cells = <1>;
};
@@ -707,7 +707,7 @@ usb-controller@65b00000 {
#size-cells = <1>;
ranges = <0 0x65b00000 0x400>;
- usb0_rst: reset@0 {
+ usb0_rst: reset-controller@0 {
compatible = "socionext,uniphier-pxs3-usb3-reset";
reg = <0x0 0x4>;
#reset-cells = <1>;
@@ -735,7 +735,7 @@ usb0_vbus1: regulator@110 {
resets = <&sys_rst 12>;
};
- usb0_hsphy0: hs-phy@200 {
+ usb0_hsphy0: phy@200 {
compatible = "socionext,uniphier-pxs3-usb3-hsphy";
reg = <0x200 0x10>;
#phy-cells = <0>;
@@ -749,7 +749,7 @@ usb0_hsphy0: hs-phy@200 {
<&usb_hs_i0>;
};
- usb0_hsphy1: hs-phy@210 {
+ usb0_hsphy1: phy@210 {
compatible = "socionext,uniphier-pxs3-usb3-hsphy";
reg = <0x210 0x10>;
#phy-cells = <0>;
@@ -763,7 +763,7 @@ usb0_hsphy1: hs-phy@210 {
<&usb_hs_i0>;
};
- usb0_ssphy0: ss-phy@300 {
+ usb0_ssphy0: phy@300 {
compatible = "socionext,uniphier-pxs3-usb3-ssphy";
reg = <0x300 0x10>;
#phy-cells = <0>;
@@ -774,7 +774,7 @@ usb0_ssphy0: ss-phy@300 {
vbus-supply = <&usb0_vbus0>;
};
- usb0_ssphy1: ss-phy@310 {
+ usb0_ssphy1: phy@310 {
compatible = "socionext,uniphier-pxs3-usb3-ssphy";
reg = <0x310 0x10>;
#phy-cells = <0>;
@@ -809,7 +809,7 @@ usb-controller@65d00000 {
#size-cells = <1>;
ranges = <0 0x65d00000 0x400>;
- usb1_rst: reset@0 {
+ usb1_rst: reset-controller@0 {
compatible = "socionext,uniphier-pxs3-usb3-reset";
reg = <0x0 0x4>;
#reset-cells = <1>;
@@ -837,7 +837,7 @@ usb1_vbus1: regulator@110 {
resets = <&sys_rst 13>;
};
- usb1_hsphy0: hs-phy@200 {
+ usb1_hsphy0: phy@200 {
compatible = "socionext,uniphier-pxs3-usb3-hsphy";
reg = <0x200 0x10>;
#phy-cells = <0>;
@@ -852,7 +852,7 @@ usb1_hsphy0: hs-phy@200 {
<&usb_hs_i2>;
};
- usb1_hsphy1: hs-phy@210 {
+ usb1_hsphy1: phy@210 {
compatible = "socionext,uniphier-pxs3-usb3-hsphy";
reg = <0x210 0x10>;
#phy-cells = <0>;
@@ -867,7 +867,7 @@ usb1_hsphy1: hs-phy@210 {
<&usb_hs_i2>;
};
- usb1_ssphy0: ss-phy@300 {
+ usb1_ssphy0: phy@300 {
compatible = "socionext,uniphier-pxs3-usb3-ssphy";
reg = <0x300 0x10>;
#phy-cells = <0>;
--
2.25.1
Add sociopnext,syscon-uhs-mode prpperty to the SD node to refer the handle
of the control logic node.
Signed-off-by: Kunihiko Hayashi <[email protected]>
---
arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 3 ++-
arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
index 5dace1137cd1..4e2171630272 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
@@ -548,7 +548,7 @@ smpctrl@59801000 {
reg = <0x59801000 0x400>;
};
- syscon@59810000 {
+ sdctrl: syscon@59810000 {
compatible = "socionext,uniphier-ld20-sdctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x400>;
@@ -611,6 +611,7 @@ sd: mmc@5a400000 {
resets = <&sd_rst 0>;
bus-width = <4>;
cap-sd-highspeed;
+ socionext,syscon-uhs-mode = <&sdctrl 0>;
};
soc_glue: syscon@5f800000 {
diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
index f62e3048d4dc..38ccfb46ea42 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
@@ -370,7 +370,7 @@ smpctrl@59801000 {
reg = <0x59801000 0x400>;
};
- syscon@59810000 {
+ sdctrl: syscon@59810000 {
compatible = "socionext,uniphier-pxs3-sdctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x400>;
@@ -437,6 +437,7 @@ sd: mmc@5a400000 {
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
+ socionext,syscon-uhs-mode = <&sdctrl 0>;
};
soc_glue: syscon@5f800000 {
--
2.25.1