2023-02-08 09:09:56

by Moudy Ho (何宗原)

Subject: [PATCH v6 00/12] Add support for multiple chips

Changes since v5:
- Rebase on linux-next.
- Integrate the chip configuration into a source file called "mdp_cfg_data.c"
instead of a header file.
- Fix undefined reference to __udividi3 caused by patch [1/12].
- Fix parentheses issue reported by check script.
- Fix compilation and smatch errors

Changes since v4:
- Rebase on linux-next.
- Fix potential frame size overflow in "mtk-mdp3-regs.c".
- Fix OOB in MDP3 component clocks in "mtk-mdp3-comp.*".
- Reconfigure the shared memory between MDP3 kerenl and SCP.

Changes since v3:
- Rebase on linux-next.
- In the file "mtk-mdp3-m2m.c", use the limited resolution defined by
each platform to replace the default format.
- Add platform ID in driver data, and refine shared memory structure preprocessing.
- Simplify the way to get mutex ID in function "mdp_path_subfrm_require".

Changes since v2:
- Depend on :
[1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=687004
- Split the shared memory header(mtk-img-ipi.h) by preprocessing instead, and
classify the generic parts into "mtk-mdp3-type.h", and move
chip-specific parts to"mt8183/mdp3-comp-mt8183.h".

Changes since v1:
- Depend on :
[1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=687004
- For hardware-specific structures in the shared memory header(mtk-img-ipi.h),
split the relevant functions and structure definitions.

Hi,

To support multiple chips, a chip configuration header file needs to be created
and the relevant information split and moved into it.
The v4l2-compliance test results list is as follows:

v4l2-compliance 1.23.0-4942, 32 bits, 32-bit time_t
v4l2-compliance SHA: 4cf258c24026 2022-07-28 15:43:45

Compliance test for mtk-mdp3 device /dev/video0:

Driver Info:
Driver name : mtk-mdp3
Card type : MediaTek MDP3
Bus info : platform:14001000.dma-controlle
Driver version : 6.2.0
Capabilities : 0x84204000
Video Memory-to-Memory Multiplanar
Streaming
Extended Pix Format
Device Capabilities
Device Caps : 0x04204000
Video Memory-to-Memory Multiplanar
Streaming
Extended Pix Format

Required ioctls:
test VIDIOC_QUERYCAP: OK
test invalid ioctls: OK

Allow for multiple opens:
test second /dev/video0 open: OK
test VIDIOC_QUERYCAP: OK
test VIDIOC_G/S_PRIORITY: OK
test for unlimited opens: OK

Debug ioctls:
test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
test VIDIOC_LOG_STATUS: OK (Not Supported)

Input ioctls:
test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
test VIDIOC_ENUMAUDIO: OK (Not Supported)
test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
test VIDIOC_G/S_AUDIO: OK (Not Supported)
Inputs: 0 Audio Inputs: 0 Tuners: 0

Output ioctls:
test VIDIOC_G/S_MODULATOR: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_ENUMAUDOUT: OK (Not Supported)
test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
test VIDIOC_G/S_AUDOUT: OK (Not Supported)
Outputs: 0 Audio Outputs: 0 Modulators: 0

Input/Output configuration ioctls:
test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
test VIDIOC_G/S_EDID: OK (Not Supported)

Control ioctls:
test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
test VIDIOC_QUERYCTRL: OK
test VIDIOC_G/S_CTRL: OK
test VIDIOC_G/S/TRY_EXT_CTRLS: OK
test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
Standard Controls: 4 Private Controls: 0

Format ioctls:
test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
test VIDIOC_G/S_PARM: OK (Not Supported)
test VIDIOC_G_FBUF: OK (Not Supported)
test VIDIOC_G_FMT: OK
test VIDIOC_TRY_FMT: OK
test VIDIOC_S_FMT: OK
test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
test Cropping: OK
test Composing: OK
test Scaling: OK

Codec ioctls:
test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
test VIDIOC_G_ENC_INDEX: OK (Not Supported)
test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)

Buffer ioctls:
test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
test VIDIOC_EXPBUF: OK
test Requests: OK (Not Supported)
test TIME32/64: OK

Test input 0:

Streaming ioctls:
test read/write: OK (Not Supported)
test blocking wait: OK
(snip)
test MMAP (no poll): OK
(snip)
test MMAP (select): OK
(snip)
test MMAP (epoll): OK
test USERPTR (no poll): OK (Not Supported)
test USERPTR (select): OK (Not Supported)
test DMABUF: Cannot test, specify --expbuf-device

Stream using all formats:
(snip)
Total for mtk-mdp3 device /dev/video0: 1174, Succeeded: 1174, Failed: 0, Warnings: 0

Moudy Ho (12):
media: platform: mtk-mdp3: fix potential frame size overflow in
mdp_try_fmt_mplane()
media: platform: mtk-mdp3: add files for chip configuration
media: platform: mtk-mdp3: chip config split about component settings
media: platform: mtk-mdp3: chip config split about subcomponents
media: platform: mtk-mdp3: chip config split about color format
media: platform: mtk-mdp3: chip config split about resolution
limitations
media: platform: mtk-mdp3: chip config split about pipe info
media: platform: mtk-mdp3: extend mdp_color format for compressed mode
media: platform: mtk-mdp3: dynamically allocate component clocks
media: platform: mtk-mdp3: Split general definitions used in MDP3
media: platform: mtk-mdp3: decompose hardware-related information in
shared memory
media: platform: mtk-mdp3: reconfigure shared memory

drivers/media/platform/mediatek/mdp3/Makefile | 2 +-
.../platform/mediatek/mdp3/mdp_cfg_data.c | 454 +++++++++++++++
.../platform/mediatek/mdp3/mdp_sm_mt8183.h | 144 +++++
.../platform/mediatek/mdp3/mtk-img-ipi.h | 189 +-----
.../platform/mediatek/mdp3/mtk-mdp3-cfg.h | 20 +
.../platform/mediatek/mdp3/mtk-mdp3-cmdq.c | 148 +++--
.../platform/mediatek/mdp3/mtk-mdp3-comp.c | 538 +++++++++++-------
.../platform/mediatek/mdp3/mtk-mdp3-comp.h | 24 +-
.../platform/mediatek/mdp3/mtk-mdp3-core.c | 46 +-
.../platform/mediatek/mdp3/mtk-mdp3-core.h | 18 +-
.../platform/mediatek/mdp3/mtk-mdp3-m2m.c | 28 +-
.../platform/mediatek/mdp3/mtk-mdp3-m2m.h | 1 -
.../platform/mediatek/mdp3/mtk-mdp3-regs.c | 293 +---------
.../platform/mediatek/mdp3/mtk-mdp3-regs.h | 214 +++----
.../platform/mediatek/mdp3/mtk-mdp3-type.h | 53 ++
.../platform/mediatek/mdp3/mtk-mdp3-vpu.c | 193 +++----
.../platform/mediatek/mdp3/mtk-mdp3-vpu.h | 29 +-
17 files changed, 1429 insertions(+), 965 deletions(-)
create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c
create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_sm_mt8183.h
create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-cfg.h
create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-type.h

--
2.18.0

2023-02-08 09:09:56

by Moudy Ho (何宗原)

Subject: [PATCH v6 12/12] media: platform: mtk-mdp3: reconfigure shared memory

For performance and multi-chip support, use dynamic layout instead of
statically configured pools.
Divide the shared memory into the 3 64-bit aligned layouts listed below:

vpu->param_addr -> +-----------------------------------------+
| |
| To SCP : Input frame parameters |
| (struct img_ipi_frameparam) |
| |
+-----------------------------------------+

vpu->work_addr -> +-----------------------------------------+
| |
| In SCP : Reserve for SCP calculation |
| |
+-----------------------------------------+

vpu->config_addr -> +-----------------------------------------+
| |
| From SCP : Output component config |
| (struct img_config) |
| |
+-----------------------------------------+

Signed-off-by: Moudy Ho <[email protected]>
---
.../platform/mediatek/mdp3/mdp_sm_mt8183.h | 4 +-
.../platform/mediatek/mdp3/mtk-mdp3-m2m.c | 13 +-
.../platform/mediatek/mdp3/mtk-mdp3-m2m.h | 1 -
.../platform/mediatek/mdp3/mtk-mdp3-vpu.c | 193 ++++++++----------
.../platform/mediatek/mdp3/mtk-mdp3-vpu.h | 29 +--
5 files changed, 95 insertions(+), 145 deletions(-)

diff --git a/drivers/media/platform/mediatek/mdp3/mdp_sm_mt8183.h b/drivers/media/platform/mediatek/mdp3/mdp_sm_mt8183.h
index effc75615af9..85637084520f 100644
--- a/drivers/media/platform/mediatek/mdp3/mdp_sm_mt8183.h
+++ b/drivers/media/platform/mediatek/mdp3/mdp_sm_mt8183.h
@@ -11,8 +11,8 @@

/*
* ISP-MDP generic output information
- * MD5 of the target SCP blob:
- * 6da52bdcf4bf76a0983b313e1d4745d6
+ * MD5 of the target SCP prebuild:
+ * 2d995ddb5c3b0cf26e96d6a823481886
*/

#define IMG_MAX_SUBFRAMES_8183 14
diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-m2m.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-m2m.c
index eba181fa50ad..f0a293ab0688 100644
--- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-m2m.c
+++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-m2m.c
@@ -87,14 +87,14 @@ static void mdp_m2m_device_run(void *priv)
dst_vb = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
mdp_set_dst_config(&param.outputs[0], frame, &dst_vb->vb2_buf);

- ret = mdp_vpu_process(&ctx->vpu, &param);
+ ret = mdp_vpu_process(&ctx->mdp_dev->vpu, &param);
if (ret) {
dev_err(&ctx->mdp_dev->pdev->dev,
"VPU MDP process failed: %d\n", ret);
goto worker_end;
}

- task.config = ctx->vpu.config;
+ task.config = ctx->mdp_dev->vpu.config;
task.param = &param;
task.composes[0] = &frame->compose;
task.cmdq_cb = NULL;
@@ -150,11 +150,6 @@ static int mdp_m2m_start_streaming(struct vb2_queue *q, unsigned int count)

if (!mdp_m2m_ctx_is_state_set(ctx, MDP_VPU_INIT)) {
ret = mdp_vpu_get_locked(ctx->mdp_dev);
- if (ret)
- return ret;
-
- ret = mdp_vpu_ctx_init(&ctx->vpu, &ctx->mdp_dev->vpu,
- MDP_DEV_M2M);
if (ret) {
dev_err(&ctx->mdp_dev->pdev->dev,
"VPU init failed %d\n", ret);
@@ -635,10 +630,8 @@ static int mdp_m2m_release(struct file *file)

mutex_lock(&mdp->m2m_lock);
v4l2_m2m_ctx_release(ctx->m2m_ctx);
- if (mdp_m2m_ctx_is_state_set(ctx, MDP_VPU_INIT)) {
- mdp_vpu_ctx_deinit(&ctx->vpu);
+ if (mdp_m2m_ctx_is_state_set(ctx, MDP_VPU_INIT))
mdp_vpu_put_locked(mdp);
- }

v4l2_ctrl_handler_free(&ctx->ctrl_handler);
v4l2_fh_del(&ctx->fh);
diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-m2m.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-m2m.h
index 61ddbaf1bf13..dfc59e5b3b87 100644
--- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-m2m.h
+++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-m2m.h
@@ -33,7 +33,6 @@ struct mdp_m2m_ctx {
struct v4l2_ctrl_handler ctrl_handler;
struct mdp_m2m_ctrls ctrls;
struct v4l2_m2m_ctx *m2m_ctx;
- struct mdp_vpu_ctx vpu;
u32 frame_count[MDP_M2M_MAX];

struct mdp_frameparam curr_param;
diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c
index a72bed927bb6..49fc2e9d45dd 100644
--- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c
+++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c
@@ -10,7 +10,6 @@
#include "mtk-mdp3-core.h"

#define MDP_VPU_MESSAGE_TIMEOUT 500U
-#define vpu_alloc_size 0x600000

static inline struct mdp_dev *vpu_to_mdp(struct mdp_vpu_dev *vpu)
{
@@ -19,23 +18,63 @@ static inline struct mdp_dev *vpu_to_mdp(struct mdp_vpu_dev *vpu)

static int mdp_vpu_shared_mem_alloc(struct mdp_vpu_dev *vpu)
{
- if (vpu->work && vpu->work_addr)
- return 0;
+ struct device *dev;

- vpu->work = dma_alloc_coherent(scp_get_device(vpu->scp), vpu_alloc_size,
- &vpu->work_addr, GFP_KERNEL);
+ if (IS_ERR_OR_NULL(vpu))
+ goto err_return;

- if (!vpu->work)
- return -ENOMEM;
- else
- return 0;
+ dev = scp_get_device(vpu->scp);
+
+ if (!vpu->param) {
+ vpu->param = dma_alloc_wc(dev, vpu->param_size,
+ &vpu->param_addr, GFP_KERNEL);
+ if (!vpu->param)
+ goto err_return;
+ }
+
+ if (!vpu->work) {
+ vpu->work = dma_alloc_wc(dev, vpu->work_size,
+ &vpu->work_addr, GFP_KERNEL);
+ if (!vpu->work)
+ goto err_free_param;
+ }
+
+ if (!vpu->config) {
+ vpu->config = dma_alloc_wc(dev, vpu->config_size,
+ &vpu->config_addr, GFP_KERNEL);
+ if (!vpu->config)
+ goto err_free_work;
+ }
+
+ return 0;
+
+err_free_work:
+ dma_free_wc(dev, vpu->work_size, vpu->work, vpu->work_addr);
+ vpu->work = NULL;
+err_free_param:
+ dma_free_wc(dev, vpu->param_size, vpu->param, vpu->param_addr);
+ vpu->param = NULL;
+err_return:
+ return -ENOMEM;
}

void mdp_vpu_shared_mem_free(struct mdp_vpu_dev *vpu)
{
+ struct device *dev;
+
+ if (IS_ERR_OR_NULL(vpu))
+ return;
+
+ dev = scp_get_device(vpu->scp);
+
+ if (vpu->param && vpu->param_addr)
+ dma_free_wc(dev, vpu->param_size, vpu->param, vpu->param_addr);
+
if (vpu->work && vpu->work_addr)
- dma_free_coherent(scp_get_device(vpu->scp), vpu_alloc_size,
- vpu->work, vpu->work_addr);
+ dma_free_wc(dev, vpu->work_size, vpu->work, vpu->work_addr);
+
+ if (vpu->config && vpu->config_addr)
+ dma_free_wc(dev, vpu->config_size, vpu->config, vpu->config_addr);
}

static void mdp_vpu_ipi_handle_init_ack(void *data, unsigned int len,
@@ -69,16 +108,16 @@ static void mdp_vpu_ipi_handle_frame_ack(void *data, unsigned int len,
struct img_sw_addr *addr = (struct img_sw_addr *)data;
struct img_ipi_frameparam *param =
(struct img_ipi_frameparam *)(unsigned long)addr->va;
- struct mdp_vpu_ctx *ctx =
- (struct mdp_vpu_ctx *)(unsigned long)param->drv_data;
+ struct mdp_vpu_dev *vpu =
+ (struct mdp_vpu_dev *)(unsigned long)param->drv_data;

if (param->state) {
- struct mdp_dev *mdp = vpu_to_mdp(ctx->vpu_dev);
+ struct mdp_dev *mdp = vpu_to_mdp(vpu);

dev_err(&mdp->pdev->dev, "VPU MDP failure:%d\n", param->state);
}
- ctx->vpu_dev->status = param->state;
- complete(&ctx->vpu_dev->ipi_acked);
+ vpu->status = param->state;
+ complete(&vpu->ipi_acked);
}

int mdp_vpu_register(struct mdp_dev *mdp)
@@ -157,9 +196,6 @@ int mdp_vpu_dev_init(struct mdp_vpu_dev *vpu, struct mtk_scp *scp,
struct mdp_ipi_init_msg msg = {
.drv_data = (unsigned long)vpu,
};
- size_t mem_size;
- phys_addr_t pool;
- const size_t pool_size = sizeof(struct mdp_config_pool);
struct mdp_dev *mdp = vpu_to_mdp(vpu);
int err;

@@ -172,34 +208,29 @@ int mdp_vpu_dev_init(struct mdp_vpu_dev *vpu, struct mtk_scp *scp,
goto err_work_size;
/* vpu work_size was set in mdp_vpu_ipi_handle_init_ack */

- mem_size = vpu_alloc_size;
+ mutex_lock(vpu->lock);
+ vpu->work_size = ALIGN(vpu->work_size, 64);
+ vpu->param_size = ALIGN(sizeof(struct img_ipi_frameparam), 64);
+ vpu->config_size = ALIGN(sizeof(struct img_config), 64);
err = mdp_vpu_shared_mem_alloc(vpu);
+ mutex_unlock(vpu->lock);
if (err) {
dev_err(&mdp->pdev->dev, "VPU memory alloc fail!");
goto err_mem_alloc;
}

- pool = ALIGN((uintptr_t)vpu->work + vpu->work_size, 8);
- if (pool + pool_size - (uintptr_t)vpu->work > mem_size) {
- dev_err(&mdp->pdev->dev,
- "VPU memory insufficient: %zx + %zx > %zx",
- vpu->work_size, pool_size, mem_size);
- err = -ENOMEM;
- goto err_mem_size;
- }
-
dev_dbg(&mdp->pdev->dev,
- "VPU work:%pK pa:%pad sz:%zx pool:%pa sz:%zx (mem sz:%zx)",
+ "VPU param:%pK pa:%pad sz:%zx, work:%pK pa:%pad sz:%zx, config:%pK pa:%pad sz:%zx",
+ vpu->param, &vpu->param_addr, vpu->param_size,
vpu->work, &vpu->work_addr, vpu->work_size,
- &pool, pool_size, mem_size);
- vpu->pool = (struct mdp_config_pool *)(uintptr_t)pool;
+ vpu->config, &vpu->config_addr, vpu->config_size);
+
msg.work_addr = vpu->work_addr;
msg.work_size = vpu->work_size;
err = mdp_vpu_sendmsg(vpu, SCP_IPI_MDP_INIT, &msg, sizeof(msg));
if (err)
goto err_work_size;

- memset(vpu->pool, 0, sizeof(*vpu->pool));
return 0;

err_work_size:
@@ -212,7 +243,6 @@ int mdp_vpu_dev_init(struct mdp_vpu_dev *vpu, struct mtk_scp *scp,
break;
}
return err;
-err_mem_size:
err_mem_alloc:
return err;
}
@@ -227,88 +257,31 @@ int mdp_vpu_dev_deinit(struct mdp_vpu_dev *vpu)
return mdp_vpu_sendmsg(vpu, SCP_IPI_MDP_DEINIT, &msg, sizeof(msg));
}

-static struct img_config *mdp_config_get(struct mdp_vpu_dev *vpu,
- enum mdp_config_id id, uint32_t *addr)
+int mdp_vpu_process(struct mdp_vpu_dev *vpu, struct img_ipi_frameparam *param)
{
- struct img_config *config;
-
- if (id < 0 || id >= MDP_CONFIG_POOL_SIZE)
- return ERR_PTR(-EINVAL);
+ struct mdp_dev *mdp = vpu_to_mdp(vpu);
+ struct img_sw_addr addr;

mutex_lock(vpu->lock);
- vpu->pool->cfg_count[id]++;
- config = &vpu->pool->configs[id];
- *addr = vpu->work_addr + ((uintptr_t)config - (uintptr_t)vpu->work);
- mutex_unlock(vpu->lock);
-
- return config;
-}
-
-static int mdp_config_put(struct mdp_vpu_dev *vpu,
- enum mdp_config_id id,
- const struct img_config *config)
-{
- int err = 0;
-
- if (id < 0 || id >= MDP_CONFIG_POOL_SIZE)
- return -EINVAL;
- if (vpu->lock)
- mutex_lock(vpu->lock);
- if (!vpu->pool->cfg_count[id] || config != &vpu->pool->configs[id])
- err = -EINVAL;
- else
- vpu->pool->cfg_count[id]--;
- if (vpu->lock)
+ if (mdp_vpu_shared_mem_alloc(vpu)) {
+ dev_err(&mdp->pdev->dev, "VPU memory alloc fail!");
mutex_unlock(vpu->lock);
- return err;
-}
-
-int mdp_vpu_ctx_init(struct mdp_vpu_ctx *ctx, struct mdp_vpu_dev *vpu,
- enum mdp_config_id id)
-{
- ctx->config = mdp_config_get(vpu, id, &ctx->inst_addr);
- if (IS_ERR(ctx->config)) {
- int err = PTR_ERR(ctx->config);
-
- ctx->config = NULL;
- return err;
+ return -ENOMEM;
}
- ctx->config_id = id;
- ctx->vpu_dev = vpu;
- return 0;
-}

-int mdp_vpu_ctx_deinit(struct mdp_vpu_ctx *ctx)
-{
- int err = mdp_config_put(ctx->vpu_dev, ctx->config_id, ctx->config);
+ memset(vpu->param, 0, vpu->param_size);
+ memset(vpu->work, 0, vpu->work_size);
+ memset(vpu->config, 0, vpu->config_size);

- ctx->config_id = 0;
- ctx->config = NULL;
- ctx->inst_addr = 0;
- return err;
-}
+ param->self_data.va = (unsigned long)vpu->work;
+ param->self_data.pa = vpu->work_addr;
+ param->config_data.va = (unsigned long)vpu->config;
+ param->config_data.pa = vpu->config_addr;
+ param->drv_data = (unsigned long)vpu;
+ memcpy(vpu->param, param, sizeof(*param));

-int mdp_vpu_process(struct mdp_vpu_ctx *ctx, struct img_ipi_frameparam *param)
-{
- struct mdp_vpu_dev *vpu = ctx->vpu_dev;
- struct mdp_dev *mdp = vpu_to_mdp(vpu);
- struct img_sw_addr addr;
-
- if (!ctx->vpu_dev->work || !ctx->vpu_dev->work_addr) {
- if (mdp_vpu_shared_mem_alloc(vpu)) {
- dev_err(&mdp->pdev->dev, "VPU memory alloc fail!");
- return -ENOMEM;
- }
- }
- memset((void *)ctx->vpu_dev->work, 0, ctx->vpu_dev->work_size);
- memset(ctx->config, 0, sizeof(*ctx->config));
- param->config_data.va = (unsigned long)ctx->config;
- param->config_data.pa = ctx->inst_addr;
- param->drv_data = (unsigned long)ctx;
-
- memcpy((void *)ctx->vpu_dev->work, param, sizeof(*param));
- addr.pa = ctx->vpu_dev->work_addr;
- addr.va = (uintptr_t)ctx->vpu_dev->work;
- return mdp_vpu_sendmsg(ctx->vpu_dev, SCP_IPI_MDP_FRAME,
- &addr, sizeof(addr));
+ addr.pa = vpu->param_addr;
+ addr.va = (unsigned long)vpu->param;
+ mutex_unlock(vpu->lock);
+ return mdp_vpu_sendmsg(vpu, SCP_IPI_MDP_FRAME, &addr, sizeof(addr));
}
diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.h
index 244b3a32d689..ad3551bc0730 100644
--- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.h
+++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.h
@@ -37,42 +37,27 @@ struct mdp_ipi_deinit_msg {
u32 work_addr;
} __packed;

-enum mdp_config_id {
- MDP_DEV_M2M = 0,
- MDP_CONFIG_POOL_SIZE /* ALWAYS keep at the end */
-};
-
-struct mdp_config_pool {
- u64 cfg_count[MDP_CONFIG_POOL_SIZE];
- struct img_config configs[MDP_CONFIG_POOL_SIZE];
-};
-
struct mdp_vpu_dev {
/* synchronization protect for accessing vpu working buffer info */
struct mutex *lock;
struct mtk_scp *scp;
struct completion ipi_acked;
+ void *param;
+ dma_addr_t param_addr;
+ size_t param_size;
void *work;
dma_addr_t work_addr;
size_t work_size;
- struct mdp_config_pool *pool;
+ void *config;
+ dma_addr_t config_addr;
+ size_t config_size;
u32 status;
};

-struct mdp_vpu_ctx {
- struct mdp_vpu_dev *vpu_dev;
- u32 config_id;
- struct img_config *config;
- u32 inst_addr;
-};
-
void mdp_vpu_shared_mem_free(struct mdp_vpu_dev *vpu);
int mdp_vpu_dev_init(struct mdp_vpu_dev *vpu, struct mtk_scp *scp,
struct mutex *lock /* for sync */);
int mdp_vpu_dev_deinit(struct mdp_vpu_dev *vpu);
-int mdp_vpu_ctx_init(struct mdp_vpu_ctx *ctx, struct mdp_vpu_dev *vpu,
- enum mdp_config_id id);
-int mdp_vpu_ctx_deinit(struct mdp_vpu_ctx *ctx);
-int mdp_vpu_process(struct mdp_vpu_ctx *vpu, struct img_ipi_frameparam *param);
+int mdp_vpu_process(struct mdp_vpu_dev *vpu, struct img_ipi_frameparam *param);

#endif /* __MTK_MDP3_VPU_H__ */
--
2.18.0

2023-02-08 09:10:00

by Moudy Ho (何宗原)

Subject: [PATCH v6 03/12] media: platform: mtk-mdp3: chip config split about component settings

For different chips, different types and numbers of components are
configured in the MDP3 to achieve the desired application, which will
cause ID compatibility problems in the same driver.

Subdivide the component ID into two kinds:
1. public_id (compatible with other chips)
2. inner_id (what the current chip actually owns)

In addition, the chip configuration related structures of MDP3 components
are integrated into specific file.

Signed-off-by: Moudy Ho <[email protected]>
---
.../platform/mediatek/mdp3/mdp_cfg_data.c | 145 ++++++++++++++++++
.../platform/mediatek/mdp3/mtk-mdp3-cfg.h | 8 +
.../platform/mediatek/mdp3/mtk-mdp3-cmdq.c | 4 +-
.../platform/mediatek/mdp3/mtk-mdp3-comp.c | 117 ++++++--------
.../platform/mediatek/mdp3/mtk-mdp3-comp.h | 21 ++-
.../platform/mediatek/mdp3/mtk-mdp3-core.h | 2 +
6 files changed, 223 insertions(+), 74 deletions(-)

diff --git a/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c b/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c
index 837b8202dcc7..af2e75acf119 100644
--- a/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c
+++ b/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c
@@ -4,7 +4,45 @@
* Author: Ping-Hsun Wu <[email protected]>
*/

+#include "mtk-mdp3-cfg.h"
#include "mtk-mdp3-core.h"
+#include "mtk-mdp3-comp.h"
+
+enum mt8183_mdp_comp_id {
+ /* ISP */
+ MT8183_MDP_COMP_WPEI = 0,
+ MT8183_MDP_COMP_WPEO, /* 1 */
+ MT8183_MDP_COMP_WPEI2, /* 2 */
+ MT8183_MDP_COMP_WPEO2, /* 3 */
+ MT8183_MDP_COMP_ISP_IMGI, /* 4 */
+ MT8183_MDP_COMP_ISP_IMGO, /* 5 */
+ MT8183_MDP_COMP_ISP_IMG2O, /* 6 */
+
+ /* IPU */
+ MT8183_MDP_COMP_IPUI, /* 7 */
+ MT8183_MDP_COMP_IPUO, /* 8 */
+
+ /* MDP */
+ MT8183_MDP_COMP_CAMIN, /* 9 */
+ MT8183_MDP_COMP_CAMIN2, /* 10 */
+ MT8183_MDP_COMP_RDMA0, /* 11 */
+ MT8183_MDP_COMP_AAL0, /* 12 */
+ MT8183_MDP_COMP_CCORR0, /* 13 */
+ MT8183_MDP_COMP_RSZ0, /* 14 */
+ MT8183_MDP_COMP_RSZ1, /* 15 */
+ MT8183_MDP_COMP_TDSHP0, /* 16 */
+ MT8183_MDP_COMP_COLOR0, /* 17 */
+ MT8183_MDP_COMP_PATH0_SOUT, /* 18 */
+ MT8183_MDP_COMP_PATH1_SOUT, /* 19 */
+ MT8183_MDP_COMP_WROT0, /* 20 */
+ MT8183_MDP_COMP_WDMA, /* 21 */
+
+ /* Dummy Engine */
+ MT8183_MDP_COMP_RDMA1, /* 22 */
+ MT8183_MDP_COMP_RSZ2, /* 23 */
+ MT8183_MDP_COMP_TDSHP1, /* 24 */
+ MT8183_MDP_COMP_WROT1, /* 25 */
+};

static const struct of_device_id mt8183_mdp_probe_infra[MDP_INFRA_MAX] = {
[MDP_INFRA_MMSYS] = { .compatible = "mediatek,mt8183-mmsys" },
@@ -31,8 +69,115 @@ static const u32 mt8183_mutex_idx[MDP_MAX_COMP_COUNT] = {
[MDP_COMP_CCORR0] = MUTEX_MOD_IDX_MDP_CCORR0,
};

+static const struct mdp_comp_data mt8183_mdp_comp_data[MDP_MAX_COMP_COUNT] = {
+ [MDP_COMP_WPEI] = {
+ {MDP_COMP_TYPE_WPEI, 0, MT8183_MDP_COMP_WPEI},
+ {0, 0, 0}
+ },
+ [MDP_COMP_WPEO] = {
+ {MDP_COMP_TYPE_EXTO, 2, MT8183_MDP_COMP_WPEO},
+ {0, 0, 0}
+ },
+ [MDP_COMP_WPEI2] = {
+ {MDP_COMP_TYPE_WPEI, 1, MT8183_MDP_COMP_WPEI2},
+ {0, 0, 0}
+ },
+ [MDP_COMP_WPEO2] = {
+ {MDP_COMP_TYPE_EXTO, 3, MT8183_MDP_COMP_WPEO2},
+ {0, 0, 0}
+ },
+ [MDP_COMP_ISP_IMGI] = {
+ {MDP_COMP_TYPE_IMGI, 0, MT8183_MDP_COMP_ISP_IMGI},
+ {0, 0, 4}
+ },
+ [MDP_COMP_ISP_IMGO] = {
+ {MDP_COMP_TYPE_EXTO, 0, MT8183_MDP_COMP_ISP_IMGO},
+ {0, 0, 4}
+ },
+ [MDP_COMP_ISP_IMG2O] = {
+ {MDP_COMP_TYPE_EXTO, 1, MT8183_MDP_COMP_ISP_IMG2O},
+ {0, 0, 0}
+ },
+ [MDP_COMP_CAMIN] = {
+ {MDP_COMP_TYPE_DL_PATH, 0, MT8183_MDP_COMP_CAMIN},
+ {2, 2, 1}
+ },
+ [MDP_COMP_CAMIN2] = {
+ {MDP_COMP_TYPE_DL_PATH, 1, MT8183_MDP_COMP_CAMIN2},
+ {2, 4, 1}
+ },
+ [MDP_COMP_RDMA0] = {
+ {MDP_COMP_TYPE_RDMA, 0, MT8183_MDP_COMP_RDMA0},
+ {2, 0, 0}
+ },
+ [MDP_COMP_CCORR0] = {
+ {MDP_COMP_TYPE_CCORR, 0, MT8183_MDP_COMP_CCORR0},
+ {1, 0, 0}
+ },
+ [MDP_COMP_RSZ0] = {
+ {MDP_COMP_TYPE_RSZ, 0, MT8183_MDP_COMP_RSZ0},
+ {1, 0, 0}
+ },
+ [MDP_COMP_RSZ1] = {
+ {MDP_COMP_TYPE_RSZ, 1, MT8183_MDP_COMP_RSZ1},
+ {1, 0, 0}
+ },
+ [MDP_COMP_TDSHP0] = {
+ {MDP_COMP_TYPE_TDSHP, 0, MT8183_MDP_COMP_TDSHP0},
+ {0, 0, 0}
+ },
+ [MDP_COMP_PATH0_SOUT] = {
+ {MDP_COMP_TYPE_PATH, 0, MT8183_MDP_COMP_PATH0_SOUT},
+ {0, 0, 0}
+ },
+ [MDP_COMP_PATH1_SOUT] = {
+ {MDP_COMP_TYPE_PATH, 1, MT8183_MDP_COMP_PATH1_SOUT},
+ {0, 0, 0}
+ },
+ [MDP_COMP_WROT0] = {
+ {MDP_COMP_TYPE_WROT, 0, MT8183_MDP_COMP_WROT0},
+ {1, 0, 0}
+ },
+ [MDP_COMP_WDMA] = {
+ {MDP_COMP_TYPE_WDMA, 0, MT8183_MDP_COMP_WDMA},
+ {1, 0, 0}
+ },
+};
+
const struct mtk_mdp_driver_data mt8183_mdp_driver_data = {
.mdp_probe_infra = mt8183_mdp_probe_infra,
.mdp_cfg = &mt8183_plat_cfg,
.mdp_mutex_table_idx = mt8183_mutex_idx,
+ .comp_data = mt8183_mdp_comp_data,
+ .comp_data_len = ARRAY_SIZE(mt8183_mdp_comp_data),
};
+
+s32 mdp_cfg_get_id_inner(struct mdp_dev *mdp_dev, enum mtk_mdp_comp_id id)
+{
+ if (!mdp_dev)
+ return MDP_COMP_NONE;
+ if (id <= MDP_COMP_NONE || id >= MDP_MAX_COMP_COUNT)
+ return MDP_COMP_NONE;
+
+ return mdp_dev->mdp_data->comp_data[id].match.inner_id;
+}
+
+enum mtk_mdp_comp_id mdp_cfg_get_id_public(struct mdp_dev *mdp_dev, s32 inner_id)
+{
+ enum mtk_mdp_comp_id public_id = MDP_COMP_NONE;
+ u32 i;
+
+ if (IS_ERR(mdp_dev) || !inner_id)
+ goto err_public_id;
+
+ for (i = 0; i < MDP_MAX_COMP_COUNT; i++) {
+ if (mdp_dev->mdp_data->comp_data[i].match.inner_id == inner_id) {
+ public_id = i;
+ return public_id;
+ }
+ }
+
+err_public_id:
+ dev_err(&mdp_dev->pdev->dev, "Unmapped inner id %d", inner_id);
+ return public_id;
+}
diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cfg.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cfg.h
index e0a698cba6ff..dee57cc4a954 100644
--- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cfg.h
+++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cfg.h
@@ -7,6 +7,14 @@
#ifndef __MTK_MDP3_CFG_H__
#define __MTK_MDP3_CFG_H__

+#include <linux/types.h>
+
extern const struct mtk_mdp_driver_data mt8183_mdp_driver_data;

+struct mdp_dev;
+enum mtk_mdp_comp_id;
+
+s32 mdp_cfg_get_id_inner(struct mdp_dev *mdp_dev, enum mtk_mdp_comp_id id);
+enum mtk_mdp_comp_id mdp_cfg_get_id_public(struct mdp_dev *mdp_dev, s32 id);
+
#endif /* __MTK_MDP3_CFG_H__ */
diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c
index 124c1b96e96b..dcd77f65b0e3 100644
--- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c
+++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c
@@ -48,7 +48,7 @@ static int mdp_path_subfrm_require(const struct mdp_path *path,
int id, index;

/* Decide which mutex to use based on the current pipeline */
- switch (path->comps[0].comp->id) {
+ switch (path->comps[0].comp->public_id) {
case MDP_COMP_RDMA0:
*mutex_id = MDP_PIPE_RDMA0;
break;
@@ -71,7 +71,7 @@ static int mdp_path_subfrm_require(const struct mdp_path *path,
ctx = &path->comps[index];
if (is_output_disabled(ctx->param, count))
continue;
- id = ctx->comp->id;
+ id = ctx->comp->public_id;
mtk_mutex_write_mod(mutex[*mutex_id],
data->mdp_mutex_table_idx[id], false);
}
diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c
index 7bc05f42a23c..1000b0ae3483 100644
--- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c
+++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c
@@ -8,6 +8,7 @@
#include <linux/of_platform.h>
#include <linux/of_address.h>
#include <linux/pm_runtime.h>
+#include "mtk-mdp3-cfg.h"
#include "mtk-mdp3-comp.h"
#include "mtk-mdp3-core.h"
#include "mtk-mdp3-regs.h"
@@ -32,12 +33,18 @@ __get_plat_cfg(const struct mdp_comp_ctx *ctx)
static s64 get_comp_flag(const struct mdp_comp_ctx *ctx)
{
const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx);
+ u32 rdma0, rsz1;
+
+ rdma0 = mdp_cfg_get_id_inner(ctx->comp->mdp_dev, MDP_COMP_RDMA0);
+ rsz1 = mdp_cfg_get_id_inner(ctx->comp->mdp_dev, MDP_COMP_RSZ1);
+ if (!rdma0 || !rsz1)
+ return MDP_COMP_NONE;

if (mdp_cfg && mdp_cfg->rdma_rsz1_sram_sharing)
- if (ctx->comp->id == MDP_COMP_RDMA0)
- return BIT(MDP_COMP_RDMA0) | BIT(MDP_COMP_RSZ1);
+ if (ctx->comp->inner_id == rdma0)
+ return BIT(rdma0) | BIT(rsz1);

- return BIT(ctx->comp->id);
+ return BIT(ctx->comp->inner_id);
}

static int init_rdma(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd)
@@ -45,12 +52,17 @@ static int init_rdma(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd)
const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx);
phys_addr_t base = ctx->comp->reg_base;
u8 subsys_id = ctx->comp->subsys_id;
+ s32 rdma0;
+
+ rdma0 = mdp_cfg_get_id_inner(ctx->comp->mdp_dev, MDP_COMP_RDMA0);
+ if (!rdma0)
+ return -EINVAL;

if (mdp_cfg && mdp_cfg->rdma_support_10bit) {
struct mdp_comp *prz1 = ctx->comp->mdp_dev->comp[MDP_COMP_RSZ1];

/* Disable RSZ1 */
- if (ctx->comp->id == MDP_COMP_RDMA0 && prz1)
+ if (ctx->comp->inner_id == rdma0 && prz1)
MM_REG_WRITE(cmd, subsys_id, prz1->reg_base, PRZ_ENABLE,
0x0, BIT(0));
}
@@ -578,32 +590,6 @@ static const struct mdp_comp_ops *mdp_comp_ops[MDP_COMP_TYPE_COUNT] = {
[MDP_COMP_TYPE_CCORR] = &ccorr_ops,
};

-struct mdp_comp_match {
- enum mdp_comp_type type;
- u32 alias_id;
-};
-
-static const struct mdp_comp_match mdp_comp_matches[MDP_MAX_COMP_COUNT] = {
- [MDP_COMP_WPEI] = { MDP_COMP_TYPE_WPEI, 0 },
- [MDP_COMP_WPEO] = { MDP_COMP_TYPE_EXTO, 2 },
- [MDP_COMP_WPEI2] = { MDP_COMP_TYPE_WPEI, 1 },
- [MDP_COMP_WPEO2] = { MDP_COMP_TYPE_EXTO, 3 },
- [MDP_COMP_ISP_IMGI] = { MDP_COMP_TYPE_IMGI, 0 },
- [MDP_COMP_ISP_IMGO] = { MDP_COMP_TYPE_EXTO, 0 },
- [MDP_COMP_ISP_IMG2O] = { MDP_COMP_TYPE_EXTO, 1 },
-
- [MDP_COMP_CAMIN] = { MDP_COMP_TYPE_DL_PATH, 0 },
- [MDP_COMP_CAMIN2] = { MDP_COMP_TYPE_DL_PATH, 1 },
- [MDP_COMP_RDMA0] = { MDP_COMP_TYPE_RDMA, 0 },
- [MDP_COMP_CCORR0] = { MDP_COMP_TYPE_CCORR, 0 },
- [MDP_COMP_RSZ0] = { MDP_COMP_TYPE_RSZ, 0 },
- [MDP_COMP_RSZ1] = { MDP_COMP_TYPE_RSZ, 1 },
- [MDP_COMP_PATH0_SOUT] = { MDP_COMP_TYPE_PATH, 0 },
- [MDP_COMP_PATH1_SOUT] = { MDP_COMP_TYPE_PATH, 1 },
- [MDP_COMP_WROT0] = { MDP_COMP_TYPE_WROT, 0 },
- [MDP_COMP_WDMA] = { MDP_COMP_TYPE_WDMA, 0 },
-};
-
static const struct of_device_id mdp_comp_dt_ids[] = {
{
.compatible = "mediatek,mt8183-mdp3-rdma",
@@ -635,21 +621,6 @@ static const struct of_device_id mdp_sub_comp_dt_ids[] = {
{}
};

-/* Used to describe the item order in MDP property */
-struct mdp_comp_info {
- u32 clk_num;
- u32 clk_ofst;
- u32 dts_reg_ofst;
-};
-
-static const struct mdp_comp_info mdp_comp_dt_info[MDP_MAX_COMP_COUNT] = {
- [MDP_COMP_RDMA0] = {2, 0, 0},
- [MDP_COMP_RSZ0] = {1, 0, 0},
- [MDP_COMP_WROT0] = {1, 0, 0},
- [MDP_COMP_WDMA] = {1, 0, 0},
- [MDP_COMP_CCORR0] = {1, 0, 0},
-};
-
static inline bool is_dma_capable(const enum mdp_comp_type type)
{
return (type == MDP_COMP_TYPE_RDMA ||
@@ -666,13 +637,13 @@ static inline bool is_bypass_gce_event(const enum mdp_comp_type type)
return (type == MDP_COMP_TYPE_PATH);
}

-static int mdp_comp_get_id(enum mdp_comp_type type, int alias_id)
+static int mdp_comp_get_id(struct mdp_dev *mdp, enum mdp_comp_type type, u32 alias_id)
{
int i;

- for (i = 0; i < ARRAY_SIZE(mdp_comp_matches); i++)
- if (mdp_comp_matches[i].type == type &&
- mdp_comp_matches[i].alias_id == alias_id)
+ for (i = 0; i < mdp->mdp_data->comp_data_len; i++)
+ if (mdp->mdp_data->comp_data[i].match.type == type &&
+ mdp->mdp_data->comp_data[i].match.alias_id == alias_id)
return i;
return -ENODEV;
}
@@ -686,7 +657,7 @@ int mdp_comp_clock_on(struct device *dev, struct mdp_comp *comp)
if (ret < 0) {
dev_err(dev,
"Failed to get power, err %d. type:%d id:%d\n",
- ret, comp->type, comp->id);
+ ret, comp->type, comp->inner_id);
return ret;
}
}
@@ -698,7 +669,7 @@ int mdp_comp_clock_on(struct device *dev, struct mdp_comp *comp)
if (ret) {
dev_err(dev,
"Failed to enable clk %d. type:%d id:%d\n",
- i, comp->type, comp->id);
+ i, comp->type, comp->inner_id);
goto err_revert;
}
}
@@ -752,8 +723,8 @@ void mdp_comp_clocks_off(struct device *dev, struct mdp_comp *comps, int num)
mdp_comp_clock_off(dev, &comps[i]);
}

-static int mdp_get_subsys_id(struct device *dev, struct device_node *node,
- struct mdp_comp *comp)
+static int mdp_get_subsys_id(struct mdp_dev *mdp, struct device *dev,
+ struct device_node *node, struct mdp_comp *comp)
{
struct platform_device *comp_pdev;
struct cmdq_client_reg cmdq_reg;
@@ -766,12 +737,12 @@ static int mdp_get_subsys_id(struct device *dev, struct device_node *node,
comp_pdev = of_find_device_by_node(node);

if (!comp_pdev) {
- dev_err(dev, "get comp_pdev fail! comp id=%d type=%d\n",
- comp->id, comp->type);
+ dev_err(dev, "get comp_pdev fail! comp public id=%d, inner id=%d, type=%d\n",
+ comp->public_id, comp->inner_id, comp->type);
return -ENODEV;
}

- index = mdp_comp_dt_info[comp->id].dts_reg_ofst;
+ index = mdp->mdp_data->comp_data[comp->public_id].info.dts_reg_ofst;
ret = cmdq_dev_get_client_reg(&comp_pdev->dev, &cmdq_reg, index);
if (ret != 0) {
dev_err(&comp_pdev->dev, "cmdq_dev_get_subsys fail!\n");
@@ -789,8 +760,9 @@ static void __mdp_comp_init(struct mdp_dev *mdp, struct device_node *node,
{
struct resource res;
phys_addr_t base;
- int index = mdp_comp_dt_info[comp->id].dts_reg_ofst;
+ int index;

+ index = mdp->mdp_data->comp_data[comp->public_id].info.dts_reg_ofst;
if (of_address_to_resource(node, index, &res) < 0)
base = 0L;
else
@@ -815,14 +787,15 @@ static int mdp_comp_init(struct mdp_dev *mdp, struct device_node *node,
return -EINVAL;
}

- comp->id = id;
- comp->type = mdp_comp_matches[id].type;
- comp->alias_id = mdp_comp_matches[id].alias_id;
+ comp->public_id = id;
+ comp->type = mdp->mdp_data->comp_data[id].match.type;
+ comp->inner_id = mdp->mdp_data->comp_data[id].match.inner_id;
+ comp->alias_id = mdp->mdp_data->comp_data[id].match.alias_id;
comp->ops = mdp_comp_ops[comp->type];
__mdp_comp_init(mdp, node, comp);

- clk_num = mdp_comp_dt_info[id].clk_num;
- clk_ofst = mdp_comp_dt_info[id].clk_ofst;
+ clk_num = mdp->mdp_data->comp_data[id].info.clk_num;
+ clk_ofst = mdp->mdp_data->comp_data[id].info.clk_ofst;

for (i = 0; i < clk_num; i++) {
comp->clks[i] = of_clk_get(node, i + clk_ofst);
@@ -830,7 +803,7 @@ static int mdp_comp_init(struct mdp_dev *mdp, struct device_node *node,
break;
}

- mdp_get_subsys_id(dev, node, comp);
+ mdp_get_subsys_id(mdp, dev, node, comp);

/* Set GCE SOF event */
if (is_bypass_gce_event(comp->type) ||
@@ -888,8 +861,8 @@ static struct mdp_comp *mdp_comp_create(struct mdp_dev *mdp,
mdp->comp[id] = comp;
mdp->comp[id]->mdp_dev = mdp;

- dev_dbg(dev, "%s type:%d alias:%d id:%d base:%#x regs:%p\n",
- dev->of_node->name, comp->type, comp->alias_id, id,
+ dev_dbg(dev, "%s type:%d alias:%d public id:%d inner id:%d base:%#x regs:%p\n",
+ dev->of_node->name, comp->type, comp->alias_id, id, comp->inner_id,
(u32)comp->reg_base, comp->regs);
return comp;
}
@@ -918,7 +891,7 @@ static int mdp_comp_sub_create(struct mdp_dev *mdp)

type = (enum mdp_comp_type)(uintptr_t)of_id->data;
alias_id = mdp_comp_alias_id[type];
- id = mdp_comp_get_id(type, alias_id);
+ id = mdp_comp_get_id(mdp, type, alias_id);
if (id < 0) {
dev_err(dev,
"Fail to get sub comp. id: type %d alias %d\n",
@@ -978,7 +951,7 @@ int mdp_comp_config(struct mdp_dev *mdp)

type = (enum mdp_comp_type)(uintptr_t)of_id->data;
alias_id = mdp_comp_alias_id[type];
- id = mdp_comp_get_id(type, alias_id);
+ id = mdp_comp_get_id(mdp, type, alias_id);
if (id < 0) {
dev_err(dev,
"Fail to get component id: type %d alias %d\n",
@@ -1025,16 +998,18 @@ int mdp_comp_ctx_config(struct mdp_dev *mdp, struct mdp_comp_ctx *ctx,
const struct img_ipi_frameparam *frame)
{
struct device *dev = &mdp->pdev->dev;
+ enum mtk_mdp_comp_id public_id = MDP_COMP_NONE;
int i;

- if (param->type < 0 || param->type >= MDP_MAX_COMP_COUNT) {
- dev_err(dev, "Invalid component id %d", param->type);
+ public_id = mdp_cfg_get_id_public(mdp, param->type);
+ if (public_id < 0) {
+ dev_err(dev, "Invalid component id %d", public_id);
return -EINVAL;
}

- ctx->comp = mdp->comp[param->type];
+ ctx->comp = mdp->comp[public_id];
if (!ctx->comp) {
- dev_err(dev, "Uninit component id %d", param->type);
+ dev_err(dev, "Uninit component inner id %d", param->type);
return -EINVAL;
}

diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h
index dc48f55ac4f7..3de994d7ef1c 100644
--- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h
+++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h
@@ -134,6 +134,24 @@ enum {
MDP_GCE_EVENT_MAX,
};

+struct mdp_comp_match {
+ enum mdp_comp_type type;
+ u32 alias_id;
+ s32 inner_id;
+};
+
+/* Used to describe the item order in MDP property */
+struct mdp_comp_info {
+ u32 clk_num;
+ u32 clk_ofst;
+ u32 dts_reg_ofst;
+};
+
+struct mdp_comp_data {
+ struct mdp_comp_match match;
+ struct mdp_comp_info info;
+};
+
struct mdp_comp_ops;

struct mdp_comp {
@@ -144,7 +162,8 @@ struct mdp_comp {
struct clk *clks[6];
struct device *comp_dev;
enum mdp_comp_type type;
- enum mtk_mdp_comp_id id;
+ enum mtk_mdp_comp_id public_id;
+ s32 inner_id;
u32 alias_id;
s32 gce_event[MDP_GCE_EVENT_MAX];
const struct mdp_comp_ops *ops;
diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h
index 2ef5fbc4f25a..0c398ef75616 100644
--- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h
+++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h
@@ -54,6 +54,8 @@ struct mtk_mdp_driver_data {
const struct of_device_id *mdp_probe_infra;
const struct mdp_platform_config *mdp_cfg;
const u32 *mdp_mutex_table_idx;
+ const struct mdp_comp_data *comp_data;
+ unsigned int comp_data_len;
};

struct mdp_dev {
--
2.18.0

2023-02-08 09:10:03

by Moudy Ho (何宗原)

Subject: [PATCH v6 05/12] media: platform: mtk-mdp3: chip config split about color format

Due to differences in hardware design, the supported color formats
will vary and should be integrated into specific config file.

Signed-off-by: Moudy Ho <[email protected]>
---
.../platform/mediatek/mdp3/mdp_cfg_data.c | 228 +++++++++++++++
.../platform/mediatek/mdp3/mtk-mdp3-core.h | 2 +
.../platform/mediatek/mdp3/mtk-mdp3-m2m.c | 10 +-
.../platform/mediatek/mdp3/mtk-mdp3-regs.c | 262 ++----------------
.../platform/mediatek/mdp3/mtk-mdp3-regs.h | 9 +-
5 files changed, 262 insertions(+), 249 deletions(-)

diff --git a/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c b/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c
index 159f5ecb9c1b..92e45bd72705 100644
--- a/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c
+++ b/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c
@@ -7,6 +7,7 @@
#include "mtk-mdp3-cfg.h"
#include "mtk-mdp3-core.h"
#include "mtk-mdp3-comp.h"
+#include "mtk-mdp3-regs.h"

enum mt8183_mdp_comp_id {
/* ISP */
@@ -155,6 +156,231 @@ static const struct of_device_id mt8183_sub_comp_dt_ids[] = {
{}
};

+/*
+ * All 10-bit related formats are not added in the basic format list,
+ * please add the corresponding format settings before use.
+ */
+static const struct mdp_format mt8183_formats[] = {
+ {
+ .pixelformat = V4L2_PIX_FMT_GREY,
+ .mdp_color = MDP_COLOR_GREY,
+ .depth = { 8 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_RGB565X,
+ .mdp_color = MDP_COLOR_BGR565,
+ .depth = { 16 },
+ .row_depth = { 16 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_RGB565,
+ .mdp_color = MDP_COLOR_RGB565,
+ .depth = { 16 },
+ .row_depth = { 16 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_RGB24,
+ .mdp_color = MDP_COLOR_RGB888,
+ .depth = { 24 },
+ .row_depth = { 24 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_BGR24,
+ .mdp_color = MDP_COLOR_BGR888,
+ .depth = { 24 },
+ .row_depth = { 24 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_ABGR32,
+ .mdp_color = MDP_COLOR_BGRA8888,
+ .depth = { 32 },
+ .row_depth = { 32 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_ARGB32,
+ .mdp_color = MDP_COLOR_ARGB8888,
+ .depth = { 32 },
+ .row_depth = { 32 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_UYVY,
+ .mdp_color = MDP_COLOR_UYVY,
+ .depth = { 16 },
+ .row_depth = { 16 },
+ .num_planes = 1,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_VYUY,
+ .mdp_color = MDP_COLOR_VYUY,
+ .depth = { 16 },
+ .row_depth = { 16 },
+ .num_planes = 1,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_YUYV,
+ .mdp_color = MDP_COLOR_YUYV,
+ .depth = { 16 },
+ .row_depth = { 16 },
+ .num_planes = 1,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_YVYU,
+ .mdp_color = MDP_COLOR_YVYU,
+ .depth = { 16 },
+ .row_depth = { 16 },
+ .num_planes = 1,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_YUV420,
+ .mdp_color = MDP_COLOR_I420,
+ .depth = { 12 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_YVU420,
+ .mdp_color = MDP_COLOR_YV12,
+ .depth = { 12 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV12,
+ .mdp_color = MDP_COLOR_NV12,
+ .depth = { 12 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV21,
+ .mdp_color = MDP_COLOR_NV21,
+ .depth = { 12 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV16,
+ .mdp_color = MDP_COLOR_NV16,
+ .depth = { 16 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV61,
+ .mdp_color = MDP_COLOR_NV61,
+ .depth = { 16 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV24,
+ .mdp_color = MDP_COLOR_NV24,
+ .depth = { 24 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV42,
+ .mdp_color = MDP_COLOR_NV42,
+ .depth = { 24 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_MT21C,
+ .mdp_color = MDP_COLOR_420_BLK_UFO,
+ .depth = { 8, 4 },
+ .row_depth = { 8, 8 },
+ .num_planes = 2,
+ .walign = 4,
+ .halign = 5,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_MM21,
+ .mdp_color = MDP_COLOR_420_BLK,
+ .depth = { 8, 4 },
+ .row_depth = { 8, 8 },
+ .num_planes = 2,
+ .walign = 4,
+ .halign = 5,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV12M,
+ .mdp_color = MDP_COLOR_NV12,
+ .depth = { 8, 4 },
+ .row_depth = { 8, 8 },
+ .num_planes = 2,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV21M,
+ .mdp_color = MDP_COLOR_NV21,
+ .depth = { 8, 4 },
+ .row_depth = { 8, 8 },
+ .num_planes = 2,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV16M,
+ .mdp_color = MDP_COLOR_NV16,
+ .depth = { 8, 8 },
+ .row_depth = { 8, 8 },
+ .num_planes = 2,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV61M,
+ .mdp_color = MDP_COLOR_NV61,
+ .depth = { 8, 8 },
+ .row_depth = { 8, 8 },
+ .num_planes = 2,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_YUV420M,
+ .mdp_color = MDP_COLOR_I420,
+ .depth = { 8, 2, 2 },
+ .row_depth = { 8, 4, 4 },
+ .num_planes = 3,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_YVU420M,
+ .mdp_color = MDP_COLOR_YV12,
+ .depth = { 8, 2, 2 },
+ .row_depth = { 8, 4, 4 },
+ .num_planes = 3,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }
+};
+
const struct mtk_mdp_driver_data mt8183_mdp_driver_data = {
.mdp_probe_infra = mt8183_mdp_probe_infra,
.mdp_cfg = &mt8183_plat_cfg,
@@ -162,6 +388,8 @@ const struct mtk_mdp_driver_data mt8183_mdp_driver_data = {
.comp_data = mt8183_mdp_comp_data,
.comp_data_len = ARRAY_SIZE(mt8183_mdp_comp_data),
.mdp_sub_comp_dt_ids = mt8183_sub_comp_dt_ids,
+ .format = mt8183_formats,
+ .format_len = ARRAY_SIZE(mt8183_formats),
};

s32 mdp_cfg_get_id_inner(struct mdp_dev *mdp_dev, enum mtk_mdp_comp_id id)
diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h
index 41eeba49fb42..327da00dd1fc 100644
--- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h
+++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h
@@ -57,6 +57,8 @@ struct mtk_mdp_driver_data {
const struct mdp_comp_data *comp_data;
unsigned int comp_data_len;
const struct of_device_id *mdp_sub_comp_dt_ids;
+ const struct mdp_format *format;
+ unsigned int format_len;
};

struct mdp_dev {
diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-m2m.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-m2m.c
index 5f74ea3b7a52..7c14679ffd78 100644
--- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-m2m.c
+++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-m2m.c
@@ -277,7 +277,9 @@ static int mdp_m2m_querycap(struct file *file, void *fh,
static int mdp_m2m_enum_fmt_mplane(struct file *file, void *fh,
struct v4l2_fmtdesc *f)
{
- return mdp_enum_fmt_mplane(f);
+ struct mdp_m2m_ctx *ctx = fh_to_ctx(fh);
+
+ return mdp_enum_fmt_mplane(ctx->mdp_dev, f);
}

static int mdp_m2m_g_fmt_mplane(struct file *file, void *fh,
@@ -307,7 +309,7 @@ static int mdp_m2m_s_fmt_mplane(struct file *file, void *fh,
const struct mdp_format *fmt;
struct vb2_queue *vq;

- fmt = mdp_try_fmt_mplane(f, &ctx->curr_param, ctx->id);
+ fmt = mdp_try_fmt_mplane(ctx->mdp_dev, f, &ctx->curr_param, ctx->id);
if (!fmt)
return -EINVAL;

@@ -346,7 +348,7 @@ static int mdp_m2m_try_fmt_mplane(struct file *file, void *fh,
{
struct mdp_m2m_ctx *ctx = fh_to_ctx(fh);

- if (!mdp_try_fmt_mplane(f, &ctx->curr_param, ctx->id))
+ if (!mdp_try_fmt_mplane(ctx->mdp_dev, f, &ctx->curr_param, ctx->id))
return -EINVAL;

return 0;
@@ -589,7 +591,7 @@ static int mdp_m2m_open(struct file *file)
ctx->fh.m2m_ctx = ctx->m2m_ctx;

ctx->curr_param.ctx = ctx;
- ret = mdp_frameparam_init(&ctx->curr_param);
+ ret = mdp_frameparam_init(mdp, &ctx->curr_param);
if (ret) {
dev_err(dev, "Failed to initialize mdp parameter\n");
goto err_release_m2m_ctx;
diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-regs.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-regs.c
index 36336d169bd9..c6fecb089687 100644
--- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-regs.c
+++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-regs.c
@@ -12,231 +12,6 @@
#include "mtk-mdp3-regs.h"
#include "mtk-mdp3-m2m.h"

-/*
- * All 10-bit related formats are not added in the basic format list,
- * please add the corresponding format settings before use.
- */
-static const struct mdp_format mdp_formats[] = {
- {
- .pixelformat = V4L2_PIX_FMT_GREY,
- .mdp_color = MDP_COLOR_GREY,
- .depth = { 8 },
- .row_depth = { 8 },
- .num_planes = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_RGB565X,
- .mdp_color = MDP_COLOR_BGR565,
- .depth = { 16 },
- .row_depth = { 16 },
- .num_planes = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_RGB565,
- .mdp_color = MDP_COLOR_RGB565,
- .depth = { 16 },
- .row_depth = { 16 },
- .num_planes = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_RGB24,
- .mdp_color = MDP_COLOR_RGB888,
- .depth = { 24 },
- .row_depth = { 24 },
- .num_planes = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_BGR24,
- .mdp_color = MDP_COLOR_BGR888,
- .depth = { 24 },
- .row_depth = { 24 },
- .num_planes = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_ABGR32,
- .mdp_color = MDP_COLOR_BGRA8888,
- .depth = { 32 },
- .row_depth = { 32 },
- .num_planes = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_ARGB32,
- .mdp_color = MDP_COLOR_ARGB8888,
- .depth = { 32 },
- .row_depth = { 32 },
- .num_planes = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_UYVY,
- .mdp_color = MDP_COLOR_UYVY,
- .depth = { 16 },
- .row_depth = { 16 },
- .num_planes = 1,
- .walign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_VYUY,
- .mdp_color = MDP_COLOR_VYUY,
- .depth = { 16 },
- .row_depth = { 16 },
- .num_planes = 1,
- .walign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_YUYV,
- .mdp_color = MDP_COLOR_YUYV,
- .depth = { 16 },
- .row_depth = { 16 },
- .num_planes = 1,
- .walign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_YVYU,
- .mdp_color = MDP_COLOR_YVYU,
- .depth = { 16 },
- .row_depth = { 16 },
- .num_planes = 1,
- .walign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_YUV420,
- .mdp_color = MDP_COLOR_I420,
- .depth = { 12 },
- .row_depth = { 8 },
- .num_planes = 1,
- .walign = 1,
- .halign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_YVU420,
- .mdp_color = MDP_COLOR_YV12,
- .depth = { 12 },
- .row_depth = { 8 },
- .num_planes = 1,
- .walign = 1,
- .halign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_NV12,
- .mdp_color = MDP_COLOR_NV12,
- .depth = { 12 },
- .row_depth = { 8 },
- .num_planes = 1,
- .walign = 1,
- .halign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_NV21,
- .mdp_color = MDP_COLOR_NV21,
- .depth = { 12 },
- .row_depth = { 8 },
- .num_planes = 1,
- .walign = 1,
- .halign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_NV16,
- .mdp_color = MDP_COLOR_NV16,
- .depth = { 16 },
- .row_depth = { 8 },
- .num_planes = 1,
- .walign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT,
- }, {
- .pixelformat = V4L2_PIX_FMT_NV61,
- .mdp_color = MDP_COLOR_NV61,
- .depth = { 16 },
- .row_depth = { 8 },
- .num_planes = 1,
- .walign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT,
- }, {
- .pixelformat = V4L2_PIX_FMT_NV24,
- .mdp_color = MDP_COLOR_NV24,
- .depth = { 24 },
- .row_depth = { 8 },
- .num_planes = 1,
- .flags = MDP_FMT_FLAG_OUTPUT,
- }, {
- .pixelformat = V4L2_PIX_FMT_NV42,
- .mdp_color = MDP_COLOR_NV42,
- .depth = { 24 },
- .row_depth = { 8 },
- .num_planes = 1,
- .flags = MDP_FMT_FLAG_OUTPUT,
- }, {
- .pixelformat = V4L2_PIX_FMT_MT21C,
- .mdp_color = MDP_COLOR_420_BLK_UFO,
- .depth = { 8, 4 },
- .row_depth = { 8, 8 },
- .num_planes = 2,
- .walign = 4,
- .halign = 5,
- .flags = MDP_FMT_FLAG_OUTPUT,
- }, {
- .pixelformat = V4L2_PIX_FMT_MM21,
- .mdp_color = MDP_COLOR_420_BLK,
- .depth = { 8, 4 },
- .row_depth = { 8, 8 },
- .num_planes = 2,
- .walign = 4,
- .halign = 5,
- .flags = MDP_FMT_FLAG_OUTPUT,
- }, {
- .pixelformat = V4L2_PIX_FMT_NV12M,
- .mdp_color = MDP_COLOR_NV12,
- .depth = { 8, 4 },
- .row_depth = { 8, 8 },
- .num_planes = 2,
- .walign = 1,
- .halign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_NV21M,
- .mdp_color = MDP_COLOR_NV21,
- .depth = { 8, 4 },
- .row_depth = { 8, 8 },
- .num_planes = 2,
- .walign = 1,
- .halign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_NV16M,
- .mdp_color = MDP_COLOR_NV16,
- .depth = { 8, 8 },
- .row_depth = { 8, 8 },
- .num_planes = 2,
- .walign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT,
- }, {
- .pixelformat = V4L2_PIX_FMT_NV61M,
- .mdp_color = MDP_COLOR_NV61,
- .depth = { 8, 8 },
- .row_depth = { 8, 8 },
- .num_planes = 2,
- .walign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT,
- }, {
- .pixelformat = V4L2_PIX_FMT_YUV420M,
- .mdp_color = MDP_COLOR_I420,
- .depth = { 8, 2, 2 },
- .row_depth = { 8, 4, 4 },
- .num_planes = 3,
- .walign = 1,
- .halign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_YVU420M,
- .mdp_color = MDP_COLOR_YV12,
- .depth = { 8, 2, 2 },
- .row_depth = { 8, 4, 4 },
- .num_planes = 3,
- .walign = 1,
- .halign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }
-};
-
static const struct mdp_limit mdp_def_limit = {
.out_limit = {
.wmin = 16,
@@ -256,32 +31,34 @@ static const struct mdp_limit mdp_def_limit = {
.v_scale_down_max = 128,
};

-static const struct mdp_format *mdp_find_fmt(u32 pixelformat, u32 type)
+static const struct mdp_format *mdp_find_fmt(const struct mtk_mdp_driver_data *mdp_data,
+ u32 pixelformat, u32 type)
{
u32 i, flag;

flag = V4L2_TYPE_IS_OUTPUT(type) ? MDP_FMT_FLAG_OUTPUT :
MDP_FMT_FLAG_CAPTURE;
- for (i = 0; i < ARRAY_SIZE(mdp_formats); ++i) {
- if (!(mdp_formats[i].flags & flag))
+ for (i = 0; i < mdp_data->format_len; ++i) {
+ if (!(mdp_data->format[i].flags & flag))
continue;
- if (mdp_formats[i].pixelformat == pixelformat)
- return &mdp_formats[i];
+ if (mdp_data->format[i].pixelformat == pixelformat)
+ return &mdp_data->format[i];
}
return NULL;
}

-static const struct mdp_format *mdp_find_fmt_by_index(u32 index, u32 type)
+static const struct mdp_format *mdp_find_fmt_by_index(const struct mtk_mdp_driver_data *mdp_data,
+ u32 index, u32 type)
{
u32 i, flag, num = 0;

flag = V4L2_TYPE_IS_OUTPUT(type) ? MDP_FMT_FLAG_OUTPUT :
MDP_FMT_FLAG_CAPTURE;
- for (i = 0; i < ARRAY_SIZE(mdp_formats); ++i) {
- if (!(mdp_formats[i].flags & flag))
+ for (i = 0; i < mdp_data->format_len; ++i) {
+ if (!(mdp_data->format[i].flags & flag))
continue;
if (index == num)
- return &mdp_formats[i];
+ return &mdp_data->format[i];
num++;
}
return NULL;
@@ -355,11 +132,11 @@ static int mdp_clamp_align(s32 *x, int min, int max, unsigned int align)
return 0;
}

-int mdp_enum_fmt_mplane(struct v4l2_fmtdesc *f)
+int mdp_enum_fmt_mplane(struct mdp_dev *mdp, struct v4l2_fmtdesc *f)
{
const struct mdp_format *fmt;

- fmt = mdp_find_fmt_by_index(f->index, f->type);
+ fmt = mdp_find_fmt_by_index(mdp->mdp_data, f->index, f->type);
if (!fmt)
return -EINVAL;

@@ -367,7 +144,8 @@ int mdp_enum_fmt_mplane(struct v4l2_fmtdesc *f)
return 0;
}

-const struct mdp_format *mdp_try_fmt_mplane(struct v4l2_format *f,
+const struct mdp_format *mdp_try_fmt_mplane(struct mdp_dev *mdp,
+ struct v4l2_format *f,
struct mdp_frameparam *param,
u32 ctx_id)
{
@@ -379,9 +157,9 @@ const struct mdp_format *mdp_try_fmt_mplane(struct v4l2_format *f,
u32 org_w, org_h;
unsigned int i;

- fmt = mdp_find_fmt(pix_mp->pixelformat, f->type);
+ fmt = mdp_find_fmt(mdp->mdp_data, pix_mp->pixelformat, f->type);
if (!fmt) {
- fmt = mdp_find_fmt_by_index(0, f->type);
+ fmt = mdp_find_fmt_by_index(mdp->mdp_data, 0, f->type);
if (!fmt) {
dev_dbg(dev, "%d: pixelformat %c%c%c%c invalid", ctx_id,
(pix_mp->pixelformat & 0xff),
@@ -701,7 +479,7 @@ void mdp_set_dst_config(struct img_output *out,
mdp_set_orientation(out, frame->rotation, frame->hflip, frame->vflip);
}

-int mdp_frameparam_init(struct mdp_frameparam *param)
+int mdp_frameparam_init(struct mdp_dev *mdp, struct mdp_frameparam *param)
{
struct mdp_frame *frame;

@@ -714,7 +492,7 @@ int mdp_frameparam_init(struct mdp_frameparam *param)

frame = &param->output;
frame->format.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
- frame->mdp_fmt = mdp_try_fmt_mplane(&frame->format, param, 0);
+ frame->mdp_fmt = mdp_try_fmt_mplane(mdp, &frame->format, param, 0);
frame->ycbcr_prof =
mdp_map_ycbcr_prof_mplane(&frame->format,
frame->mdp_fmt->mdp_color);
@@ -723,7 +501,7 @@ int mdp_frameparam_init(struct mdp_frameparam *param)
param->num_captures = 1;
frame = &param->captures[0];
frame->format.type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
- frame->mdp_fmt = mdp_try_fmt_mplane(&frame->format, param, 0);
+ frame->mdp_fmt = mdp_try_fmt_mplane(mdp, &frame->format, param, 0);
frame->ycbcr_prof =
mdp_map_ycbcr_prof_mplane(&frame->format,
frame->mdp_fmt->mdp_color);
diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-regs.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-regs.h
index f995e536d45f..8e91bcb094e0 100644
--- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-regs.h
+++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-regs.h
@@ -353,8 +353,11 @@ struct mdp_frameparam {
enum v4l2_quantization quant;
};

-int mdp_enum_fmt_mplane(struct v4l2_fmtdesc *f);
-const struct mdp_format *mdp_try_fmt_mplane(struct v4l2_format *f,
+struct mdp_dev;
+
+int mdp_enum_fmt_mplane(struct mdp_dev *mdp, struct v4l2_fmtdesc *f);
+const struct mdp_format *mdp_try_fmt_mplane(struct mdp_dev *mdp,
+ struct v4l2_format *f,
struct mdp_frameparam *param,
u32 ctx_id);
enum mdp_ycbcr_profile mdp_map_ycbcr_prof_mplane(struct v4l2_format *f,
@@ -368,6 +371,6 @@ void mdp_set_src_config(struct img_input *in,
struct mdp_frame *frame, struct vb2_buffer *vb);
void mdp_set_dst_config(struct img_output *out,
struct mdp_frame *frame, struct vb2_buffer *vb);
-int mdp_frameparam_init(struct mdp_frameparam *param);
+int mdp_frameparam_init(struct mdp_dev *mdp, struct mdp_frameparam *param);

#endif /* __MTK_MDP3_REGS_H__ */
--
2.18.0

2023-02-08 09:10:08

by Moudy Ho (何宗原)

Subject: [PATCH v6 11/12] media: platform: mtk-mdp3: decompose hardware-related information in shared memory

The communication between the MDP3 kernel driver and SCP is to
pass a shared memory through the cooperation of "mtk-mdp3-vpu.c" and
remoteproc driver.
The data structure of this shared memory is defined in "mtk-img-ipi.h",
as shown below:

vpu->work_addr -> +-----------------------------------------+
| |
| To SCP : Input frame parameters |
| (struct img_ipi_frameparam) |
| |
vpu->pool -> +-----------------------------------------+
| |
| From SCP : Output component config pool |
| (struct img_config) |
| |
| *struct img_config 1 |
| | |
| | |
| v |
| *struct img_config N |
| (N = MDP_CONFIG_POOL_SIZE) |
+-----------------------------------------+

One output component configuration contains the components
currently used by the pipeline, and has the register settings
that each component needs to set.

Since the quantity, type and function of components on each chip
will vary, the effect is that the size of the "struct img_config"
and its substructures will be different on each chip.
In addition, all chips will have to update their SCP firmware for
every change if the output component config structure is defined
and shared by a common header.

Therefore, all functions that operate on "struct img_config" and
its substructures must be separated by chips and so are the
relevant definations.

Signed-off-by: Moudy Ho <[email protected]>
---
.../platform/mediatek/mdp3/mdp_cfg_data.c | 2 +
.../platform/mediatek/mdp3/mdp_sm_mt8183.h | 144 +++++++
.../platform/mediatek/mdp3/mtk-img-ipi.h | 143 ++-----
.../platform/mediatek/mdp3/mtk-mdp3-cmdq.c | 121 ++++--
.../platform/mediatek/mdp3/mtk-mdp3-comp.c | 364 +++++++++++++-----
.../platform/mediatek/mdp3/mtk-mdp3-core.h | 1 +
6 files changed, 526 insertions(+), 249 deletions(-)
create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_sm_mt8183.h

diff --git a/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c b/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c
index 9d1a080d1b65..91e59bfec123 100644
--- a/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c
+++ b/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c
@@ -4,6 +4,7 @@
* Author: Ping-Hsun Wu <[email protected]>
*/

+#include "mtk-img-ipi.h"
#include "mtk-mdp3-cfg.h"
#include "mtk-mdp3-core.h"
#include "mtk-mdp3-comp.h"
@@ -408,6 +409,7 @@ static const struct mdp_pipe_info mt8183_pipe_info[] = {
};

const struct mtk_mdp_driver_data mt8183_mdp_driver_data = {
+ .mdp_plat_id = MT8183,
.mdp_probe_infra = mt8183_mdp_probe_infra,
.mdp_cfg = &mt8183_plat_cfg,
.mdp_mutex_table_idx = mt8183_mutex_idx,
diff --git a/drivers/media/platform/mediatek/mdp3/mdp_sm_mt8183.h b/drivers/media/platform/mediatek/mdp3/mdp_sm_mt8183.h
new file mode 100644
index 000000000000..effc75615af9
--- /dev/null
+++ b/drivers/media/platform/mediatek/mdp3/mdp_sm_mt8183.h
@@ -0,0 +1,144 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2023 MediaTek Inc.
+ * Author: Ping-Hsun Wu <[email protected]>
+ */
+
+#ifndef __MDP_SM_MT8183_H__
+#define __MDP_SM_MT8183_H__
+
+#include "mtk-mdp3-type.h"
+
+/*
+ * ISP-MDP generic output information
+ * MD5 of the target SCP blob:
+ * 6da52bdcf4bf76a0983b313e1d4745d6
+ */
+
+#define IMG_MAX_SUBFRAMES_8183 14
+
+struct img_comp_frame_8183 {
+ u32 output_disable:1;
+ u32 bypass:1;
+ u16 in_width;
+ u16 in_height;
+ u16 out_width;
+ u16 out_height;
+ struct img_crop crop;
+ u16 in_total_width;
+ u16 out_total_width;
+} __packed;
+
+struct img_comp_subfrm_8183 {
+ u32 tile_disable:1;
+ struct img_region in;
+ struct img_region out;
+ struct img_offset luma;
+ struct img_offset chroma;
+ s16 out_vertical; /* Output vertical index */
+ s16 out_horizontal; /* Output horizontal index */
+} __packed;
+
+struct mdp_rdma_subfrm_8183 {
+ u32 offset[IMG_MAX_PLANES];
+ u32 offset_0_p;
+ u32 src;
+ u32 clip;
+ u32 clip_ofst;
+} __packed;
+
+struct mdp_rdma_data_8183 {
+ u32 src_ctrl;
+ u32 control;
+ u32 iova[IMG_MAX_PLANES];
+ u32 iova_end[IMG_MAX_PLANES];
+ u32 mf_bkgd;
+ u32 mf_bkgd_in_pxl;
+ u32 sf_bkgd;
+ u32 ufo_dec_y;
+ u32 ufo_dec_c;
+ u32 transform;
+ struct mdp_rdma_subfrm_8183 subfrms[IMG_MAX_SUBFRAMES_8183];
+} __packed;
+
+struct mdp_rsz_subfrm_8183 {
+ u32 control2;
+ u32 src;
+ u32 clip;
+} __packed;
+
+struct mdp_rsz_data_8183 {
+ u32 coeff_step_x;
+ u32 coeff_step_y;
+ u32 control1;
+ u32 control2;
+ struct mdp_rsz_subfrm_8183 subfrms[IMG_MAX_SUBFRAMES_8183];
+} __packed;
+
+struct mdp_wrot_subfrm_8183 {
+ u32 offset[IMG_MAX_PLANES];
+ u32 src;
+ u32 clip;
+ u32 clip_ofst;
+ u32 main_buf;
+} __packed;
+
+struct mdp_wrot_data_8183 {
+ u32 iova[IMG_MAX_PLANES];
+ u32 control;
+ u32 stride[IMG_MAX_PLANES];
+ u32 mat_ctrl;
+ u32 fifo_test;
+ u32 filter;
+ struct mdp_wrot_subfrm_8183 subfrms[IMG_MAX_SUBFRAMES_8183];
+} __packed;
+
+struct mdp_wdma_subfrm_8183 {
+ u32 offset[IMG_MAX_PLANES];
+ u32 src;
+ u32 clip;
+ u32 clip_ofst;
+} __packed;
+
+struct mdp_wdma_data_8183 {
+ u32 wdma_cfg;
+ u32 iova[IMG_MAX_PLANES];
+ u32 w_in_byte;
+ u32 uv_stride;
+ struct mdp_wdma_subfrm_8183 subfrms[IMG_MAX_SUBFRAMES_8183];
+} __packed;
+
+struct isp_data_8183 {
+ u64 dl_flags; /* 1 << (enum mdp_comp_type) */
+ u32 smxi_iova[4];
+ u32 cq_idx;
+ u32 cq_iova;
+ u32 tpipe_iova[IMG_MAX_SUBFRAMES_8183];
+} __packed;
+
+struct img_compparam_8183 {
+ u16 type; /* enum mdp_comp_id */
+ u16 id; /* engine alias_id */
+ u32 input;
+ u32 outputs[IMG_MAX_HW_OUTPUTS];
+ u32 num_outputs;
+ struct img_comp_frame_8183 frame;
+ struct img_comp_subfrm_8183 subfrms[IMG_MAX_SUBFRAMES_8183];
+ u32 num_subfrms;
+ union {
+ struct mdp_rdma_data_8183 rdma;
+ struct mdp_rsz_data_8183 rsz;
+ struct mdp_wrot_data_8183 wrot;
+ struct mdp_wdma_data_8183 wdma;
+ struct isp_data_8183 isp;
+ };
+} __packed;
+
+struct img_config_8183 {
+ struct img_compparam_8183 components[IMG_MAX_COMPONENTS];
+ u32 num_components;
+ struct img_mmsys_ctrl ctrls[IMG_MAX_SUBFRAMES_8183];
+ u32 num_subfrms;
+} __packed;
+
+#endif /* __MDP_SM_MT8183_H__ */
diff --git a/drivers/media/platform/mediatek/mdp3/mtk-img-ipi.h b/drivers/media/platform/mediatek/mdp3/mtk-img-ipi.h
index f5296994137a..22b8b9a10ef7 100644
--- a/drivers/media/platform/mediatek/mdp3/mtk-img-ipi.h
+++ b/drivers/media/platform/mediatek/mdp3/mtk-img-ipi.h
@@ -8,13 +8,11 @@
#ifndef __MTK_IMG_IPI_H__
#define __MTK_IMG_IPI_H__

+#include <linux/err.h>
+#include "mdp_sm_mt8183.h"
#include "mtk-mdp3-type.h"

-/*
- * ISP-MDP generic input information
- * MD5 of the target SCP blob:
- * 6da52bdcf4bf76a0983b313e1d4745d6
- */
+/* ISP-MDP generic input information */

#define IMG_IPI_INIT 1
#define IMG_IPI_DEINIT 2
@@ -115,132 +113,37 @@ struct img_frameparam {
struct img_ipi_frameparam frameparam;
} __packed;

-/* ISP-MDP generic output information */
+/* Platform config indicator */
+#define MT8183 8183

-struct img_comp_frame {
- u32 output_disable;
- u32 bypass;
- u32 in_width;
- u32 in_height;
- u32 out_width;
- u32 out_height;
- struct img_crop crop;
- u32 in_total_width;
- u32 out_total_width;
-} __packed;
+#define CFG_CHECK(plat, p_id) ((plat) == (p_id))

-struct img_comp_subfrm {
- u32 tile_disable;
- struct img_region in;
- struct img_region out;
- struct img_offset luma;
- struct img_offset chroma;
- s32 out_vertical; /* Output vertical index */
- s32 out_horizontal; /* Output horizontal index */
-} __packed;
+#define _CFG_OFST(plat, cfg, ofst) ((void *)(&((cfg)->config_##plat) + (ofst)))
+#define CFG_OFST(plat, cfg, ofst) \
+ (IS_ERR_OR_NULL(cfg) ? NULL : _CFG_OFST(plat, cfg, ofst))

-#define IMG_MAX_SUBFRAMES 14
+#define _CFG_ADDR(plat, cfg, mem) (&((cfg)->config_##plat.mem))
+#define CFG_ADDR(plat, cfg, mem) \
+ (IS_ERR_OR_NULL(cfg) ? NULL : _CFG_ADDR(plat, cfg, mem))

-struct mdp_rdma_subfrm {
- u32 offset[IMG_MAX_PLANES];
- u32 offset_0_p;
- u32 src;
- u32 clip;
- u32 clip_ofst;
-} __packed;
+#define _CFG_GET(plat, cfg, mem) ((cfg)->config_##plat.mem)
+#define CFG_GET(plat, cfg, mem) \
+ (IS_ERR_OR_NULL(cfg) ? 0 : _CFG_GET(plat, cfg, mem))

-struct mdp_rdma_data {
- u32 src_ctrl;
- u32 control;
- u32 iova[IMG_MAX_PLANES];
- u32 iova_end[IMG_MAX_PLANES];
- u32 mf_bkgd;
- u32 mf_bkgd_in_pxl;
- u32 sf_bkgd;
- u32 ufo_dec_y;
- u32 ufo_dec_c;
- u32 transform;
- struct mdp_rdma_subfrm subfrms[IMG_MAX_SUBFRAMES];
-} __packed;
+#define _CFG_COMP(plat, comp, mem) ((comp)->comp_##plat.mem)
+#define CFG_COMP(plat, comp, mem) \
+ (IS_ERR_OR_NULL(comp) ? 0 : _CFG_COMP(plat, comp, mem))

-struct mdp_rsz_subfrm {
- u32 control2;
- u32 src;
- u32 clip;
-} __packed;
-
-struct mdp_rsz_data {
- u32 coeff_step_x;
- u32 coeff_step_y;
- u32 control1;
- u32 control2;
- struct mdp_rsz_subfrm subfrms[IMG_MAX_SUBFRAMES];
-} __packed;
-
-struct mdp_wrot_subfrm {
- u32 offset[IMG_MAX_PLANES];
- u32 src;
- u32 clip;
- u32 clip_ofst;
- u32 main_buf;
-} __packed;
-
-struct mdp_wrot_data {
- u32 iova[IMG_MAX_PLANES];
- u32 control;
- u32 stride[IMG_MAX_PLANES];
- u32 mat_ctrl;
- u32 fifo_test;
- u32 filter;
- struct mdp_wrot_subfrm subfrms[IMG_MAX_SUBFRAMES];
-} __packed;
-
-struct mdp_wdma_subfrm {
- u32 offset[IMG_MAX_PLANES];
- u32 src;
- u32 clip;
- u32 clip_ofst;
-} __packed;
-
-struct mdp_wdma_data {
- u32 wdma_cfg;
- u32 iova[IMG_MAX_PLANES];
- u32 w_in_byte;
- u32 uv_stride;
- struct mdp_wdma_subfrm subfrms[IMG_MAX_SUBFRAMES];
-} __packed;
-
-struct isp_data {
- u64 dl_flags; /* 1 << (enum mdp_comp_type) */
- u32 smxi_iova[4];
- u32 cq_idx;
- u32 cq_iova;
- u32 tpipe_iova[IMG_MAX_SUBFRAMES];
+struct img_config {
+ union {
+ struct img_config_8183 config_8183;
+ };
} __packed;

struct img_compparam {
- u32 type; /* enum mdp_comp_id */
- u32 id; /* engine alias_id */
- u32 input;
- u32 outputs[IMG_MAX_HW_OUTPUTS];
- u32 num_outputs;
- struct img_comp_frame frame;
- struct img_comp_subfrm subfrms[IMG_MAX_SUBFRAMES];
- u32 num_subfrms;
union {
- struct mdp_rdma_data rdma;
- struct mdp_rsz_data rsz;
- struct mdp_wrot_data wrot;
- struct mdp_wdma_data wdma;
- struct isp_data isp;
+ struct img_compparam_8183 comp_8183;
};
} __packed;

-struct img_config {
- struct img_compparam components[IMG_MAX_COMPONENTS];
- u32 num_components;
- struct img_mmsys_ctrl ctrls[IMG_MAX_SUBFRAMES];
- u32 num_subfrms;
-} __packed;
-
#endif /* __MTK_IMG_IPI_H__ */
diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c
index bff14e4944c5..3177592490be 100644
--- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c
+++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c
@@ -10,6 +10,7 @@
#include "mtk-mdp3-comp.h"
#include "mtk-mdp3-core.h"
#include "mtk-mdp3-m2m.h"
+#include "mtk-img-ipi.h"

#define MDP_PATH_MAX_COMPS IMG_MAX_COMPONENTS

@@ -28,24 +29,35 @@ struct mdp_path {
#define call_op(ctx, op, ...) \
(has_op(ctx, op) ? (ctx)->comp->ops->op(ctx, ##__VA_ARGS__) : 0)

-static bool is_output_disabled(const struct img_compparam *param, u32 count)
+static bool is_output_disabled(int p_id, const struct img_compparam *param, u32 count)
{
- return (count < param->num_subfrms) ?
- (param->frame.output_disable ||
- param->subfrms[count].tile_disable) :
- true;
+ u32 num = 0;
+ bool dis_output = false;
+ bool dis_tile = false;
+
+ if (CFG_CHECK(MT8183, p_id)) {
+ num = CFG_COMP(MT8183, param, num_subfrms);
+ dis_output = CFG_COMP(MT8183, param, frame.output_disable);
+ dis_tile = CFG_COMP(MT8183, param, frame.output_disable);
+ }
+
+ return (count < num) ? (dis_output || dis_tile) : true;
}

static int mdp_path_subfrm_require(const struct mdp_path *path,
struct mdp_cmdq_cmd *cmd,
s32 *mutex_id, u32 count)
{
- const struct img_config *config = path->config;
+ const int p_id = path->mdp_dev->mdp_data->mdp_plat_id;
const struct mdp_comp_ctx *ctx;
const struct mtk_mdp_driver_data *data = path->mdp_dev->mdp_data;
struct device *dev = &path->mdp_dev->pdev->dev;
struct mtk_mutex **mutex = path->mdp_dev->mdp_mutex;
int id, index;
+ u32 num_comp = 0;
+
+ if (CFG_CHECK(MT8183, p_id))
+ num_comp = CFG_GET(MT8183, path->config, num_components);

/* Decide which mutex to use based on the current pipeline */
switch (path->comps[0].comp->public_id) {
@@ -68,9 +80,9 @@ static int mdp_path_subfrm_require(const struct mdp_path *path,
*mutex_id = data->pipe_info[index].mutex_id;

/* Set mutex mod */
- for (index = 0; index < config->num_components; index++) {
+ for (index = 0; index < num_comp; index++) {
ctx = &path->comps[index];
- if (is_output_disabled(ctx->param, count))
+ if (is_output_disabled(p_id, ctx->param, count))
continue;
id = ctx->comp->public_id;
mtk_mutex_write_mod(mutex[*mutex_id],
@@ -87,11 +99,12 @@ static int mdp_path_subfrm_run(const struct mdp_path *path,
struct mdp_cmdq_cmd *cmd,
s32 *mutex_id, u32 count)
{
- const struct img_config *config = path->config;
+ const int p_id = path->mdp_dev->mdp_data->mdp_plat_id;
const struct mdp_comp_ctx *ctx;
struct device *dev = &path->mdp_dev->pdev->dev;
struct mtk_mutex **mutex = path->mdp_dev->mdp_mutex;
int index;
+ u32 num_comp = 0;
s32 event;

if (-1 == *mutex_id) {
@@ -99,11 +112,14 @@ static int mdp_path_subfrm_run(const struct mdp_path *path,
return -EINVAL;
}

+ if (CFG_CHECK(MT8183, p_id))
+ num_comp = CFG_GET(MT8183, path->config, num_components);
+
/* Wait WROT SRAM shared to DISP RDMA */
/* Clear SOF event for each engine */
- for (index = 0; index < config->num_components; index++) {
+ for (index = 0; index < num_comp; index++) {
ctx = &path->comps[index];
- if (is_output_disabled(ctx->param, count))
+ if (is_output_disabled(p_id, ctx->param, count))
continue;
event = ctx->comp->gce_event[MDP_GCE_EVENT_SOF];
if (event != MDP_GCE_NO_EVENT)
@@ -114,9 +130,9 @@ static int mdp_path_subfrm_run(const struct mdp_path *path,
mtk_mutex_enable_by_cmdq(mutex[*mutex_id], (void *)&cmd->pkt);

/* Wait SOF events and clear mutex modules (optional) */
- for (index = 0; index < config->num_components; index++) {
+ for (index = 0; index < num_comp; index++) {
ctx = &path->comps[index];
- if (is_output_disabled(ctx->param, count))
+ if (is_output_disabled(p_id, ctx->param, count))
continue;
event = ctx->comp->gce_event[MDP_GCE_EVENT_SOF];
if (event != MDP_GCE_NO_EVENT)
@@ -128,16 +144,22 @@ static int mdp_path_subfrm_run(const struct mdp_path *path,

static int mdp_path_ctx_init(struct mdp_dev *mdp, struct mdp_path *path)
{
- const struct img_config *config = path->config;
+ const int p_id = mdp->mdp_data->mdp_plat_id;
+ void *param = NULL;
int index, ret;
+ u32 num_comp = 0;

- if (config->num_components < 1)
+ if (CFG_CHECK(MT8183, p_id))
+ num_comp = CFG_GET(MT8183, path->config, num_components);
+
+ if (num_comp < 1)
return -EINVAL;

- for (index = 0; index < config->num_components; index++) {
+ for (index = 0; index < num_comp; index++) {
+ if (CFG_CHECK(MT8183, p_id))
+ param = (void *)CFG_ADDR(MT8183, path->config, components[index]);
ret = mdp_comp_ctx_config(mdp, &path->comps[index],
- &config->components[index],
- path->param);
+ param, path->param);
if (ret)
return ret;
}
@@ -148,12 +170,19 @@ static int mdp_path_ctx_init(struct mdp_dev *mdp, struct mdp_path *path)
static int mdp_path_config_subfrm(struct mdp_cmdq_cmd *cmd,
struct mdp_path *path, u32 count)
{
- const struct img_config *config = path->config;
- const struct img_mmsys_ctrl *ctrl = &config->ctrls[count];
+ const int p_id = path->mdp_dev->mdp_data->mdp_plat_id;
+ const struct img_mmsys_ctrl *ctrl = NULL;
const struct img_mux *set;
struct mdp_comp_ctx *ctx;
s32 mutex_id;
int index, ret;
+ u32 num_comp = 0;
+
+ if (CFG_CHECK(MT8183, p_id))
+ num_comp = CFG_GET(MT8183, path->config, num_components);
+
+ if (CFG_CHECK(MT8183, p_id))
+ ctrl = CFG_ADDR(MT8183, path->config, ctrls[count]);

/* Acquire components */
ret = mdp_path_subfrm_require(path, cmd, &mutex_id, count);
@@ -166,9 +195,9 @@ static int mdp_path_config_subfrm(struct mdp_cmdq_cmd *cmd,
set->value, 0xFFFFFFFF);
}
/* Config sub-frame information */
- for (index = (config->num_components - 1); index >= 0; index--) {
+ for (index = (num_comp - 1); index >= 0; index--) {
ctx = &path->comps[index];
- if (is_output_disabled(ctx->param, count))
+ if (is_output_disabled(p_id, ctx->param, count))
continue;
ret = call_op(ctx, config_subfrm, cmd, count);
if (ret)
@@ -179,16 +208,16 @@ static int mdp_path_config_subfrm(struct mdp_cmdq_cmd *cmd,
if (ret)
return ret;
/* Wait components done */
- for (index = 0; index < config->num_components; index++) {
+ for (index = 0; index < num_comp; index++) {
ctx = &path->comps[index];
- if (is_output_disabled(ctx->param, count))
+ if (is_output_disabled(p_id, ctx->param, count))
continue;
ret = call_op(ctx, wait_comp_event, cmd);
if (ret)
return ret;
}
/* Advance to the next sub-frame */
- for (index = 0; index < config->num_components; index++) {
+ for (index = 0; index < num_comp; index++) {
ctx = &path->comps[index];
ret = call_op(ctx, advance_subfrm, cmd, count);
if (ret)
@@ -207,23 +236,35 @@ static int mdp_path_config_subfrm(struct mdp_cmdq_cmd *cmd,
static int mdp_path_config(struct mdp_dev *mdp, struct mdp_cmdq_cmd *cmd,
struct mdp_path *path)
{
- const struct img_config *config = path->config;
+ const int p_id = mdp->mdp_data->mdp_plat_id;
struct mdp_comp_ctx *ctx;
int index, count, ret;
+ u32 num_comp = 0;
+ u32 num_sub = 0;
+
+ if (CFG_CHECK(MT8183, p_id))
+ num_comp = CFG_GET(MT8183, path->config, num_components);
+
+ if (CFG_CHECK(MT8183, p_id))
+ num_sub = CFG_GET(MT8183, path->config, num_subfrms);

/* Config path frame */
/* Reset components */
- for (index = 0; index < config->num_components; index++) {
+ for (index = 0; index < num_comp; index++) {
ctx = &path->comps[index];
ret = call_op(ctx, init_comp, cmd);
if (ret)
return ret;
}
/* Config frame mode */
- for (index = 0; index < config->num_components; index++) {
- const struct v4l2_rect *compose =
- path->composes[ctx->param->outputs[0]];
+ for (index = 0; index < num_comp; index++) {
+ const struct v4l2_rect *compose;
+ u32 out = 0;
+
+ if (CFG_CHECK(MT8183, p_id))
+ out = CFG_COMP(MT8183, ctx->param, outputs[0]);

+ compose = path->composes[out];
ctx = &path->comps[index];
ret = call_op(ctx, config_frame, cmd, compose);
if (ret)
@@ -231,13 +272,13 @@ static int mdp_path_config(struct mdp_dev *mdp, struct mdp_cmdq_cmd *cmd,
}

/* Config path sub-frames */
- for (count = 0; count < config->num_subfrms; count++) {
+ for (count = 0; count < num_sub; count++) {
ret = mdp_path_config_subfrm(cmd, path, count);
if (ret)
return ret;
}
/* Post processing information */
- for (index = 0; index < config->num_components; index++) {
+ for (index = 0; index < num_comp; index++) {
ctx = &path->comps[index];
ret = call_op(ctx, post_process, cmd);
if (ret)
@@ -361,7 +402,9 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param)
struct mdp_cmdq_cmd *cmd = NULL;
struct mdp_comp *comps = NULL;
struct device *dev = &mdp->pdev->dev;
+ const int p_id = mdp->mdp_data->mdp_plat_id;
int i, ret;
+ u32 num_comp = 0;

atomic_inc(&mdp->job_count);
if (atomic_read(&mdp->suspended)) {
@@ -379,8 +422,13 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param)
if (ret)
goto err_free_cmd;

- comps = kcalloc(param->config->num_components, sizeof(*comps),
- GFP_KERNEL);
+ if (CFG_CHECK(MT8183, p_id)) {
+ num_comp = CFG_GET(MT8183, param->config, num_components);
+ } else {
+ ret = -EINVAL;
+ goto err_destroy_pkt;
+ }
+ comps = kcalloc(num_comp, sizeof(*comps), GFP_KERNEL);
if (!comps) {
ret = -ENOMEM;
goto err_destroy_pkt;
@@ -412,7 +460,6 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param)
path->composes[i] = param->composes[i] ?
param->composes[i] : &path->bounds[i];
}
-
ret = mdp_path_ctx_init(mdp, path);
if (ret) {
dev_err(dev, "mdp_path_ctx_init error\n");
@@ -426,7 +473,7 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param)
}
cmdq_pkt_finalize(&cmd->pkt);

- for (i = 0; i < param->config->num_components; i++)
+ for (i = 0; i < num_comp; i++)
memcpy(&comps[i], path->comps[i].comp,
sizeof(struct mdp_comp));

@@ -435,7 +482,7 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param)
cmd->user_cmdq_cb = param->cmdq_cb;
cmd->user_cb_data = param->cb_data;
cmd->comps = comps;
- cmd->num_comps = param->config->num_components;
+ cmd->num_comps = num_comp;
cmd->mdp_ctx = param->mdp_ctx;

ret = mdp_comp_clocks_on(&mdp->pdev->dev, cmd->comps, cmd->num_comps);
diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c
index d9963f265a07..75c92e282fa2 100644
--- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c
+++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c
@@ -20,6 +20,7 @@
#include "mdp_reg_wdma.h"

static u32 mdp_comp_alias_id[MDP_COMP_TYPE_COUNT];
+static int p_id;

static inline const struct mdp_platform_config *
__get_plat_cfg(const struct mdp_comp_ctx *ctx)
@@ -78,13 +79,13 @@ static int config_rdma_frame(struct mdp_comp_ctx *ctx,
struct mdp_cmdq_cmd *cmd,
const struct v4l2_rect *compose)
{
- const struct mdp_rdma_data *rdma = &ctx->param->rdma;
const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx);
u32 colorformat = ctx->input->buffer.format.colorformat;
bool block10bit = MDP_COLOR_IS_10BIT_PACKED(colorformat);
bool en_ufo = MDP_COLOR_IS_UFP(colorformat);
phys_addr_t base = ctx->comp->reg_base;
u8 subsys_id = ctx->comp->subsys_id;
+ u32 reg = 0;

if (mdp_cfg && mdp_cfg->rdma_support_10bit) {
if (block10bit)
@@ -102,49 +103,78 @@ static int config_rdma_frame(struct mdp_comp_ctx *ctx,
0x00030071);

/* Setup source frame info */
- MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_CON, rdma->src_ctrl,
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, rdma.src_ctrl);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_CON, reg,
0x03C8FE0F);

if (mdp_cfg)
if (mdp_cfg->rdma_support_10bit && en_ufo) {
/* Setup source buffer base */
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, rdma.ufo_dec_y);
MM_REG_WRITE(cmd, subsys_id,
base, MDP_RDMA_UFO_DEC_LENGTH_BASE_Y,
- rdma->ufo_dec_y, 0xFFFFFFFF);
+ reg, 0xFFFFFFFF);
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, rdma.ufo_dec_c);
MM_REG_WRITE(cmd, subsys_id,
base, MDP_RDMA_UFO_DEC_LENGTH_BASE_C,
- rdma->ufo_dec_c, 0xFFFFFFFF);
+ reg, 0xFFFFFFFF);
/* Set 10bit source frame pitch */
- if (block10bit)
+ if (block10bit) {
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, rdma.mf_bkgd_in_pxl);
MM_REG_WRITE(cmd, subsys_id,
base, MDP_RDMA_MF_BKGD_SIZE_IN_PXL,
- rdma->mf_bkgd_in_pxl, 0x001FFFFF);
+ reg, 0x001FFFFF);
+ }
}

- MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_CON, rdma->control,
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, rdma.control);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_CON, reg,
0x1110);
/* Setup source buffer base */
- MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_0, rdma->iova[0],
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, rdma.iova[0]);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_0, reg,
0xFFFFFFFF);
- MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_1, rdma->iova[1],
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, rdma.iova[1]);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_1, reg,
0xFFFFFFFF);
- MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_2, rdma->iova[2],
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, rdma.iova[2]);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_2, reg,
0xFFFFFFFF);
/* Setup source buffer end */
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, rdma.iova_end[0]);
MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_END_0,
- rdma->iova_end[0], 0xFFFFFFFF);
+ reg, 0xFFFFFFFF);
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, rdma.iova_end[1]);
MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_END_1,
- rdma->iova_end[1], 0xFFFFFFFF);
+ reg, 0xFFFFFFFF);
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, rdma.iova_end[2]);
MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_END_2,
- rdma->iova_end[2], 0xFFFFFFFF);
+ reg, 0xFFFFFFFF);
/* Setup source frame pitch */
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, rdma.mf_bkgd);
MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_BKGD_SIZE_IN_BYTE,
- rdma->mf_bkgd, 0x001FFFFF);
+ reg, 0x001FFFFF);
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, rdma.sf_bkgd);
MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SF_BKGD_SIZE_IN_BYTE,
- rdma->sf_bkgd, 0x001FFFFF);
+ reg, 0x001FFFFF);
/* Setup color transform */
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, rdma.transform);
MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_TRANSFORM_0,
- rdma->transform, 0x0F110000);
+ reg, 0x0F110000);

return 0;
}
@@ -152,47 +182,67 @@ static int config_rdma_frame(struct mdp_comp_ctx *ctx,
static int config_rdma_subfrm(struct mdp_comp_ctx *ctx,
struct mdp_cmdq_cmd *cmd, u32 index)
{
- const struct mdp_rdma_subfrm *subfrm = &ctx->param->rdma.subfrms[index];
- const struct img_comp_subfrm *csf = &ctx->param->subfrms[index];
const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx);
u32 colorformat = ctx->input->buffer.format.colorformat;
bool block10bit = MDP_COLOR_IS_10BIT_PACKED(colorformat);
bool en_ufo = MDP_COLOR_IS_UFP(colorformat);
phys_addr_t base = ctx->comp->reg_base;
u8 subsys_id = ctx->comp->subsys_id;
+ u32 csf_l = 0, csf_r = 0;
+ u32 reg = 0;

/* Enable RDMA */
MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_EN, BIT(0), BIT(0));

/* Set Y pixel offset */
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset[0]);
MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_0,
- subfrm->offset[0], 0xFFFFFFFF);
+ reg, 0xFFFFFFFF);

/* Set 10bit UFO mode */
- if (mdp_cfg)
- if (mdp_cfg->rdma_support_10bit && block10bit && en_ufo)
+ if (mdp_cfg) {
+ if (mdp_cfg->rdma_support_10bit && block10bit && en_ufo) {
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset_0_p);
MM_REG_WRITE(cmd, subsys_id, base,
MDP_RDMA_SRC_OFFSET_0_P,
- subfrm->offset_0_p, 0xFFFFFFFF);
+ reg, 0xFFFFFFFF);
+ }
+ }

/* Set U pixel offset */
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset[1]);
MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_1,
- subfrm->offset[1], 0xFFFFFFFF);
+ reg, 0xFFFFFFFF);
/* Set V pixel offset */
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset[2]);
MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_2,
- subfrm->offset[2], 0xFFFFFFFF);
+ reg, 0xFFFFFFFF);
/* Set source size */
- MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_SRC_SIZE, subfrm->src,
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].src);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_SRC_SIZE, reg,
0x1FFF1FFF);
/* Set target size */
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].clip);
MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_CLIP_SIZE,
- subfrm->clip, 0x1FFF1FFF);
+ reg, 0x1FFF1FFF);
/* Set crop offset */
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].clip_ofst);
MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_OFFSET_1,
- subfrm->clip_ofst, 0x003F001F);
+ reg, 0x003F001F);

+ if (CFG_CHECK(MT8183, p_id)) {
+ csf_l = CFG_COMP(MT8183, ctx->param, subfrms[index].in.left);
+ csf_r = CFG_COMP(MT8183, ctx->param, subfrms[index].in.right);
+ }
if (mdp_cfg && mdp_cfg->rdma_upsample_repeat_only)
- if ((csf->in.right - csf->in.left + 1) > 320)
+ if ((csf_r - csf_l + 1) > 320)
MM_REG_WRITE(cmd, subsys_id, base,
MDP_RDMA_RESV_DUMMY_0, BIT(2), BIT(2));

@@ -240,63 +290,97 @@ static int config_rsz_frame(struct mdp_comp_ctx *ctx,
struct mdp_cmdq_cmd *cmd,
const struct v4l2_rect *compose)
{
- const struct mdp_rsz_data *rsz = &ctx->param->rsz;
phys_addr_t base = ctx->comp->reg_base;
u8 subsys_id = ctx->comp->subsys_id;
+ bool bypass = FALSE;
+ u32 reg = 0;

- if (ctx->param->frame.bypass) {
+ if (CFG_CHECK(MT8183, p_id))
+ bypass = CFG_COMP(MT8183, ctx->param, frame.bypass);
+
+ if (bypass) {
/* Disable RSZ */
MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, 0x0, BIT(0));
return 0;
}

- MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_1, rsz->control1,
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, rsz.control1);
+ MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_1, reg,
0x03FFFDF3);
- MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_2, rsz->control2,
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, rsz.control2);
+ MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_2, reg,
0x0FFFC290);
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, rsz.coeff_step_x);
MM_REG_WRITE(cmd, subsys_id, base, PRZ_HORIZONTAL_COEFF_STEP,
- rsz->coeff_step_x, 0x007FFFFF);
+ reg, 0x007FFFFF);
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, rsz.coeff_step_y);
MM_REG_WRITE(cmd, subsys_id, base, PRZ_VERTICAL_COEFF_STEP,
- rsz->coeff_step_y, 0x007FFFFF);
+ reg, 0x007FFFFF);
return 0;
}

static int config_rsz_subfrm(struct mdp_comp_ctx *ctx,
struct mdp_cmdq_cmd *cmd, u32 index)
{
- const struct mdp_rsz_subfrm *subfrm = &ctx->param->rsz.subfrms[index];
- const struct img_comp_subfrm *csf = &ctx->param->subfrms[index];
const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx);
phys_addr_t base = ctx->comp->reg_base;
u8 subsys_id = ctx->comp->subsys_id;
+ u32 csf_l = 0, csf_r = 0;
+ u32 reg = 0;

- MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_2, subfrm->control2,
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, rsz.subfrms[index].control2);
+ MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_2, reg,
0x00003800);
- MM_REG_WRITE(cmd, subsys_id, base, PRZ_INPUT_IMAGE, subfrm->src,
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, rsz.subfrms[index].src);
+ MM_REG_WRITE(cmd, subsys_id, base, PRZ_INPUT_IMAGE, reg,
0xFFFFFFFF);

+ if (CFG_CHECK(MT8183, p_id)) {
+ csf_l = CFG_COMP(MT8183, ctx->param, subfrms[index].in.left);
+ csf_r = CFG_COMP(MT8183, ctx->param, subfrms[index].in.right);
+ }
if (mdp_cfg && mdp_cfg->rsz_disable_dcm_small_sample)
- if ((csf->in.right - csf->in.left + 1) <= 16)
+ if ((csf_r - csf_l + 1) <= 16)
MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_1,
BIT(27), BIT(27));

+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.left);
MM_REG_WRITE(cmd, subsys_id, base, PRZ_LUMA_HORIZONTAL_INTEGER_OFFSET,
- csf->luma.left, 0xFFFF);
+ reg, 0xFFFF);
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.left_subpix);
MM_REG_WRITE(cmd, subsys_id,
base, PRZ_LUMA_HORIZONTAL_SUBPIXEL_OFFSET,
- csf->luma.left_subpix, 0x1FFFFF);
+ reg, 0x1FFFFF);
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.top);
MM_REG_WRITE(cmd, subsys_id, base, PRZ_LUMA_VERTICAL_INTEGER_OFFSET,
- csf->luma.top, 0xFFFF);
+ reg, 0xFFFF);
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.top_subpix);
MM_REG_WRITE(cmd, subsys_id, base, PRZ_LUMA_VERTICAL_SUBPIXEL_OFFSET,
- csf->luma.top_subpix, 0x1FFFFF);
+ reg, 0x1FFFFF);
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, subfrms[index].chroma.left);
MM_REG_WRITE(cmd, subsys_id,
base, PRZ_CHROMA_HORIZONTAL_INTEGER_OFFSET,
- csf->chroma.left, 0xFFFF);
+ reg, 0xFFFF);
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, subfrms[index].chroma.left_subpix);
MM_REG_WRITE(cmd, subsys_id,
base, PRZ_CHROMA_HORIZONTAL_SUBPIXEL_OFFSET,
- csf->chroma.left_subpix, 0x1FFFFF);
+ reg, 0x1FFFFF);

- MM_REG_WRITE(cmd, subsys_id, base, PRZ_OUTPUT_IMAGE, subfrm->clip,
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, rsz.subfrms[index].clip);
+ MM_REG_WRITE(cmd, subsys_id, base, PRZ_OUTPUT_IMAGE, reg,
0xFFFFFFFF);

return 0;
@@ -308,11 +392,16 @@ static int advance_rsz_subfrm(struct mdp_comp_ctx *ctx,
const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx);

if (mdp_cfg && mdp_cfg->rsz_disable_dcm_small_sample) {
- const struct img_comp_subfrm *csf = &ctx->param->subfrms[index];
phys_addr_t base = ctx->comp->reg_base;
u8 subsys_id = ctx->comp->subsys_id;
+ u32 csf_l = 0, csf_r = 0;

- if ((csf->in.right - csf->in.left + 1) <= 16)
+ if (CFG_CHECK(MT8183, p_id)) {
+ csf_l = CFG_COMP(MT8183, ctx->param, subfrms[index].in.left);
+ csf_r = CFG_COMP(MT8183, ctx->param, subfrms[index].in.right);
+ }
+
+ if ((csf_r - csf_l + 1) <= 16)
MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_1, 0x0,
BIT(27));
}
@@ -345,31 +434,47 @@ static int config_wrot_frame(struct mdp_comp_ctx *ctx,
struct mdp_cmdq_cmd *cmd,
const struct v4l2_rect *compose)
{
- const struct mdp_wrot_data *wrot = &ctx->param->wrot;
const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx);
phys_addr_t base = ctx->comp->reg_base;
u8 subsys_id = ctx->comp->subsys_id;
+ u32 reg = 0;

/* Write frame base address */
- MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR, wrot->iova[0],
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, wrot.iova[0]);
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR, reg,
0xFFFFFFFF);
- MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR_C, wrot->iova[1],
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, wrot.iova[1]);
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR_C, reg,
0xFFFFFFFF);
- MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR_V, wrot->iova[2],
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, wrot.iova[2]);
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR_V, reg,
0xFFFFFFFF);
/* Write frame related registers */
- MM_REG_WRITE(cmd, subsys_id, base, VIDO_CTRL, wrot->control,
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, wrot.control);
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_CTRL, reg,
0xF131510F);
/* Write frame Y pitch */
- MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE, wrot->stride[0],
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, wrot.stride[0]);
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE, reg,
0x0000FFFF);
/* Write frame UV pitch */
- MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE_C, wrot->stride[1],
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, wrot.stride[1]);
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE_C, reg,
0xFFFF);
- MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE_V, wrot->stride[2],
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, wrot.stride[2]);
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE_V, reg,
0xFFFF);
/* Write matrix control */
- MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAT_CTRL, wrot->mat_ctrl, 0xF3);
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, wrot.mat_ctrl);
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAT_CTRL, reg, 0xF3);

/* Set the fixed ALPHA as 0xFF */
MM_REG_WRITE(cmd, subsys_id, base, VIDO_DITHER, 0xFF000000,
@@ -377,13 +482,18 @@ static int config_wrot_frame(struct mdp_comp_ctx *ctx,
/* Set VIDO_EOL_SEL */
MM_REG_WRITE(cmd, subsys_id, base, VIDO_RSV_1, BIT(31), BIT(31));
/* Set VIDO_FIFO_TEST */
- if (wrot->fifo_test != 0)
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, wrot.fifo_test);
+ if (reg != 0)
MM_REG_WRITE(cmd, subsys_id, base, VIDO_FIFO_TEST,
- wrot->fifo_test, 0xFFF);
+ reg, 0xFFF);
/* Filter enable */
- if (mdp_cfg && mdp_cfg->wrot_filter_constraint)
+ if (mdp_cfg && mdp_cfg->wrot_filter_constraint) {
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, wrot.filter);
MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE,
- wrot->filter, 0x77);
+ reg, 0x77);
+ }

return 0;
}
@@ -391,30 +501,44 @@ static int config_wrot_frame(struct mdp_comp_ctx *ctx,
static int config_wrot_subfrm(struct mdp_comp_ctx *ctx,
struct mdp_cmdq_cmd *cmd, u32 index)
{
- const struct mdp_wrot_subfrm *subfrm = &ctx->param->wrot.subfrms[index];
phys_addr_t base = ctx->comp->reg_base;
u8 subsys_id = ctx->comp->subsys_id;
+ u32 reg = 0;

/* Write Y pixel offset */
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].offset[0]);
MM_REG_WRITE(cmd, subsys_id, base, VIDO_OFST_ADDR,
- subfrm->offset[0], 0x0FFFFFFF);
+ reg, 0x0FFFFFFF);
/* Write U pixel offset */
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].offset[1]);
MM_REG_WRITE(cmd, subsys_id, base, VIDO_OFST_ADDR_C,
- subfrm->offset[1], 0x0FFFFFFF);
+ reg, 0x0FFFFFFF);
/* Write V pixel offset */
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].offset[2]);
MM_REG_WRITE(cmd, subsys_id, base, VIDO_OFST_ADDR_V,
- subfrm->offset[2], 0x0FFFFFFF);
+ reg, 0x0FFFFFFF);
/* Write source size */
- MM_REG_WRITE(cmd, subsys_id, base, VIDO_IN_SIZE, subfrm->src,
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].src);
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_IN_SIZE, reg,
0x1FFF1FFF);
/* Write target size */
- MM_REG_WRITE(cmd, subsys_id, base, VIDO_TAR_SIZE, subfrm->clip,
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].clip);
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_TAR_SIZE, reg,
0x1FFF1FFF);
- MM_REG_WRITE(cmd, subsys_id, base, VIDO_CROP_OFST, subfrm->clip_ofst,
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].clip_ofst);
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_CROP_OFST, reg,
0x1FFF1FFF);

+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].main_buf);
MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE,
- subfrm->main_buf, 0x1FFF7F00);
+ reg, 0x1FFF7F00);

/* Enable WROT */
MM_REG_WRITE(cmd, subsys_id, base, VIDO_ROT_EN, BIT(0), BIT(0));
@@ -468,29 +592,41 @@ static int config_wdma_frame(struct mdp_comp_ctx *ctx,
struct mdp_cmdq_cmd *cmd,
const struct v4l2_rect *compose)
{
- const struct mdp_wdma_data *wdma = &ctx->param->wdma;
phys_addr_t base = ctx->comp->reg_base;
u8 subsys_id = ctx->comp->subsys_id;
+ u32 reg = 0;

MM_REG_WRITE(cmd, subsys_id, base, WDMA_BUF_CON2, 0x10101050,
0xFFFFFFFF);

/* Setup frame information */
- MM_REG_WRITE(cmd, subsys_id, base, WDMA_CFG, wdma->wdma_cfg,
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, wdma.wdma_cfg);
+ MM_REG_WRITE(cmd, subsys_id, base, WDMA_CFG, reg,
0x0F01B8F0);
/* Setup frame base address */
- MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_ADDR, wdma->iova[0],
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, wdma.iova[0]);
+ MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_ADDR, reg,
0xFFFFFFFF);
- MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_U_ADDR, wdma->iova[1],
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, wdma.iova[1]);
+ MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_U_ADDR, reg,
0xFFFFFFFF);
- MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_V_ADDR, wdma->iova[2],
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, wdma.iova[2]);
+ MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_V_ADDR, reg,
0xFFFFFFFF);
/* Setup Y pitch */
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, wdma.w_in_byte);
MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_W_IN_BYTE,
- wdma->w_in_byte, 0x0000FFFF);
+ reg, 0x0000FFFF);
/* Setup UV pitch */
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, wdma.uv_stride);
MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_UV_PITCH,
- wdma->uv_stride, 0x0000FFFF);
+ reg, 0x0000FFFF);
/* Set the fixed ALPHA as 0xFF */
MM_REG_WRITE(cmd, subsys_id, base, WDMA_ALPHA, 0x800000FF,
0x800000FF);
@@ -501,27 +637,39 @@ static int config_wdma_frame(struct mdp_comp_ctx *ctx,
static int config_wdma_subfrm(struct mdp_comp_ctx *ctx,
struct mdp_cmdq_cmd *cmd, u32 index)
{
- const struct mdp_wdma_subfrm *subfrm = &ctx->param->wdma.subfrms[index];
phys_addr_t base = ctx->comp->reg_base;
u8 subsys_id = ctx->comp->subsys_id;
+ u32 reg = 0;

/* Write Y pixel offset */
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].offset[0]);
MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_ADDR_OFFSET,
- subfrm->offset[0], 0x0FFFFFFF);
+ reg, 0x0FFFFFFF);
/* Write U pixel offset */
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].offset[1]);
MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_U_ADDR_OFFSET,
- subfrm->offset[1], 0x0FFFFFFF);
+ reg, 0x0FFFFFFF);
/* Write V pixel offset */
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].offset[2]);
MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_V_ADDR_OFFSET,
- subfrm->offset[2], 0x0FFFFFFF);
+ reg, 0x0FFFFFFF);
/* Write source size */
- MM_REG_WRITE(cmd, subsys_id, base, WDMA_SRC_SIZE, subfrm->src,
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].src);
+ MM_REG_WRITE(cmd, subsys_id, base, WDMA_SRC_SIZE, reg,
0x3FFF3FFF);
/* Write target size */
- MM_REG_WRITE(cmd, subsys_id, base, WDMA_CLIP_SIZE, subfrm->clip,
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].clip);
+ MM_REG_WRITE(cmd, subsys_id, base, WDMA_CLIP_SIZE, reg,
0x3FFF3FFF);
/* Write clip offset */
- MM_REG_WRITE(cmd, subsys_id, base, WDMA_CLIP_COORD, subfrm->clip_ofst,
+ if (CFG_CHECK(MT8183, p_id))
+ reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].clip_ofst);
+ MM_REG_WRITE(cmd, subsys_id, base, WDMA_CLIP_COORD, reg,
0x3FFF3FFF);

/* Enable WDMA */
@@ -564,13 +712,21 @@ static int init_ccorr(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd)
static int config_ccorr_subfrm(struct mdp_comp_ctx *ctx,
struct mdp_cmdq_cmd *cmd, u32 index)
{
- const struct img_comp_subfrm *csf = &ctx->param->subfrms[index];
phys_addr_t base = ctx->comp->reg_base;
u8 subsys_id = ctx->comp->subsys_id;
+ u32 csf_l = 0, csf_r = 0;
+ u32 csf_t = 0, csf_b = 0;
u32 hsize, vsize;

- hsize = csf->in.right - csf->in.left + 1;
- vsize = csf->in.bottom - csf->in.top + 1;
+ if (CFG_CHECK(MT8183, p_id)) {
+ csf_l = CFG_COMP(MT8183, ctx->param, subfrms[index].in.left);
+ csf_r = CFG_COMP(MT8183, ctx->param, subfrms[index].in.right);
+ csf_t = CFG_COMP(MT8183, ctx->param, subfrms[index].in.top);
+ csf_b = CFG_COMP(MT8183, ctx->param, subfrms[index].in.bottom);
+ }
+
+ hsize = csf_r - csf_l + 1;
+ vsize = csf_b - csf_t + 1;
MM_REG_WRITE(cmd, subsys_id, base, MDP_CCORR_SIZE,
(hsize << 16) + (vsize << 0), 0x1FFF1FFF);
return 0;
@@ -939,6 +1095,7 @@ int mdp_comp_config(struct mdp_dev *mdp)
int ret;

memset(mdp_comp_alias_id, 0, sizeof(mdp_comp_alias_id));
+ p_id = mdp->mdp_data->mdp_plat_id;

parent = dev->of_node->parent;
/* Iterate over sibling MDP function blocks */
@@ -998,9 +1155,19 @@ int mdp_comp_ctx_config(struct mdp_dev *mdp, struct mdp_comp_ctx *ctx,
{
struct device *dev = &mdp->pdev->dev;
enum mtk_mdp_comp_id public_id = MDP_COMP_NONE;
- int i;
+ u32 arg;
+ int i, idx;

- public_id = mdp_cfg_get_id_public(mdp, param->type);
+ if (!param) {
+ dev_err(dev, "Invalid component param");
+ return -EINVAL;
+ }
+
+ if (CFG_CHECK(MT8183, p_id))
+ arg = CFG_COMP(MT8183, param, type);
+ else
+ return -EINVAL;
+ public_id = mdp_cfg_get_id_public(mdp, arg);
if (public_id < 0) {
dev_err(dev, "Invalid component id %d", public_id);
return -EINVAL;
@@ -1008,13 +1175,26 @@ int mdp_comp_ctx_config(struct mdp_dev *mdp, struct mdp_comp_ctx *ctx,

ctx->comp = mdp->comp[public_id];
if (!ctx->comp) {
- dev_err(dev, "Uninit component inner id %d", param->type);
+ dev_err(dev, "Uninit component inner id %d", arg);
return -EINVAL;
}

ctx->param = param;
- ctx->input = &frame->inputs[param->input];
- for (i = 0; i < param->num_outputs; i++)
- ctx->outputs[i] = &frame->outputs[param->outputs[i]];
+ if (CFG_CHECK(MT8183, p_id))
+ arg = CFG_COMP(MT8183, param, input);
+ else
+ return -EINVAL;
+ ctx->input = &frame->inputs[arg];
+ if (CFG_CHECK(MT8183, p_id))
+ idx = CFG_COMP(MT8183, param, num_outputs);
+ else
+ return -EINVAL;
+ for (i = 0; i < idx; i++) {
+ if (CFG_CHECK(MT8183, p_id))
+ arg = CFG_COMP(MT8183, param, outputs[i]);
+ else
+ return -EINVAL;
+ ctx->outputs[i] = &frame->outputs[arg];
+ }
return 0;
}
diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h
index 59a1c88d8184..7e21d226ceb8 100644
--- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h
+++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h
@@ -51,6 +51,7 @@ enum mdp_pipe_id {
};

struct mtk_mdp_driver_data {
+ const int mdp_plat_id;
const struct of_device_id *mdp_probe_infra;
const struct mdp_platform_config *mdp_cfg;
const u32 *mdp_mutex_table_idx;
--
2.18.0

2023-03-21 13:30:06

by Hans Verkuil

Subject: Re: [PATCH v6 00/12] Add support for multiple chips

Hi Moudy,

On 08/02/2023 10:08, Moudy Ho wrote:
> Changes since v5:
> - Rebase on linux-next.
> - Integrate the chip configuration into a source file called "mdp_cfg_data.c"
> instead of a header file.
> - Fix undefined reference to __udividi3 caused by patch [1/12].
> - Fix parentheses issue reported by check script.
> - Fix compilation and smatch errors
>
> Changes since v4:
> - Rebase on linux-next.
> - Fix potential frame size overflow in "mtk-mdp3-regs.c".
> - Fix OOB in MDP3 component clocks in "mtk-mdp3-comp.*".
> - Reconfigure the shared memory between MDP3 kerenl and SCP.
>
> Changes since v3:
> - Rebase on linux-next.
> - In the file "mtk-mdp3-m2m.c", use the limited resolution defined by
> each platform to replace the default format.
> - Add platform ID in driver data, and refine shared memory structure preprocessing.
> - Simplify the way to get mutex ID in function "mdp_path_subfrm_require".
>
> Changes since v2:
> - Depend on :
> [1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=687004
> - Split the shared memory header(mtk-img-ipi.h) by preprocessing instead, and
> classify the generic parts into "mtk-mdp3-type.h", and move
> chip-specific parts to"mt8183/mdp3-comp-mt8183.h".
>
> Changes since v1:
> - Depend on :
> [1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=687004
> - For hardware-specific structures in the shared memory header(mtk-img-ipi.h),
> split the relevant functions and structure definitions.
>
> Hi,
>
> To support multiple chips, a chip configuration header file needs to be created
> and the relevant information split and moved into it.

This series is close to be ready for merging.

Two issues: please rebase again to the latest media_stage tree
https://git.linuxtv.org/media_stage.git/

I had a number of conflicts, and I didn't feel comfortable to make the
changes myself, it wasn't trivial.

Secondly, I get a smatch error:

drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c:452 mdp_cfg_get_id_public() error: 'mdp_dev' dereferencing possible ERR_PTR()

In any case, if you can rebase and fix that issue, then I'll make a PR.

Thanks!

Hans

> The v4l2-compliance test results list is as follows:
>
> v4l2-compliance 1.23.0-4942, 32 bits, 32-bit time_t
> v4l2-compliance SHA: 4cf258c24026 2022-07-28 15:43:45
>
> Compliance test for mtk-mdp3 device /dev/video0:
>
> Driver Info:
> Driver name : mtk-mdp3
> Card type : MediaTek MDP3
> Bus info : platform:14001000.dma-controlle
> Driver version : 6.2.0
> Capabilities : 0x84204000
> Video Memory-to-Memory Multiplanar
> Streaming
> Extended Pix Format
> Device Capabilities
> Device Caps : 0x04204000
> Video Memory-to-Memory Multiplanar
> Streaming
> Extended Pix Format
>
> Required ioctls:
> test VIDIOC_QUERYCAP: OK
> test invalid ioctls: OK
>
> Allow for multiple opens:
> test second /dev/video0 open: OK
> test VIDIOC_QUERYCAP: OK
> test VIDIOC_G/S_PRIORITY: OK
> test for unlimited opens: OK
>
> Debug ioctls:
> test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
> test VIDIOC_LOG_STATUS: OK (Not Supported)
>
> Input ioctls:
> test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
> test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
> test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
> test VIDIOC_ENUMAUDIO: OK (Not Supported)
> test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
> test VIDIOC_G/S_AUDIO: OK (Not Supported)
> Inputs: 0 Audio Inputs: 0 Tuners: 0
>
> Output ioctls:
> test VIDIOC_G/S_MODULATOR: OK (Not Supported)
> test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
> test VIDIOC_ENUMAUDOUT: OK (Not Supported)
> test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
> test VIDIOC_G/S_AUDOUT: OK (Not Supported)
> Outputs: 0 Audio Outputs: 0 Modulators: 0
>
> Input/Output configuration ioctls:
> test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
> test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
> test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
> test VIDIOC_G/S_EDID: OK (Not Supported)
>
> Control ioctls:
> test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
> test VIDIOC_QUERYCTRL: OK
> test VIDIOC_G/S_CTRL: OK
> test VIDIOC_G/S/TRY_EXT_CTRLS: OK
> test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
> test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
> Standard Controls: 4 Private Controls: 0
>
> Format ioctls:
> test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
> test VIDIOC_G/S_PARM: OK (Not Supported)
> test VIDIOC_G_FBUF: OK (Not Supported)
> test VIDIOC_G_FMT: OK
> test VIDIOC_TRY_FMT: OK
> test VIDIOC_S_FMT: OK
> test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
> test Cropping: OK
> test Composing: OK
> test Scaling: OK
>
> Codec ioctls:
> test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
> test VIDIOC_G_ENC_INDEX: OK (Not Supported)
> test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
>
> Buffer ioctls:
> test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
> test VIDIOC_EXPBUF: OK
> test Requests: OK (Not Supported)
> test TIME32/64: OK
>
> Test input 0:
>
> Streaming ioctls:
> test read/write: OK (Not Supported)
> test blocking wait: OK
> (snip)
> test MMAP (no poll): OK
> (snip)
> test MMAP (select): OK
> (snip)
> test MMAP (epoll): OK
> test USERPTR (no poll): OK (Not Supported)
> test USERPTR (select): OK (Not Supported)
> test DMABUF: Cannot test, specify --expbuf-device
>
> Stream using all formats:
> (snip)
> Total for mtk-mdp3 device /dev/video0: 1174, Succeeded: 1174, Failed: 0, Warnings: 0
>
> Moudy Ho (12):
> media: platform: mtk-mdp3: fix potential frame size overflow in
> mdp_try_fmt_mplane()
> media: platform: mtk-mdp3: add files for chip configuration
> media: platform: mtk-mdp3: chip config split about component settings
> media: platform: mtk-mdp3: chip config split about subcomponents
> media: platform: mtk-mdp3: chip config split about color format
> media: platform: mtk-mdp3: chip config split about resolution
> limitations
> media: platform: mtk-mdp3: chip config split about pipe info
> media: platform: mtk-mdp3: extend mdp_color format for compressed mode
> media: platform: mtk-mdp3: dynamically allocate component clocks
> media: platform: mtk-mdp3: Split general definitions used in MDP3
> media: platform: mtk-mdp3: decompose hardware-related information in
> shared memory
> media: platform: mtk-mdp3: reconfigure shared memory
>
> drivers/media/platform/mediatek/mdp3/Makefile | 2 +-
> .../platform/mediatek/mdp3/mdp_cfg_data.c | 454 +++++++++++++++
> .../platform/mediatek/mdp3/mdp_sm_mt8183.h | 144 +++++
> .../platform/mediatek/mdp3/mtk-img-ipi.h | 189 +-----
> .../platform/mediatek/mdp3/mtk-mdp3-cfg.h | 20 +
> .../platform/mediatek/mdp3/mtk-mdp3-cmdq.c | 148 +++--
> .../platform/mediatek/mdp3/mtk-mdp3-comp.c | 538 +++++++++++-------
> .../platform/mediatek/mdp3/mtk-mdp3-comp.h | 24 +-
> .../platform/mediatek/mdp3/mtk-mdp3-core.c | 46 +-
> .../platform/mediatek/mdp3/mtk-mdp3-core.h | 18 +-
> .../platform/mediatek/mdp3/mtk-mdp3-m2m.c | 28 +-
> .../platform/mediatek/mdp3/mtk-mdp3-m2m.h | 1 -
> .../platform/mediatek/mdp3/mtk-mdp3-regs.c | 293 +---------
> .../platform/mediatek/mdp3/mtk-mdp3-regs.h | 214 +++----
> .../platform/mediatek/mdp3/mtk-mdp3-type.h | 53 ++
> .../platform/mediatek/mdp3/mtk-mdp3-vpu.c | 193 +++----
> .../platform/mediatek/mdp3/mtk-mdp3-vpu.h | 29 +-
> 17 files changed, 1429 insertions(+), 965 deletions(-)
> create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c
> create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_sm_mt8183.h
> create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-cfg.h
> create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-type.h
>

2023-03-23 06:25:38

by Moudy Ho (何宗原)

Subject: Re: [PATCH v6 00/12] Add support for multiple chips

On Tue, 2023-03-21 at 14:29 +0100, Hans Verkuil wrote:
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>
>
> Hi Moudy,
>
> On 08/02/2023 10:08, Moudy Ho wrote:
> > Changes since v5:
> > - Rebase on linux-next.
> > - Integrate the chip configuration into a source file called
> > "mdp_cfg_data.c"
> > instead of a header file.
> > - Fix undefined reference to __udividi3 caused by patch [1/12].
> > - Fix parentheses issue reported by check script.
> > - Fix compilation and smatch errors
> >
> > Changes since v4:
> > - Rebase on linux-next.
> > - Fix potential frame size overflow in "mtk-mdp3-regs.c".
> > - Fix OOB in MDP3 component clocks in "mtk-mdp3-comp.*".
> > - Reconfigure the shared memory between MDP3 kerenl and SCP.
> >
> > Changes since v3:
> > - Rebase on linux-next.
> > - In the file "mtk-mdp3-m2m.c", use the limited resolution defined
> > by
> > each platform to replace the default format.
> > - Add platform ID in driver data, and refine shared memory
> > structure preprocessing.
> > - Simplify the way to get mutex ID in function
> > "mdp_path_subfrm_require".
> >
> > Changes since v2:
> > - Depend on :
> > [1]
> > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/list/?series=687004__;!!CTRNKA9wMg0ARbw!iAf3tcBZjw9AvEspq5iBDy6AFb5FJqABlIoz-UirBUdXA5xp6vK7hIERvETf2q1Xau_WCznVyqQQjBNhPGkfq2pNtBEmFQ$
> > - Split the shared memory header(mtk-img-ipi.h) by preprocessing
> > instead, and
> > classify the generic parts into "mtk-mdp3-type.h", and move
> > chip-specific parts to"mt8183/mdp3-comp-mt8183.h".
> >
> > Changes since v1:
> > - Depend on :
> > [1]
> > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/list/?series=687004__;!!CTRNKA9wMg0ARbw!iAf3tcBZjw9AvEspq5iBDy6AFb5FJqABlIoz-UirBUdXA5xp6vK7hIERvETf2q1Xau_WCznVyqQQjBNhPGkfq2pNtBEmFQ$
> > - For hardware-specific structures in the shared memory header(mtk-
> > img-ipi.h),
> > split the relevant functions and structure definitions.
> >
> > Hi,
> >
> > To support multiple chips, a chip configuration header file needs
> > to be created
> > and the relevant information split and moved into it.
>
> This series is close to be ready for merging.
>
> Two issues: please rebase again to the latest media_stage tree
>
https://urldefense.com/v3/__https://git.linuxtv.org/media_stage.git/__;!!CTRNKA9wMg0ARbw!iAf3tcBZjw9AvEspq5iBDy6AFb5FJqABlIoz-UirBUdXA5xp6vK7hIERvETf2q1Xau_WCznVyqQQjBNhPGkfq2r8-L9Eew$
>
> I had a number of conflicts, and I didn't feel comfortable to make
> the
> changes myself, it wasn't trivial.
>
> Secondly, I get a smatch error:
>
> drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c:452
> mdp_cfg_get_id_public() error: 'mdp_dev' dereferencing possible
> ERR_PTR()
>
> In any case, if you can rebase and fix that issue, then I'll make a
> PR.
>
> Thanks!
>
> Hans
>

Hi Hans,

Thanks for all those assistance, I'll rebase and fix this series as
soon as possible.

Sincerely,
Moudy Ho

> > The v4l2-compliance test results list is as follows:
> >
> > v4l2-compliance 1.23.0-4942, 32 bits, 32-bit time_t
> > v4l2-compliance SHA: 4cf258c24026 2022-07-28 15:43:45
> >
> > Compliance test for mtk-mdp3 device /dev/video0:
> >
> > Driver Info:
> > Driver name : mtk-mdp3
> > Card type : MediaTek MDP3
> > Bus info : platform:14001000.dma-controlle
> > Driver version : 6.2.0
> > Capabilities : 0x84204000
> > Video Memory-to-Memory Multiplanar
> > Streaming
> > Extended Pix Format
> > Device Capabilities
> > Device Caps : 0x04204000
> > Video Memory-to-Memory Multiplanar
> > Streaming
> > Extended Pix Format
> >
> > Required ioctls:
> > test VIDIOC_QUERYCAP: OK
> > test invalid ioctls: OK
> >
> > Allow for multiple opens:
> > test second /dev/video0 open: OK
> > test VIDIOC_QUERYCAP: OK
> > test VIDIOC_G/S_PRIORITY: OK
> > test for unlimited opens: OK
> >
> > Debug ioctls:
> > test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
> > test VIDIOC_LOG_STATUS: OK (Not Supported)
> >
> > Input ioctls:
> > test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
> > test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
> > test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
> > test VIDIOC_ENUMAUDIO: OK (Not Supported)
> > test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
> > test VIDIOC_G/S_AUDIO: OK (Not Supported)
> > Inputs: 0 Audio Inputs: 0 Tuners: 0
> >
> > Output ioctls:
> > test VIDIOC_G/S_MODULATOR: OK (Not Supported)
> > test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
> > test VIDIOC_ENUMAUDOUT: OK (Not Supported)
> > test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
> > test VIDIOC_G/S_AUDOUT: OK (Not Supported)
> > Outputs: 0 Audio Outputs: 0 Modulators: 0
> >
> > Input/Output configuration ioctls:
> > test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
> > test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
> > test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
> > test VIDIOC_G/S_EDID: OK (Not Supported)
> >
> > Control ioctls:
> > test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
> > test VIDIOC_QUERYCTRL: OK
> > test VIDIOC_G/S_CTRL: OK
> > test VIDIOC_G/S/TRY_EXT_CTRLS: OK
> > test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
> > test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
> > Standard Controls: 4 Private Controls: 0
> >
> > Format ioctls:
> > test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
> > test VIDIOC_G/S_PARM: OK (Not Supported)
> > test VIDIOC_G_FBUF: OK (Not Supported)
> > test VIDIOC_G_FMT: OK
> > test VIDIOC_TRY_FMT: OK
> > test VIDIOC_S_FMT: OK
> > test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
> > test Cropping: OK
> > test Composing: OK
> > test Scaling: OK
> >
> > Codec ioctls:
> > test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
> > test VIDIOC_G_ENC_INDEX: OK (Not Supported)
> > test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
> >
> > Buffer ioctls:
> > test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
> > test VIDIOC_EXPBUF: OK
> > test Requests: OK (Not Supported)
> > test TIME32/64: OK
> >
> > Test input 0:
> >
> > Streaming ioctls:
> > test read/write: OK (Not Supported)
> > test blocking wait: OK
> > (snip)
> > test MMAP (no poll): OK
> > (snip)
> > test MMAP (select): OK
> > (snip)
> > test MMAP (epoll): OK
> > test USERPTR (no poll): OK (Not Supported)
> > test USERPTR (select): OK (Not Supported)
> > test DMABUF: Cannot test, specify --expbuf-device
> >
> > Stream using all formats:
> > (snip)
> > Total for mtk-mdp3 device /dev/video0: 1174, Succeeded: 1174,
> > Failed: 0, Warnings: 0
> >
> > Moudy Ho (12):
> > media: platform: mtk-mdp3: fix potential frame size overflow in
> > mdp_try_fmt_mplane()
> > media: platform: mtk-mdp3: add files for chip configuration
> > media: platform: mtk-mdp3: chip config split about component
> > settings
> > media: platform: mtk-mdp3: chip config split about subcomponents
> > media: platform: mtk-mdp3: chip config split about color format
> > media: platform: mtk-mdp3: chip config split about resolution
> > limitations
> > media: platform: mtk-mdp3: chip config split about pipe info
> > media: platform: mtk-mdp3: extend mdp_color format for compressed
> > mode
> > media: platform: mtk-mdp3: dynamically allocate component clocks
> > media: platform: mtk-mdp3: Split general definitions used in MDP3
> > media: platform: mtk-mdp3: decompose hardware-related information
> > in
> > shared memory
> > media: platform: mtk-mdp3: reconfigure shared memory
> >
> > drivers/media/platform/mediatek/mdp3/Makefile | 2 +-
> > .../platform/mediatek/mdp3/mdp_cfg_data.c | 454
> > +++++++++++++++
> > .../platform/mediatek/mdp3/mdp_sm_mt8183.h | 144 +++++
> > .../platform/mediatek/mdp3/mtk-img-ipi.h | 189 +-----
> > .../platform/mediatek/mdp3/mtk-mdp3-cfg.h | 20 +
> > .../platform/mediatek/mdp3/mtk-mdp3-cmdq.c | 148 +++--
> > .../platform/mediatek/mdp3/mtk-mdp3-comp.c | 538 +++++++++++---
> > ----
> > .../platform/mediatek/mdp3/mtk-mdp3-comp.h | 24 +-
> > .../platform/mediatek/mdp3/mtk-mdp3-core.c | 46 +-
> > .../platform/mediatek/mdp3/mtk-mdp3-core.h | 18 +-
> > .../platform/mediatek/mdp3/mtk-mdp3-m2m.c | 28 +-
> > .../platform/mediatek/mdp3/mtk-mdp3-m2m.h | 1 -
> > .../platform/mediatek/mdp3/mtk-mdp3-regs.c | 293 +---------
> > .../platform/mediatek/mdp3/mtk-mdp3-regs.h | 214 +++----
> > .../platform/mediatek/mdp3/mtk-mdp3-type.h | 53 ++
> > .../platform/mediatek/mdp3/mtk-mdp3-vpu.c | 193 +++----
> > .../platform/mediatek/mdp3/mtk-mdp3-vpu.h | 29 +-
> > 17 files changed, 1429 insertions(+), 965 deletions(-)
> > create mode 100644
> > drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c
> > create mode 100644
> > drivers/media/platform/mediatek/mdp3/mdp_sm_mt8183.h
> > create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-
> > cfg.h
> > create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-
> > type.h
> >
>
>