Adds status interface for zynqmp-fpga, It's a read only interface
which allows the user to get the Programmable Logic(PL) status.
-Device Initialization error.
-Device internal signal error.
-All I/Os are placed in High-Z state.
-Device start-up sequence error.
-Firmware error.
For more details refer the ug570.
https://docs.xilinx.com/v/u/en-US/ug570-ultrascale-configuration
Nava kishore Manne (2):
firmware: xilinx: Add pm api function for PL config reg readback
fpga: zynqmp-fpga: Adds status interface
.../ABI/testing/sysfs-driver-zynqmp-fpga | 72 +++++++++++++++++++
drivers/firmware/xilinx/zynqmp.c | 33 +++++++++
drivers/fpga/zynqmp-fpga.c | 23 ++++++
include/linux/firmware/xlnx-zynqmp.h | 11 +++
4 files changed, 139 insertions(+)
create mode 100644 Documentation/ABI/testing/sysfs-driver-zynqmp-fpga
--
2.25.1
Adds PM API for performing Programmable Logic(PL) configuration
register readback. It provides an interface to the firmware(pmufw)
to readback the FPGA configuration register.
Signed-off-by: Nava kishore Manne <[email protected]>
---
changes for v2:
- None.
Changes for v3:
- Updated API and config reg read-back handling logic
- Updated the commit msg to align with the changes.
Changes for v4:
- Fixed some minor coding issues. No functional changes.
- Updated Return value comments as suggested by Xu Yilun.
Changes for v5:
- Fixed some minor coding issues as suggested by Xu Yilun.
No functional changes.
Changes for v6:
- None.
drivers/firmware/xilinx/zynqmp.c | 33 ++++++++++++++++++++++++++++
include/linux/firmware/xlnx-zynqmp.h | 11 ++++++++++
2 files changed, 44 insertions(+)
diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index 129f68d7a6f5..3d8cc6795b43 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -948,6 +948,39 @@ int zynqmp_pm_fpga_get_status(u32 *value)
}
EXPORT_SYMBOL_GPL(zynqmp_pm_fpga_get_status);
+/**
+ * zynqmp_pm_fpga_get_config_status - Get the FPGA configuration status.
+ * @value: Buffer to store FPGA configuration status.
+ *
+ * This function provides access to the pmufw to get the FPGA configuration
+ * status
+ *
+ * Return: 0 on success, a negative value on error
+ */
+int zynqmp_pm_fpga_get_config_status(u32 *value)
+{
+ u32 ret_payload[PAYLOAD_ARG_CNT];
+ u32 buf, lower_addr, upper_addr;
+ int ret;
+
+ if (!value)
+ return -EINVAL;
+
+ lower_addr = lower_32_bits((u64)&buf);
+ upper_addr = upper_32_bits((u64)&buf);
+
+ ret = zynqmp_pm_invoke_fn(PM_FPGA_READ,
+ XILINX_ZYNQMP_PM_FPGA_CONFIG_STAT_OFFSET,
+ lower_addr, upper_addr,
+ XILINX_ZYNQMP_PM_FPGA_READ_CONFIG_REG,
+ ret_payload);
+
+ *value = ret_payload[1];
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_fpga_get_config_status);
+
/**
* zynqmp_pm_pinctrl_request - Request Pin from firmware
* @pin: Pin number to request
diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
index b09f443d3ab9..ce37d55ffa44 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -71,6 +71,10 @@
#define XILINX_ZYNQMP_PM_FPGA_FULL 0x0U
#define XILINX_ZYNQMP_PM_FPGA_PARTIAL BIT(0)
+/* FPGA Status Reg */
+#define XILINX_ZYNQMP_PM_FPGA_CONFIG_STAT_OFFSET 7U
+#define XILINX_ZYNQMP_PM_FPGA_READ_CONFIG_REG 0U
+
/*
* Node IDs for the Error Events.
*/
@@ -120,6 +124,7 @@ enum pm_api_id {
PM_CLOCK_GETRATE = 42,
PM_CLOCK_SETPARENT = 43,
PM_CLOCK_GETPARENT = 44,
+ PM_FPGA_READ = 46,
PM_SECURE_AES = 47,
PM_FEATURE_CHECK = 63,
};
@@ -515,6 +520,7 @@ int zynqmp_pm_aes_engine(const u64 address, u32 *out);
int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags);
int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags);
int zynqmp_pm_fpga_get_status(u32 *value);
+int zynqmp_pm_fpga_get_config_status(u32 *value);
int zynqmp_pm_write_ggs(u32 index, u32 value);
int zynqmp_pm_read_ggs(u32 index, u32 *value);
int zynqmp_pm_write_pggs(u32 index, u32 value);
@@ -721,6 +727,11 @@ static inline int zynqmp_pm_fpga_get_status(u32 *value)
return -ENODEV;
}
+static inline int zynqmp_pm_fpga_get_config_status(u32 *value)
+{
+ return -ENODEV;
+}
+
static inline int zynqmp_pm_write_ggs(u32 index, u32 value)
{
return -ENODEV;
--
2.25.1
Adds status interface for zynqmp-fpga, It's a read only interface
which allows the user to get the Programmable Logic(PL) configuration
status.
Usage:
To read the Programmable Logic(PL) configuration status
cat /sys/bus/platform/drivers/zynqmp_fpga_manager/
firmware:zynqmp-firmware:pcap/status
Signed-off-by: Nava kishore Manne <[email protected]>
---
hanges for v2:
- Updated status messages handling logic as suggested by Xu Yilun.
Changes for v3:
- Updated status interface handling logic (Restrict the status
interface to the device-specific instead of handled by the core)
as suggested by Xu Yilun.
Changes for v4:
- Limit the error strings to one word for each as suggested by
Xu Yilun
Changes for v5:
- Added new sysfs-driver-zynqmp-fpga file.
Changes for v6:
- Updated the sysfs interface to cat /sys/bus/platform/drivers/...
as suggested by Xu Yilun.
- Exported raw hex value instead of multiple error strings
as suggested by Greg.
.../ABI/testing/sysfs-driver-zynqmp-fpga | 72 +++++++++++++++++++
drivers/fpga/zynqmp-fpga.c | 23 ++++++
2 files changed, 95 insertions(+)
create mode 100644 Documentation/ABI/testing/sysfs-driver-zynqmp-fpga
diff --git a/Documentation/ABI/testing/sysfs-driver-zynqmp-fpga b/Documentation/ABI/testing/sysfs-driver-zynqmp-fpga
new file mode 100644
index 000000000000..af5d42916dd1
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-driver-zynqmp-fpga
@@ -0,0 +1,72 @@
+What: /sys/bus/platform/drivers/zynqmp_fpga_manager/firmware:zynqmp-firmware:pcap/status
+Date: Jan 2023
+KernelVersion: 6.2
+Contact: Nava kishore Manne <[email protected]>
+Description: (RO) Read fpga status.
+ Read returns a hexadecimal value that tells the current status
+ of the FPGA device. Each bit position in the status value is
+ described Below(see ug570 chapter 9).
+
+ ====================== ==============================================
+ BIT(0) 0: No CRC error
+ 1: CRC error
+
+ BIT(1) 0: Decryptor security not set
+ 1: Decryptor security set
+
+ BIT(2) 0: MMCMs/PLLs are not locked
+ 1: MMCMs/PLLs are locked
+
+ BIT(3) 0: DCI not matched
+ 1: DCI matched
+
+ BIT(4) 0: Start-up sequence has not finished
+ 1: Start-up sequence has finished
+
+ BIT(5) 0: All I/Os are placed in High-Z state
+ 1: All I/Os behave as configured
+
+ BIT(6) 0: Flip-flops and block RAM are write disabled
+ 1: Flip-flops and block RAM are write enabled
+
+ BIT(7) 0: GHIGH_B_STATUS asserted
+ 1: GHIGH_B_STATUS deasserted
+
+ BIT(8) to BIT(10) Status of the mode pins
+
+ BIT(11) 0: Initialization has not finished
+ 1: Initialization finished
+
+ BIT(12) Value on INIT_B_PIN pin
+
+ BIT(13) 0: Signal not released
+ 1: Signal released
+
+ BIT(14) Value on DONE_PIN pin.
+
+ BIT(15) 0: No IDCODE_ERROR
+ 1: IDCODE_ERROR
+
+ BIT(16) 0: No SECURITY_ERROR
+ 1: SECURITY_ERROR
+
+ BIT(17) System Monitor over-temperature if set
+
+ BIT(18) to BIT(20) Start-up state machine (0 to 7)
+ Phase 0 = 000
+ Phase 1 = 001
+ Phase 2 = 011
+ Phase 3 = 010
+ Phase 4 = 110
+ Phase 5 = 111
+ Phase 6 = 101
+ Phase 7 = 100
+
+ BIT(25) to BIT(26) Indicates the detected bus width
+ 00 = x1
+ 01 = x8
+ 10 = x16
+ 11 = x32
+ ====================== ==============================================
+
+ The other bits are reserved.
diff --git a/drivers/fpga/zynqmp-fpga.c b/drivers/fpga/zynqmp-fpga.c
index c60f20949c47..0c58ca27319f 100644
--- a/drivers/fpga/zynqmp-fpga.c
+++ b/drivers/fpga/zynqmp-fpga.c
@@ -77,6 +77,28 @@ static enum fpga_mgr_states zynqmp_fpga_ops_state(struct fpga_manager *mgr)
return FPGA_MGR_STATE_UNKNOWN;
}
+static ssize_t status_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ u32 status;
+ int ret;
+
+ ret = zynqmp_pm_fpga_get_config_status(&status);
+ if (ret)
+ return ret;
+
+ return sprintf(buf, "0x%x\n", status);
+}
+
+static DEVICE_ATTR_RO(status);
+
+static struct attribute *zynqmp_fpga_attrs[] = {
+ &dev_attr_status.attr,
+ NULL,
+};
+
+ATTRIBUTE_GROUPS(zynqmp_fpga);
+
static const struct fpga_manager_ops zynqmp_fpga_ops = {
.state = zynqmp_fpga_ops_state,
.write_init = zynqmp_fpga_ops_write_init,
@@ -113,6 +135,7 @@ static struct platform_driver zynqmp_fpga_driver = {
.driver = {
.name = "zynqmp_fpga_manager",
.of_match_table = of_match_ptr(zynqmp_fpga_of_match),
+ .dev_groups = zynqmp_fpga_groups,
},
};
--
2.25.1
On 2023-02-17 at 17:20:36 +0530, Nava kishore Manne wrote:
> Adds status interface for zynqmp-fpga, It's a read only interface
s/,/.
> which allows the user to get the Programmable Logic(PL) configuration
> status.
>
> Usage:
> To read the Programmable Logic(PL) configuration status
> cat /sys/bus/platform/drivers/zynqmp_fpga_manager/
> firmware:zynqmp-firmware:pcap/status
Don't wrap here.
>
> Signed-off-by: Nava kishore Manne <[email protected]>
> ---
> hanges for v2:
> - Updated status messages handling logic as suggested by Xu Yilun.
>
> Changes for v3:
> - Updated status interface handling logic (Restrict the status
> interface to the device-specific instead of handled by the core)
> as suggested by Xu Yilun.
>
> Changes for v4:
> - Limit the error strings to one word for each as suggested by
> Xu Yilun
>
> Changes for v5:
> - Added new sysfs-driver-zynqmp-fpga file.
>
> Changes for v6:
> - Updated the sysfs interface to cat /sys/bus/platform/drivers/...
> as suggested by Xu Yilun.
> - Exported raw hex value instead of multiple error strings
> as suggested by Greg.
>
> .../ABI/testing/sysfs-driver-zynqmp-fpga | 72 +++++++++++++++++++
> drivers/fpga/zynqmp-fpga.c | 23 ++++++
> 2 files changed, 95 insertions(+)
> create mode 100644 Documentation/ABI/testing/sysfs-driver-zynqmp-fpga
>
> diff --git a/Documentation/ABI/testing/sysfs-driver-zynqmp-fpga b/Documentation/ABI/testing/sysfs-driver-zynqmp-fpga
> new file mode 100644
> index 000000000000..af5d42916dd1
> --- /dev/null
> +++ b/Documentation/ABI/testing/sysfs-driver-zynqmp-fpga
> @@ -0,0 +1,72 @@
> +What: /sys/bus/platform/drivers/zynqmp_fpga_manager/firmware:zynqmp-firmware:pcap/status
> +Date: Jan 2023
> +KernelVersion: 6.2
Please update the version & Data, I expect this could be merged in next
cycle, so 6.4
> +Contact: Nava kishore Manne <[email protected]>
> +Description: (RO) Read fpga status.
> + Read returns a hexadecimal value that tells the current status
> + of the FPGA device. Each bit position in the status value is
> + described Below(see ug570 chapter 9).
Please provide the URL for ug570, the commit message in Patch #0 that
contains the info will not appear in mainline.
> +
> + ====================== ==============================================
> + BIT(0) 0: No CRC error
> + 1: CRC error
> +
> + BIT(1) 0: Decryptor security not set
> + 1: Decryptor security set
> +
> + BIT(2) 0: MMCMs/PLLs are not locked
> + 1: MMCMs/PLLs are locked
> +
> + BIT(3) 0: DCI not matched
> + 1: DCI matched
> +
> + BIT(4) 0: Start-up sequence has not finished
> + 1: Start-up sequence has finished
> +
> + BIT(5) 0: All I/Os are placed in High-Z state
> + 1: All I/Os behave as configured
> +
> + BIT(6) 0: Flip-flops and block RAM are write disabled
> + 1: Flip-flops and block RAM are write enabled
> +
> + BIT(7) 0: GHIGH_B_STATUS asserted
> + 1: GHIGH_B_STATUS deasserted
> +
> + BIT(8) to BIT(10) Status of the mode pins
> +
> + BIT(11) 0: Initialization has not finished
> + 1: Initialization finished
> +
> + BIT(12) Value on INIT_B_PIN pin
> +
> + BIT(13) 0: Signal not released
> + 1: Signal released
> +
> + BIT(14) Value on DONE_PIN pin.
> +
> + BIT(15) 0: No IDCODE_ERROR
> + 1: IDCODE_ERROR
> +
> + BIT(16) 0: No SECURITY_ERROR
> + 1: SECURITY_ERROR
> +
> + BIT(17) System Monitor over-temperature if set
> +
> + BIT(18) to BIT(20) Start-up state machine (0 to 7)
> + Phase 0 = 000
> + Phase 1 = 001
> + Phase 2 = 011
> + Phase 3 = 010
> + Phase 4 = 110
> + Phase 5 = 111
> + Phase 6 = 101
> + Phase 7 = 100
> +
> + BIT(25) to BIT(26) Indicates the detected bus width
> + 00 = x1
> + 01 = x8
> + 10 = x16
> + 11 = x32
> + ====================== ==============================================
> +
> + The other bits are reserved.
> diff --git a/drivers/fpga/zynqmp-fpga.c b/drivers/fpga/zynqmp-fpga.c
> index c60f20949c47..0c58ca27319f 100644
> --- a/drivers/fpga/zynqmp-fpga.c
> +++ b/drivers/fpga/zynqmp-fpga.c
> @@ -77,6 +77,28 @@ static enum fpga_mgr_states zynqmp_fpga_ops_state(struct fpga_manager *mgr)
> return FPGA_MGR_STATE_UNKNOWN;
> }
>
> +static ssize_t status_show(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
> + u32 status;
> + int ret;
> +
> + ret = zynqmp_pm_fpga_get_config_status(&status);
> + if (ret)
> + return ret;
> +
> + return sprintf(buf, "0x%x\n", status);
sysfs_emit?
> +}
> +
No blank line please.
> +static DEVICE_ATTR_RO(status);
> +
> +static struct attribute *zynqmp_fpga_attrs[] = {
> + &dev_attr_status.attr,
> + NULL,
> +};
> +
Same.
Thanks,
Yilun
> +ATTRIBUTE_GROUPS(zynqmp_fpga);
> +
> static const struct fpga_manager_ops zynqmp_fpga_ops = {
> .state = zynqmp_fpga_ops_state,
> .write_init = zynqmp_fpga_ops_write_init,
> @@ -113,6 +135,7 @@ static struct platform_driver zynqmp_fpga_driver = {
> .driver = {
> .name = "zynqmp_fpga_manager",
> .of_match_table = of_match_ptr(zynqmp_fpga_of_match),
> + .dev_groups = zynqmp_fpga_groups,
> },
> };
>
> --
> 2.25.1
>