Add compatibles for the Cortex-A715 and X3 cores found in some
recent flagship designs.
Signed-off-by: Konrad Dybcio <[email protected]>
---
Documentation/devicetree/bindings/arm/cpus.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
index a7586295a6f5..c145f6a035ee 100644
--- a/Documentation/devicetree/bindings/arm/cpus.yaml
+++ b/Documentation/devicetree/bindings/arm/cpus.yaml
@@ -141,6 +141,7 @@ properties:
- arm,cortex-a78ae
- arm,cortex-a510
- arm,cortex-a710
+ - arm,cortex-a715
- arm,cortex-m0
- arm,cortex-m0+
- arm,cortex-m1
@@ -151,6 +152,7 @@ properties:
- arm,cortex-r7
- arm,cortex-x1
- arm,cortex-x2
+ - arm,cortex-x3
- arm,neoverse-e1
- arm,neoverse-n1
- arm,neoverse-n2
--
2.39.1
Use the correct compatibles for the four kinds of CPU cores used on
SM8550, based on the value of their MIDR_EL1 registers:
CPU7: 0x411fd4e0 - CX3 r1p1
CPU5-6: 0x412fd470 - CA710 r?p?
CPU3-4: 0x411fd4d0 - CA715 r?p?
CPU0-2: 0x411fd461 - CA510 r?p?
Signed-off-by: Konrad Dybcio <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index ff4d342c0725..a65c3151baf3 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -66,7 +66,7 @@ cpus {
CPU0: cpu@0 {
device_type = "cpu";
- compatible = "qcom,kryo";
+ compatible = "arm,cortex-a510";
reg = <0 0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
@@ -89,7 +89,7 @@ L3_0: l3-cache {
CPU1: cpu@100 {
device_type = "cpu";
- compatible = "qcom,kryo";
+ compatible = "arm,cortex-a510";
reg = <0 0x100>;
enable-method = "psci";
next-level-cache = <&L2_100>;
@@ -108,7 +108,7 @@ L2_100: l2-cache {
CPU2: cpu@200 {
device_type = "cpu";
- compatible = "qcom,kryo";
+ compatible = "arm,cortex-a510";
reg = <0 0x200>;
enable-method = "psci";
next-level-cache = <&L2_200>;
@@ -127,7 +127,7 @@ L2_200: l2-cache {
CPU3: cpu@300 {
device_type = "cpu";
- compatible = "qcom,kryo";
+ compatible = "arm,cortex-a715";
reg = <0 0x300>;
enable-method = "psci";
next-level-cache = <&L2_300>;
@@ -146,7 +146,7 @@ L2_300: l2-cache {
CPU4: cpu@400 {
device_type = "cpu";
- compatible = "qcom,kryo";
+ compatible = "arm,cortex-a715";
reg = <0 0x400>;
enable-method = "psci";
next-level-cache = <&L2_400>;
@@ -165,7 +165,7 @@ L2_400: l2-cache {
CPU5: cpu@500 {
device_type = "cpu";
- compatible = "qcom,kryo";
+ compatible = "arm,cortex-a710";
reg = <0 0x500>;
enable-method = "psci";
next-level-cache = <&L2_500>;
@@ -184,7 +184,7 @@ L2_500: l2-cache {
CPU6: cpu@600 {
device_type = "cpu";
- compatible = "qcom,kryo";
+ compatible = "arm,cortex-a710";
reg = <0 0x600>;
enable-method = "psci";
next-level-cache = <&L2_600>;
@@ -203,7 +203,7 @@ L2_600: l2-cache {
CPU7: cpu@700 {
device_type = "cpu";
- compatible = "qcom,kryo";
+ compatible = "arm,cortex-x3";
reg = <0 0x700>;
enable-method = "psci";
next-level-cache = <&L2_700>;
--
2.39.1
On Thu, Feb 16, 2023 at 12:08:03PM +0100, Konrad Dybcio wrote:
> Use the correct compatibles for the four kinds of CPU cores used on
> SM8550, based on the value of their MIDR_EL1 registers:
>
> CPU7: 0x411fd4e0 - CX3 r1p1
> CPU5-6: 0x412fd470 - CA710 r?p?
> CPU3-4: 0x411fd4d0 - CA715 r?p?
> CPU0-2: 0x411fd461 - CA510 r?p?
>
> Signed-off-by: Konrad Dybcio <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 16 ++++++++--------
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index ff4d342c0725..a65c3151baf3 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -66,7 +66,7 @@ cpus {
>
> CPU0: cpu@0 {
> device_type = "cpu";
> - compatible = "qcom,kryo";
> + compatible = "arm,cortex-a510";
Good. We should kill off the meaningless 'qcom,kryo'.
Acked-by: Rob Herring <[email protected]>
On Thu, 16 Feb 2023 12:08:02 +0100, Konrad Dybcio wrote:
> Add compatibles for the Cortex-A715 and X3 cores found in some
> recent flagship designs.
>
> Signed-off-by: Konrad Dybcio <[email protected]>
> ---
> Documentation/devicetree/bindings/arm/cpus.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
I took this for v6.3. No need for it to wait.
Rob
On Thu, 16 Feb 2023 12:08:02 +0100, Konrad Dybcio wrote:
> Add compatibles for the Cortex-A715 and X3 cores found in some
> recent flagship designs.
>
>
Applied, thanks!
[2/2] arm64: dts: qcom: sm8550: Use correct CPU compatibles
commit: 27072f2ffb29283b9a44d878204c86c08d86b37f
Best regards,
--
Bjorn Andersson <[email protected]>