Add compatibles for the Cortex-A78C and X1C cores found in some
recent flagship designs.
Signed-off-by: Konrad Dybcio <[email protected]>
---
Documentation/devicetree/bindings/arm/cpus.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
index c145f6a035ee..a9bbe2b74b5d 100644
--- a/Documentation/devicetree/bindings/arm/cpus.yaml
+++ b/Documentation/devicetree/bindings/arm/cpus.yaml
@@ -139,6 +139,7 @@ properties:
- arm,cortex-a77
- arm,cortex-a78
- arm,cortex-a78ae
+ - arm,cortex-a78c
- arm,cortex-a510
- arm,cortex-a710
- arm,cortex-a715
@@ -151,6 +152,7 @@ properties:
- arm,cortex-r5
- arm,cortex-r7
- arm,cortex-x1
+ - arm,cortex-x1c
- arm,cortex-x2
- arm,cortex-x3
- arm,neoverse-e1
--
2.39.2
Cores 0-3 are CA78C r0p0, cores 4-7 are CX1C r0p0. Use the correct
compatibles instead of the placeholder qcom,kryo.
Signed-off-by: Konrad Dybcio <[email protected]>
---
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 0d02599d8867..9c186ba55cdc 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -43,7 +43,7 @@ cpus {
CPU0: cpu@0 {
device_type = "cpu";
- compatible = "qcom,kryo";
+ compatible = "arm,cortex-a78c";
reg = <0x0 0x0>;
enable-method = "psci";
capacity-dmips-mhz = <602>;
@@ -67,7 +67,7 @@ L3_0: l3-cache {
CPU1: cpu@100 {
device_type = "cpu";
- compatible = "qcom,kryo";
+ compatible = "arm,cortex-a78c";
reg = <0x0 0x100>;
enable-method = "psci";
capacity-dmips-mhz = <602>;
@@ -87,7 +87,7 @@ L2_100: l2-cache {
CPU2: cpu@200 {
device_type = "cpu";
- compatible = "qcom,kryo";
+ compatible = "arm,cortex-a78c";
reg = <0x0 0x200>;
enable-method = "psci";
capacity-dmips-mhz = <602>;
@@ -107,7 +107,7 @@ L2_200: l2-cache {
CPU3: cpu@300 {
device_type = "cpu";
- compatible = "qcom,kryo";
+ compatible = "arm,cortex-a78c";
reg = <0x0 0x300>;
enable-method = "psci";
capacity-dmips-mhz = <602>;
@@ -127,7 +127,7 @@ L2_300: l2-cache {
CPU4: cpu@400 {
device_type = "cpu";
- compatible = "qcom,kryo";
+ compatible = "arm,cortex-x1c";
reg = <0x0 0x400>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
@@ -147,7 +147,7 @@ L2_400: l2-cache {
CPU5: cpu@500 {
device_type = "cpu";
- compatible = "qcom,kryo";
+ compatible = "arm,cortex-x1c";
reg = <0x0 0x500>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
@@ -167,7 +167,7 @@ L2_500: l2-cache {
CPU6: cpu@600 {
device_type = "cpu";
- compatible = "qcom,kryo";
+ compatible = "arm,cortex-x1c";
reg = <0x0 0x600>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
@@ -187,7 +187,7 @@ L2_600: l2-cache {
CPU7: cpu@700 {
device_type = "cpu";
- compatible = "qcom,kryo";
+ compatible = "arm,cortex-x1c";
reg = <0x0 0x700>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
--
2.39.2
On 24/02/2023 14:07, Konrad Dybcio wrote:
> Add compatibles for the Cortex-A78C and X1C cores found in some
> recent flagship designs.
>
> Signed-off-by: Konrad Dybcio <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On Fri, 24 Feb 2023 14:07:57 +0100, Konrad Dybcio wrote:
> Add compatibles for the Cortex-A78C and X1C cores found in some
> recent flagship designs.
>
> Signed-off-by: Konrad Dybcio <[email protected]>
> ---
> Documentation/devicetree/bindings/arm/cpus.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
Applied, thanks!
On Fri, 24 Feb 2023 14:07:57 +0100, Konrad Dybcio wrote:
> Add compatibles for the Cortex-A78C and X1C cores found in some
> recent flagship designs.
>
>
Applied, thanks!
[2/2] arm64: dts: qcom: sc8280xp: Use correct CPU compatibles
commit: c2819cab9d2edddcb8395bb74367ba61e581a2c5
Best regards,
--
Bjorn Andersson <[email protected]>