Changes in v4:
- Added a fix for MT8192 Vgpu voltage constraints
- Changed constraints for MT8192 VSRAM-GPU to reflect the maximum
achievable voltage as per the actual vsram-vgpu relation constraint
Changes in v3:
- Changed MT8186 compatibles for new bindings
- Added min/max voltage overrides for vgpu/vsram_gpu on
mt8183-pumpkin and evb as suggested by Chen-Yu
- Cosmetic fixes for "arm64: dts: mediatek: mt8192: Add GPU nodes"
Changes in v2:
- Changed MT8186 to use only two power domains for the GPU.
We finally have working GPU DVFS on MediaTek SoCs.
On Panfrost.
For real.
...and the best part is that it's going upstream.
In order to get GPU DVFS working, it was necessary to satisfy a
specific constraint (which is different, depending on the SoC)
between two regulators: GPU VCORE and GPU SRAM.
This was done through adding the mtk-regulator-coupler driver,
which transparently manages the voltage relation between these
two vregs, hence completely eliminating the need to manage these
regulators in the Panfrost driver; this solves the long standing
issue with devfreq+opp tables not supporting managing voltages
for two regulators per opp entry out of the box, due to which
we never got GPU DVFS on those SoCs, often locking them out to
a low GPU frequency.
This changes. Right now!
Tested on MT8192, MT8195 Chromebooks.
This series depends on [1].
[1]: https://lore.kernel.org/lkml/[email protected]/
Alyssa Rosenzweig (2):
arm64: dts: mediatek: mt8192: Add GPU nodes
arm64: dts: mediatek: mt8192-asurada: Enable GPU
AngeloGioacchino Del Regno (16):
arm64: dts: mediatek: mt8183-kukui: Couple VGPU and VSRAM_GPU
regulators
arm64: dts: mediatek: mt8183-kukui: Override vgpu/vsram_gpu
constraints
arm64: dts: mediatek: mt8183: Remove second opp-microvolt entries from
gpu table
arm64: dts: mt8183-pumpkin: Couple VGPU and VSRAM_GPU regulators
arm64: dts: mediatek: mt8183-evb: Couple VGPU and VSRAM_GPU regulators
arm64: dts: mediatek: mt8183: Use mediatek,mt8183b-mali as GPU
compatible
arm64: dts: mediatek: mt8192: Add mfg_ref_sel clock to MFG0 domain
arm64: dts: mediatek: mt8192-asurada: Assign sram supply to MFG1 pd
arm64: dts: mediatek: mt8192-asurada: Fix voltage constraint for Vgpu
arm64: dts: mediatek: mt8192-asurada: Couple VGPU and VSRAM_OTHER
regulators
arm64: dts: mediatek: mt8195: Add mfg_core_tmp clock to MFG1 domain
arm64: dts: mt8195: Add panfrost node for Mali-G57 Valhall Natt GPU
arm64: dts: mediatek: mt8195-cherry: Enable Mali-G57 GPU
arm64: dts: mediatek: mt8186: Add GPU node
arm64: dts: mediatek: mt8183-pumpkin: Override vgpu/vsram_gpu
constraints
arm64: dts: mediatek: mt8183-evb: Override vgpu/vsram_gpu constraints
Nícolas F. R. A. Prado (1):
arm64: dts: mediatek: mt8192-asurada: Add MFG0 domain supply
arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 17 ++-
.../arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 17 ++-
.../boot/dts/mediatek/mt8183-pumpkin.dts | 17 ++-
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 34 ++---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 17 +++
.../boot/dts/mediatek/mt8192-asurada.dtsi | 24 +++-
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 116 +++++++++++++++++-
.../boot/dts/mediatek/mt8195-cherry.dtsi | 5 +
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 95 +++++++++++++-
9 files changed, 315 insertions(+), 27 deletions(-)
--
2.39.2
Add coupling for these regulators, as they have a strict voltage output
relation to satisfy in order to ensure GPU stable operation.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
index fbe14b13051a..de9778c85b94 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
@@ -294,7 +294,6 @@ dsi_out: endpoint {
&gpu {
mali-supply = <&mt6358_vgpu_reg>;
- sram-supply = <&mt6358_vsram_gpu_reg>;
};
&i2c0 {
@@ -401,6 +400,11 @@ &mt6358codec {
Avdd-supply = <&mt6358_vaud28_reg>;
};
+&mt6358_vgpu_reg {
+ regulator-coupled-with = <&mt6358_vsram_gpu_reg>;
+ regulator-coupled-max-spread = <100000>;
+};
+
&mt6358_vsim1_reg {
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2700000>;
@@ -411,6 +415,11 @@ &mt6358_vsim2_reg {
regulator-max-microvolt = <2700000>;
};
+&mt6358_vsram_gpu_reg {
+ regulator-coupled-with = <&mt6358_vgpu_reg>;
+ regulator-coupled-max-spread = <100000>;
+};
+
&pio {
aud_pins_default: audiopins {
pins_bus {
--
2.39.2
Override the PMIC-default voltage constraints for VGPU and VSRAM_GPU
with the platform specific vmin/vmax for the highest possible SoC
binning.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
index de9778c85b94..63952c1251df 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
@@ -401,6 +401,9 @@ &mt6358codec {
};
&mt6358_vgpu_reg {
+ regulator-min-microvolt = <625000>;
+ regulator-max-microvolt = <900000>;
+
regulator-coupled-with = <&mt6358_vsram_gpu_reg>;
regulator-coupled-max-spread = <100000>;
};
@@ -416,6 +419,9 @@ &mt6358_vsim2_reg {
};
&mt6358_vsram_gpu_reg {
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1000000>;
+
regulator-coupled-with = <&mt6358_vgpu_reg>;
regulator-coupled-max-spread = <100000>;
};
--
2.39.2
Add coupling for these regulators, as they have a strict voltage output
relation to satisfy in order to ensure GPU stable operation.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts
index a1d01639df30..c228f04d086b 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts
@@ -71,7 +71,6 @@ &auxadc {
&gpu {
mali-supply = <&mt6358_vgpu_reg>;
- sram-supply = <&mt6358_vsram_gpu_reg>;
};
&i2c0 {
@@ -176,6 +175,16 @@ &mmc1 {
non-removable;
};
+&mt6358_vgpu_reg {
+ regulator-coupled-with = <&mt6358_vsram_gpu_reg>;
+ regulator-coupled-max-spread = <100000>;
+};
+
+&mt6358_vsram_gpu_reg {
+ regulator-coupled-with = <&mt6358_vgpu_reg>;
+ regulator-coupled-max-spread = <100000>;
+};
+
&pio {
i2c_pins_0: i2c0 {
pins_i2c{
--
2.39.2
Add coupling for these regulators, as they have a strict voltage output
relation to satisfy in order to ensure GPU stable operation.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
index 52dc4a50e34d..fd327437e932 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
@@ -52,7 +52,6 @@ &auxadc {
&gpu {
mali-supply = <&mt6358_vgpu_reg>;
- sram-supply = <&mt6358_vsram_gpu_reg>;
};
&i2c0 {
@@ -138,6 +137,16 @@ &mmc1 {
non-removable;
};
+&mt6358_vgpu_reg {
+ regulator-coupled-with = <&mt6358_vsram_gpu_reg>;
+ regulator-coupled-max-spread = <100000>;
+};
+
+&mt6358_vsram_gpu_reg {
+ regulator-coupled-with = <&mt6358_vgpu_reg>;
+ regulator-coupled-max-spread = <100000>;
+};
+
&pio {
i2c_pins_0: i2c0{
pins_i2c{
--
2.39.2
This was done to keep a strict relation between VSRAM and VGPU, but
it never worked: now we're doing it transparently with the new
mediatek-regulator-coupler driver.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 32 ++++++++++++------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 3d1d7870a5f1..e01b96adef02 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -563,82 +563,82 @@ gpu_opp_table: opp-table-0 {
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
- opp-microvolt = <625000>, <850000>;
+ opp-microvolt = <625000>;
};
opp-320000000 {
opp-hz = /bits/ 64 <320000000>;
- opp-microvolt = <631250>, <850000>;
+ opp-microvolt = <631250>;
};
opp-340000000 {
opp-hz = /bits/ 64 <340000000>;
- opp-microvolt = <637500>, <850000>;
+ opp-microvolt = <637500>;
};
opp-360000000 {
opp-hz = /bits/ 64 <360000000>;
- opp-microvolt = <643750>, <850000>;
+ opp-microvolt = <643750>;
};
opp-380000000 {
opp-hz = /bits/ 64 <380000000>;
- opp-microvolt = <650000>, <850000>;
+ opp-microvolt = <650000>;
};
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
- opp-microvolt = <656250>, <850000>;
+ opp-microvolt = <656250>;
};
opp-420000000 {
opp-hz = /bits/ 64 <420000000>;
- opp-microvolt = <662500>, <850000>;
+ opp-microvolt = <662500>;
};
opp-460000000 {
opp-hz = /bits/ 64 <460000000>;
- opp-microvolt = <675000>, <850000>;
+ opp-microvolt = <675000>;
};
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
- opp-microvolt = <687500>, <850000>;
+ opp-microvolt = <687500>;
};
opp-540000000 {
opp-hz = /bits/ 64 <540000000>;
- opp-microvolt = <700000>, <850000>;
+ opp-microvolt = <700000>;
};
opp-580000000 {
opp-hz = /bits/ 64 <580000000>;
- opp-microvolt = <712500>, <850000>;
+ opp-microvolt = <712500>;
};
opp-620000000 {
opp-hz = /bits/ 64 <620000000>;
- opp-microvolt = <725000>, <850000>;
+ opp-microvolt = <725000>;
};
opp-653000000 {
opp-hz = /bits/ 64 <653000000>;
- opp-microvolt = <743750>, <850000>;
+ opp-microvolt = <743750>;
};
opp-698000000 {
opp-hz = /bits/ 64 <698000000>;
- opp-microvolt = <768750>, <868750>;
+ opp-microvolt = <768750>;
};
opp-743000000 {
opp-hz = /bits/ 64 <743000000>;
- opp-microvolt = <793750>, <893750>;
+ opp-microvolt = <793750>;
};
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
- opp-microvolt = <825000>, <925000>;
+ opp-microvolt = <825000>;
};
};
--
2.39.2
Use the new GPU related compatible to finally enable GPU DVFS on
the MT8183 SoC.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index e01b96adef02..5169779d01df 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -1752,7 +1752,7 @@ mfgcfg: syscon@13000000 {
};
gpu: gpu@13040000 {
- compatible = "mediatek,mt8183-mali", "arm,mali-bifrost";
+ compatible = "mediatek,mt8183b-mali", "arm,mali-bifrost";
reg = <0 0x13040000 0 0x4000>;
interrupts =
<GIC_SPI 280 IRQ_TYPE_LEVEL_LOW>,
--
2.39.2
The mfg_ref_sel clock is a mux used to switch between different "safe"
(and slower) clock sources for the GPU: this is used during MFGPLL
reconfiguration and eventually during idling at very low frequencies.
This clock getting turned off means that the GPU will occasionally be
unclocked, producing obvious consequences such as system crash or
unpredictable behavior: assigning it to the top level MFG power domain
will make sure that this stays on at all times during any operation on
the MFG domain (only GPU-related transactions).
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 34631adc52c6..a29cdff8a095 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -499,8 +499,9 @@ power-domain@MT8192_POWER_DOMAIN_CONN {
power-domain@MT8192_POWER_DOMAIN_MFG0 {
reg = <MT8192_POWER_DOMAIN_MFG0>;
- clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>;
- clock-names = "mfg";
+ clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>,
+ <&topckgen CLK_TOP_MFG_REF_SEL>;
+ clock-names = "mfg", "alt";
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
--
2.39.2
From: Alyssa Rosenzweig <[email protected]>
The MediaTek MT8192 includes a Mali-G57 GPU supported in Panfrost. Add
the GPU node to the device tree to enable 3D acceleration.
The GPU node is disabled by default. It should be enabled by board with
its power supplies correctly assigned.
Signed-off-by: Alyssa Rosenzweig <[email protected]>
[nfraprado: removed sram supply, tweaked opp node name, adjusted commit message]
Signed-off-by: Nícolas F. R. A. Prado <[email protected]>
[wenst@: disable GPU by default; adjusted prefix; split out board change]
Signed-off-by: Chen-Yu Tsai <[email protected]>
[Angelo: cosmetic fixes]
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 107 +++++++++++++++++++++++
1 file changed, 107 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 87b91c8feaf9..34631adc52c6 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -312,6 +312,91 @@ timer: timer {
clock-frequency = <13000000>;
};
+ gpu_opp_table: opp-table-0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-358000000 {
+ opp-hz = /bits/ 64 <358000000>;
+ opp-microvolt = <606250>;
+ };
+
+ opp-399000000 {
+ opp-hz = /bits/ 64 <399000000>;
+ opp-microvolt = <618750>;
+ };
+
+ opp-440000000 {
+ opp-hz = /bits/ 64 <440000000>;
+ opp-microvolt = <631250>;
+ };
+
+ opp-482000000 {
+ opp-hz = /bits/ 64 <482000000>;
+ opp-microvolt = <643750>;
+ };
+
+ opp-523000000 {
+ opp-hz = /bits/ 64 <523000000>;
+ opp-microvolt = <656250>;
+ };
+
+ opp-564000000 {
+ opp-hz = /bits/ 64 <564000000>;
+ opp-microvolt = <668750>;
+ };
+
+ opp-605000000 {
+ opp-hz = /bits/ 64 <605000000>;
+ opp-microvolt = <681250>;
+ };
+
+ opp-647000000 {
+ opp-hz = /bits/ 64 <647000000>;
+ opp-microvolt = <693750>;
+ };
+
+ opp-688000000 {
+ opp-hz = /bits/ 64 <688000000>;
+ opp-microvolt = <706250>;
+ };
+
+ opp-724000000 {
+ opp-hz = /bits/ 64 <724000000>;
+ opp-microvolt = <725000>;
+ };
+
+ opp-748000000 {
+ opp-hz = /bits/ 64 <748000000>;
+ opp-microvolt = <737500>;
+ };
+
+ opp-772000000 {
+ opp-hz = /bits/ 64 <772000000>;
+ opp-microvolt = <750000>;
+ };
+
+ opp-795000000 {
+ opp-hz = /bits/ 64 <795000000>;
+ opp-microvolt = <762500>;
+ };
+
+ opp-819000000 {
+ opp-hz = /bits/ 64 <819000000>;
+ opp-microvolt = <775000>;
+ };
+
+ opp-843000000 {
+ opp-hz = /bits/ 64 <843000000>;
+ opp-microvolt = <787500>;
+ };
+
+ opp-866000000 {
+ opp-hz = /bits/ 64 <866000000>;
+ opp-microvolt = <800000>;
+ };
+ };
+
soc {
#address-cells = <2>;
#size-cells = <2>;
@@ -1266,6 +1351,28 @@ mmc1: mmc@11f70000 {
status = "disabled";
};
+ gpu: gpu@13000000 {
+ compatible = "mediatek,mt8192-mali", "arm,mali-valhall-jm";
+ reg = <0 0x13000000 0 0x4000>;
+ interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "job", "mmu", "gpu";
+
+ clocks = <&apmixedsys CLK_APMIXED_MFGPLL>;
+
+ power-domains = <&spm MT8192_POWER_DOMAIN_MFG2>,
+ <&spm MT8192_POWER_DOMAIN_MFG3>,
+ <&spm MT8192_POWER_DOMAIN_MFG4>,
+ <&spm MT8192_POWER_DOMAIN_MFG5>,
+ <&spm MT8192_POWER_DOMAIN_MFG6>;
+ power-domain-names = "core0", "core1", "core2", "core3", "core4";
+
+ operating-points-v2 = <&gpu_opp_table>;
+
+ status = "disabled";
+ };
+
mfgcfg: clock-controller@13fbf000 {
compatible = "mediatek,mt8192-mfgcfg";
reg = <0 0x13fbf000 0 0x1000>;
--
2.39.2
From: Nícolas F. R. A. Prado <[email protected]>
The mfg0 power domain encompasses the whole GPU and its surrounding
glue logic. This power domain has a separate power rail.
Add its power supply for Asurada.
Signed-off-by: Nícolas F. R. A. Prado <[email protected]>
[[email protected]: fix subject prefix and add commit message]
Signed-off-by: Chen-Yu Tsai <[email protected]>
[Angelo: Reordered commits to address DVFS stability issues]
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 4 ++++
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
index 9f12257ab4e7..ec013d5ef157 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
@@ -380,6 +380,10 @@ &i2c7 {
pinctrl-0 = <&i2c7_pins>;
};
+&mfg0 {
+ domain-supply = <&mt6315_7_vbuck1>;
+};
+
&mipi_tx0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index a29cdff8a095..f19d4a8ef3f6 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -497,7 +497,7 @@ power-domain@MT8192_POWER_DOMAIN_CONN {
#power-domain-cells = <0>;
};
- power-domain@MT8192_POWER_DOMAIN_MFG0 {
+ mfg0: power-domain@MT8192_POWER_DOMAIN_MFG0 {
reg = <MT8192_POWER_DOMAIN_MFG0>;
clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>,
<&topckgen CLK_TOP_MFG_REF_SEL>;
--
2.39.2
Add a phandle to the MT8192_POWER_DOMAIN_MFG1 power domain and
assign the GPU VSRAM supply to this in mt8192-asurada: this allows to
keep the sram powered up while the GPU is used.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 4 ++++
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
index ec013d5ef157..df477eb89f21 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
@@ -384,6 +384,10 @@ &mfg0 {
domain-supply = <&mt6315_7_vbuck1>;
};
+&mfg1 {
+ domain-supply = <&mt6359_vsram_others_ldo_reg>;
+};
+
&mipi_tx0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index f19d4a8ef3f6..5c30caf74026 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -506,7 +506,7 @@ mfg0: power-domain@MT8192_POWER_DOMAIN_MFG0 {
#size-cells = <0>;
#power-domain-cells = <1>;
- power-domain@MT8192_POWER_DOMAIN_MFG1 {
+ mfg1: power-domain@MT8192_POWER_DOMAIN_MFG1 {
reg = <MT8192_POWER_DOMAIN_MFG1>;
mediatek,infracfg = <&infracfg>;
#address-cells = <1>;
--
2.39.2
The MT8192 SoC specifies a maximum voltage for the GPU's digital supply
of 0.88V and the GPU OPPs are declaring a maximum voltage of 0.80V.
In order to keep the GPU voltage in the safe range, change the maximum
voltage for mt6315@7's vbuck1 to 0.80V as sending, for any mistake,
1.193V would be catastrophic.
Fixes: 3183cb62b033 ("arm64: dts: mediatek: asurada: Add SPMI regulators")
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
index df477eb89f21..8570b78c04a4 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
@@ -1408,7 +1408,7 @@ mt6315_7_vbuck1: vbuck1 {
regulator-compatible = "vbuck1";
regulator-name = "Vgpu";
regulator-min-microvolt = <606250>;
- regulator-max-microvolt = <1193750>;
+ regulator-max-microvolt = <800000>;
regulator-enable-ramp-delay = <256>;
regulator-allowed-modes = <0 1 2>;
};
--
2.39.2
Add coupling for these regulators, as VSRAM_OTHER is used to power the
GPU SRAM, and they have a strict voltage output relation to satisfy in
order to ensure GPU stable operation.
While at it, also add voltage constraint overrides for the GPU SRAM
regulator "mt6359_vsram_others" so that we stay in a safe range of
0.75-0.80V.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
index 8570b78c04a4..f858eca219d7 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
@@ -447,6 +447,13 @@ &mt6359_vrf12_ldo_reg {
regulator-always-on;
};
+&mt6359_vsram_others_ldo_reg {
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <800000>;
+ regulator-coupled-with = <&mt6315_7_vbuck1>;
+ regulator-coupled-max-spread = <10000>;
+};
+
&mt6359_vufs_ldo_reg {
regulator-always-on;
};
@@ -1411,6 +1418,8 @@ mt6315_7_vbuck1: vbuck1 {
regulator-max-microvolt = <800000>;
regulator-enable-ramp-delay = <256>;
regulator-allowed-modes = <0 1 2>;
+ regulator-coupled-with = <&mt6359_vsram_others_ldo_reg>;
+ regulator-coupled-max-spread = <10000>;
};
};
};
--
2.39.2
From: Alyssa Rosenzweig <[email protected]>
Enable the GPU with its power supplies described.
Signed-off-by: Alyssa Rosenzweig <[email protected]>
[wenst@: patch split out from MT8192 GPU node patch]
Signed-off-by: Chen-Yu Tsai <[email protected]>
[Angelo: Minor commit title fix]
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
index f858eca219d7..5a440504d4f9 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
@@ -275,6 +275,11 @@ &dsi_out {
remote-endpoint = <&anx7625_in>;
};
+&gpu {
+ mali-supply = <&mt6315_7_vbuck1>;
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
--
2.39.2
Similarly to what can be seen in MT8192, on MT8195 the mfg_core_tmp
clock is a mux used to switch between different "safe" (and slower)
clock sources for the GPU: this is used during MFGPLL reconfiguration
and eventually during idling at very low frequencies.
This clock getting turned off means that the GPU will occasionally be
unclocked, producing obvious consequences such as system crash or
unpredictable behavior: assigning it to the top level MFG power domain
will make sure that this stays on at all times during any operation on
the MFG domain (only GPU-related transactions).
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 8f1264d5290b..d116830d6af3 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -446,8 +446,9 @@ mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 {
power-domain@MT8195_POWER_DOMAIN_MFG1 {
reg = <MT8195_POWER_DOMAIN_MFG1>;
- clocks = <&apmixedsys CLK_APMIXED_MFGPLL>;
- clock-names = "mfg";
+ clocks = <&apmixedsys CLK_APMIXED_MFGPLL>,
+ <&topckgen CLK_TOP_MFG_CORE_TMP>;
+ clock-names = "mfg", "alt";
mediatek,infracfg = <&infracfg_ao>;
#address-cells = <1>;
#size-cells = <0>;
--
2.39.2
Add GPU support through panfrost for the Mali-G57 GPU on MT8195
with its OPP table but keep it in disabled state.
This is expected to be enabled only on boards which make use of
the GPU.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 90 ++++++++++++++++++++++++
1 file changed, 90 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index d116830d6af3..0e4ee7713c30 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -333,6 +333,76 @@ performance: performance-controller@11bc10 {
#performance-domain-cells = <1>;
};
+ gpu_opp_table: opp-table-gpu {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-390000000 {
+ opp-hz = /bits/ 64 <390000000>;
+ opp-microvolt = <625000>;
+ };
+ opp-410000000 {
+ opp-hz = /bits/ 64 <410000000>;
+ opp-microvolt = <631250>;
+ };
+ opp-431000000 {
+ opp-hz = /bits/ 64 <431000000>;
+ opp-microvolt = <631250>;
+ };
+ opp-473000000 {
+ opp-hz = /bits/ 64 <473000000>;
+ opp-microvolt = <637500>;
+ };
+ opp-515000000 {
+ opp-hz = /bits/ 64 <515000000>;
+ opp-microvolt = <637500>;
+ };
+ opp-556000000 {
+ opp-hz = /bits/ 64 <556000000>;
+ opp-microvolt = <643750>;
+ };
+ opp-598000000 {
+ opp-hz = /bits/ 64 <598000000>;
+ opp-microvolt = <650000>;
+ };
+ opp-640000000 {
+ opp-hz = /bits/ 64 <640000000>;
+ opp-microvolt = <650000>;
+ };
+ opp-670000000 {
+ opp-hz = /bits/ 64 <670000000>;
+ opp-microvolt = <662500>;
+ };
+ opp-700000000 {
+ opp-hz = /bits/ 64 <700000000>;
+ opp-microvolt = <675000>;
+ };
+ opp-730000000 {
+ opp-hz = /bits/ 64 <730000000>;
+ opp-microvolt = <687500>;
+ };
+ opp-760000000 {
+ opp-hz = /bits/ 64 <760000000>;
+ opp-microvolt = <700000>;
+ };
+ opp-790000000 {
+ opp-hz = /bits/ 64 <790000000>;
+ opp-microvolt = <712500>;
+ };
+ opp-820000000 {
+ opp-hz = /bits/ 64 <820000000>;
+ opp-microvolt = <725000>;
+ };
+ opp-850000000 {
+ opp-hz = /bits/ 64 <850000000>;
+ opp-microvolt = <737500>;
+ };
+ opp-880000000 {
+ opp-hz = /bits/ 64 <880000000>;
+ opp-microvolt = <750000>;
+ };
+ };
+
pmu-a55 {
compatible = "arm,cortex-a55-pmu";
interrupt-parent = <&gic>;
@@ -1790,6 +1860,26 @@ ufsphy: ufs-phy@11fa0000 {
status = "disabled";
};
+ gpu: gpu@13000000 {
+ compatible = "mediatek,mt8195-mali", "mediatek,mt8192-mali",
+ "arm,mali-valhall-jm";
+ reg = <0 0x13000000 0 0x4000>;
+
+ clocks = <&mfgcfg CLK_MFG_BG3D>;
+ interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "job", "mmu", "gpu";
+ operating-points-v2 = <&gpu_opp_table>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_MFG2>,
+ <&spm MT8195_POWER_DOMAIN_MFG3>,
+ <&spm MT8195_POWER_DOMAIN_MFG4>,
+ <&spm MT8195_POWER_DOMAIN_MFG5>,
+ <&spm MT8195_POWER_DOMAIN_MFG6>;
+ power-domain-names = "core0", "core1", "core2", "core3", "core4";
+ status = "disabled";
+ };
+
mfgcfg: clock-controller@13fbf000 {
compatible = "mediatek,mt8195-mfgcfg";
reg = <0 0x13fbf000 0 0x1000>;
--
2.39.2
Enable the Mali-G57 found on this platform with the open-source
Panfrost driver.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
index 56749cfe7c33..24669093fbed 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
@@ -238,6 +238,11 @@ dptx_out: endpoint {
};
};
+&gpu {
+ status = "okay";
+ mali-supply = <&mt6315_7_vbuck1>;
+};
+
&i2c0 {
status = "okay";
--
2.39.2
Add a GPU node for MT8186 SoC but keep it disabled.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index a0d3e1f731bd..78ff8ba5718e 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -1075,6 +1075,23 @@ mfgsys: clock-controller@13000000 {
#clock-cells = <1>;
};
+ gpu: gpu@13040000 {
+ compatible = "mediatek,mt8186-mali",
+ "arm,mali-bifrost";
+ reg = <0 0x13040000 0 0x4000>;
+
+ clocks = <&mfgsys CLK_MFG_BG3D>;
+ interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "job", "mmu", "gpu";
+ power-domains = <&spm MT8186_POWER_DOMAIN_MFG2>,
+ <&spm MT8186_POWER_DOMAIN_MFG3>;
+ power-domain-names = "core0", "core1";
+ #cooling-cells = <2>;
+ status = "disabled";
+ };
+
mmsys: syscon@14000000 {
compatible = "mediatek,mt8186-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
--
2.39.2
Override the PMIC-default voltage constraints for VGPU and VSRAM_GPU
with the platform specific vmin/vmax for the highest possible SoC
binning.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Suggested-by: Chen-Yu Tsai <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts
index c228f04d086b..526bcae7a3f8 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts
@@ -176,11 +176,17 @@ &mmc1 {
};
&mt6358_vgpu_reg {
+ regulator-min-microvolt = <625000>;
+ regulator-max-microvolt = <900000>;
+
regulator-coupled-with = <&mt6358_vsram_gpu_reg>;
regulator-coupled-max-spread = <100000>;
};
&mt6358_vsram_gpu_reg {
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1000000>;
+
regulator-coupled-with = <&mt6358_vgpu_reg>;
regulator-coupled-max-spread = <100000>;
};
--
2.39.2
Override the PMIC-default voltage constraints for VGPU and VSRAM_GPU
with the platform specific vmin/vmax for the highest possible SoC
binning.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Suggested-by: Chen-Yu Tsai <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
index fd327437e932..3e3f4b1b00f0 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
@@ -138,11 +138,17 @@ &mmc1 {
};
&mt6358_vgpu_reg {
+ regulator-min-microvolt = <625000>;
+ regulator-max-microvolt = <900000>;
+
regulator-coupled-with = <&mt6358_vsram_gpu_reg>;
regulator-coupled-max-spread = <100000>;
};
&mt6358_vsram_gpu_reg {
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1000000>;
+
regulator-coupled-with = <&mt6358_vgpu_reg>;
regulator-coupled-max-spread = <100000>;
};
--
2.39.2
Series looks good but from my understanding has a dependency on:
[PATCH v4 00/12] Panfrost: Improve and add MediaTek SoCs support
(https://lore.kernel.org/linux-mediatek/[email protected]/)
Did I get that right?
Regards,
Matthias
On 01/03/2023 10:55, AngeloGioacchino Del Regno wrote:
> Changes in v4:
> - Added a fix for MT8192 Vgpu voltage constraints
> - Changed constraints for MT8192 VSRAM-GPU to reflect the maximum
> achievable voltage as per the actual vsram-vgpu relation constraint
>
> Changes in v3:
> - Changed MT8186 compatibles for new bindings
> - Added min/max voltage overrides for vgpu/vsram_gpu on
> mt8183-pumpkin and evb as suggested by Chen-Yu
> - Cosmetic fixes for "arm64: dts: mediatek: mt8192: Add GPU nodes"
>
> Changes in v2:
> - Changed MT8186 to use only two power domains for the GPU.
>
> We finally have working GPU DVFS on MediaTek SoCs.
> On Panfrost.
> For real.
> ...and the best part is that it's going upstream.
>
> In order to get GPU DVFS working, it was necessary to satisfy a
> specific constraint (which is different, depending on the SoC)
> between two regulators: GPU VCORE and GPU SRAM.
> This was done through adding the mtk-regulator-coupler driver,
> which transparently manages the voltage relation between these
> two vregs, hence completely eliminating the need to manage these
> regulators in the Panfrost driver; this solves the long standing
> issue with devfreq+opp tables not supporting managing voltages
> for two regulators per opp entry out of the box, due to which
> we never got GPU DVFS on those SoCs, often locking them out to
> a low GPU frequency.
>
> This changes. Right now!
>
> Tested on MT8192, MT8195 Chromebooks.
>
> This series depends on [1].
>
> [1]: https://lore.kernel.org/lkml/[email protected]/
>
> Alyssa Rosenzweig (2):
> arm64: dts: mediatek: mt8192: Add GPU nodes
> arm64: dts: mediatek: mt8192-asurada: Enable GPU
>
> AngeloGioacchino Del Regno (16):
> arm64: dts: mediatek: mt8183-kukui: Couple VGPU and VSRAM_GPU
> regulators
> arm64: dts: mediatek: mt8183-kukui: Override vgpu/vsram_gpu
> constraints
> arm64: dts: mediatek: mt8183: Remove second opp-microvolt entries from
> gpu table
> arm64: dts: mt8183-pumpkin: Couple VGPU and VSRAM_GPU regulators
> arm64: dts: mediatek: mt8183-evb: Couple VGPU and VSRAM_GPU regulators
> arm64: dts: mediatek: mt8183: Use mediatek,mt8183b-mali as GPU
> compatible
> arm64: dts: mediatek: mt8192: Add mfg_ref_sel clock to MFG0 domain
> arm64: dts: mediatek: mt8192-asurada: Assign sram supply to MFG1 pd
> arm64: dts: mediatek: mt8192-asurada: Fix voltage constraint for Vgpu
> arm64: dts: mediatek: mt8192-asurada: Couple VGPU and VSRAM_OTHER
> regulators
> arm64: dts: mediatek: mt8195: Add mfg_core_tmp clock to MFG1 domain
> arm64: dts: mt8195: Add panfrost node for Mali-G57 Valhall Natt GPU
> arm64: dts: mediatek: mt8195-cherry: Enable Mali-G57 GPU
> arm64: dts: mediatek: mt8186: Add GPU node
> arm64: dts: mediatek: mt8183-pumpkin: Override vgpu/vsram_gpu
> constraints
> arm64: dts: mediatek: mt8183-evb: Override vgpu/vsram_gpu constraints
>
> Nícolas F. R. A. Prado (1):
> arm64: dts: mediatek: mt8192-asurada: Add MFG0 domain supply
>
> arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 17 ++-
> .../arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 17 ++-
> .../boot/dts/mediatek/mt8183-pumpkin.dts | 17 ++-
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 34 ++---
> arch/arm64/boot/dts/mediatek/mt8186.dtsi | 17 +++
> .../boot/dts/mediatek/mt8192-asurada.dtsi | 24 +++-
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 116 +++++++++++++++++-
> .../boot/dts/mediatek/mt8195-cherry.dtsi | 5 +
> arch/arm64/boot/dts/mediatek/mt8195.dtsi | 95 +++++++++++++-
> 9 files changed, 315 insertions(+), 27 deletions(-)
>
On Wed, Mar 1, 2023 at 5:55 PM AngeloGioacchino Del Regno
<[email protected]> wrote:
>
> The MT8192 SoC specifies a maximum voltage for the GPU's digital supply
> of 0.88V and the GPU OPPs are declaring a maximum voltage of 0.80V.
>
> In order to keep the GPU voltage in the safe range, change the maximum
> voltage for mt6315@7's vbuck1 to 0.80V as sending, for any mistake,
> 1.193V would be catastrophic.
>
> Fixes: 3183cb62b033 ("arm64: dts: mediatek: asurada: Add SPMI regulators")
> Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Chen-yu Tsai <[email protected]>
On Wed, Mar 1, 2023 at 5:55 PM AngeloGioacchino Del Regno
<[email protected]> wrote:
>
> Add coupling for these regulators, as VSRAM_OTHER is used to power the
> GPU SRAM, and they have a strict voltage output relation to satisfy in
> order to ensure GPU stable operation.
> While at it, also add voltage constraint overrides for the GPU SRAM
> regulator "mt6359_vsram_others" so that we stay in a safe range of
> 0.75-0.80V.
>
> Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
> ---
> arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
> index 8570b78c04a4..f858eca219d7 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
> @@ -447,6 +447,13 @@ &mt6359_vrf12_ldo_reg {
> regulator-always-on;
> };
>
> +&mt6359_vsram_others_ldo_reg {
> + regulator-min-microvolt = <750000>;
> + regulator-max-microvolt = <800000>;
> + regulator-coupled-with = <&mt6315_7_vbuck1>;
> + regulator-coupled-max-spread = <10000>;
Looking again at the downstream OPP table, it seems there's no voltage
difference requirement. It only needs V_SRAM >= V_GPU. Same applies to
MT8195. Looks like only MT8183 and MT8186 need V_SRAM - V_GPU >= 10000.
Would setting max-spread to 0 work? I ask because with both regulator's
maximum voltage set to 0.8V, there's no way we can reach the highest
OPP.
ChenYu
> +};
> +
> &mt6359_vufs_ldo_reg {
> regulator-always-on;
> };
> @@ -1411,6 +1418,8 @@ mt6315_7_vbuck1: vbuck1 {
> regulator-max-microvolt = <800000>;
> regulator-enable-ramp-delay = <256>;
> regulator-allowed-modes = <0 1 2>;
> + regulator-coupled-with = <&mt6359_vsram_others_ldo_reg>;
> + regulator-coupled-max-spread = <10000>;
> };
> };
> };
> --
> 2.39.2
>
Il 02/03/23 10:36, Matthias Brugger ha scritto:
> Series looks good but from my understanding has a dependency on:
> [PATCH v4 00/12] Panfrost: Improve and add MediaTek SoCs support
> (https://lore.kernel.org/linux-mediatek/[email protected]/)
>
> Did I get that right?
>
Yes you got it right - without the mentioned series, this one will do nothing
at all (and will also fail binding checks, as the bindings are introduced in
that other series).
Cheers,
Angelo
> Regards,
> Matthias
>
> On 01/03/2023 10:55, AngeloGioacchino Del Regno wrote:
>> Changes in v4:
>> - Added a fix for MT8192 Vgpu voltage constraints
>> - Changed constraints for MT8192 VSRAM-GPU to reflect the maximum
>> achievable voltage as per the actual vsram-vgpu relation constraint
>>
>> Changes in v3:
>> - Changed MT8186 compatibles for new bindings
>> - Added min/max voltage overrides for vgpu/vsram_gpu on
>> mt8183-pumpkin and evb as suggested by Chen-Yu
>> - Cosmetic fixes for "arm64: dts: mediatek: mt8192: Add GPU nodes"
>>
>> Changes in v2:
>> - Changed MT8186 to use only two power domains for the GPU.
>>
>> We finally have working GPU DVFS on MediaTek SoCs.
>> On Panfrost.
>> For real.
>> ...and the best part is that it's going upstream.
>>
>> In order to get GPU DVFS working, it was necessary to satisfy a
>> specific constraint (which is different, depending on the SoC)
>> between two regulators: GPU VCORE and GPU SRAM.
>> This was done through adding the mtk-regulator-coupler driver,
>> which transparently manages the voltage relation between these
>> two vregs, hence completely eliminating the need to manage these
>> regulators in the Panfrost driver; this solves the long standing
>> issue with devfreq+opp tables not supporting managing voltages
>> for two regulators per opp entry out of the box, due to which
>> we never got GPU DVFS on those SoCs, often locking them out to
>> a low GPU frequency.
>>
>> This changes. Right now!
>>
>> Tested on MT8192, MT8195 Chromebooks.
>>
>> This series depends on [1].
>>
>> [1]:
>> https://lore.kernel.org/lkml/[email protected]/
>>
>> Alyssa Rosenzweig (2):
>> arm64: dts: mediatek: mt8192: Add GPU nodes
>> arm64: dts: mediatek: mt8192-asurada: Enable GPU
>>
>> AngeloGioacchino Del Regno (16):
>> arm64: dts: mediatek: mt8183-kukui: Couple VGPU and VSRAM_GPU
>> regulators
>> arm64: dts: mediatek: mt8183-kukui: Override vgpu/vsram_gpu
>> constraints
>> arm64: dts: mediatek: mt8183: Remove second opp-microvolt entries from
>> gpu table
>> arm64: dts: mt8183-pumpkin: Couple VGPU and VSRAM_GPU regulators
>> arm64: dts: mediatek: mt8183-evb: Couple VGPU and VSRAM_GPU regulators
>> arm64: dts: mediatek: mt8183: Use mediatek,mt8183b-mali as GPU
>> compatible
>> arm64: dts: mediatek: mt8192: Add mfg_ref_sel clock to MFG0 domain
>> arm64: dts: mediatek: mt8192-asurada: Assign sram supply to MFG1 pd
>> arm64: dts: mediatek: mt8192-asurada: Fix voltage constraint for Vgpu
>> arm64: dts: mediatek: mt8192-asurada: Couple VGPU and VSRAM_OTHER
>> regulators
>> arm64: dts: mediatek: mt8195: Add mfg_core_tmp clock to MFG1 domain
>> arm64: dts: mt8195: Add panfrost node for Mali-G57 Valhall Natt GPU
>> arm64: dts: mediatek: mt8195-cherry: Enable Mali-G57 GPU
>> arm64: dts: mediatek: mt8186: Add GPU node
>> arm64: dts: mediatek: mt8183-pumpkin: Override vgpu/vsram_gpu
>> constraints
>> arm64: dts: mediatek: mt8183-evb: Override vgpu/vsram_gpu constraints
>>
>> Nícolas F. R. A. Prado (1):
>> arm64: dts: mediatek: mt8192-asurada: Add MFG0 domain supply
>>
>> arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 17 ++-
>> .../arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 17 ++-
>> .../boot/dts/mediatek/mt8183-pumpkin.dts | 17 ++-
>> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 34 ++---
>> arch/arm64/boot/dts/mediatek/mt8186.dtsi | 17 +++
>> .../boot/dts/mediatek/mt8192-asurada.dtsi | 24 +++-
>> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 116 +++++++++++++++++-
>> .../boot/dts/mediatek/mt8195-cherry.dtsi | 5 +
>> arch/arm64/boot/dts/mediatek/mt8195.dtsi | 95 +++++++++++++-
>> 9 files changed, 315 insertions(+), 27 deletions(-)
>>
--
AngeloGioacchino Del Regno
Software Engineer
Collabora Ltd.
Platinum Building, St John's Innovation Park, Cambridge CB4 0DS, UK
Registered in England & Wales, no. 5513718
On Thu, Mar 2, 2023 at 6:10 PM AngeloGioacchino Del Regno
<[email protected]> wrote:
>
> Il 02/03/23 10:36, Matthias Brugger ha scritto:
> > Series looks good but from my understanding has a dependency on:
> > [PATCH v4 00/12] Panfrost: Improve and add MediaTek SoCs support
> > (https://lore.kernel.org/linux-mediatek/[email protected]/)
> >
> > Did I get that right?
> >
>
> Yes you got it right - without the mentioned series, this one will do nothing
> at all (and will also fail binding checks, as the bindings are introduced in
> that other series).
Please also let me test them on MT8183 and MT8186 before merging them.
ChenYu
Il 02/03/23 11:03, Chen-Yu Tsai ha scritto:
> On Wed, Mar 1, 2023 at 5:55 PM AngeloGioacchino Del Regno
> <[email protected]> wrote:
>>
>> Add coupling for these regulators, as VSRAM_OTHER is used to power the
>> GPU SRAM, and they have a strict voltage output relation to satisfy in
>> order to ensure GPU stable operation.
>> While at it, also add voltage constraint overrides for the GPU SRAM
>> regulator "mt6359_vsram_others" so that we stay in a safe range of
>> 0.75-0.80V.
>>
>> Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
>> ---
>> arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 9 +++++++++
>> 1 file changed, 9 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
>> index 8570b78c04a4..f858eca219d7 100644
>> --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
>> +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
>> @@ -447,6 +447,13 @@ &mt6359_vrf12_ldo_reg {
>> regulator-always-on;
>> };
>>
>> +&mt6359_vsram_others_ldo_reg {
>> + regulator-min-microvolt = <750000>;
>> + regulator-max-microvolt = <800000>;
>> + regulator-coupled-with = <&mt6315_7_vbuck1>;
>> + regulator-coupled-max-spread = <10000>;
>
> Looking again at the downstream OPP table, it seems there's no voltage
> difference requirement. It only needs V_SRAM >= V_GPU. Same applies to
> MT8195. Looks like only MT8183 and MT8186 need V_SRAM - V_GPU >= 10000.
On MT8195 we don't need any regulator coupling. There, the GPU-SRAM voltage
is fixed at .. I don't remember, 0.7V? - anyway - MT8195 doesn't need to
scale the vsram.
>
> Would setting max-spread to 0 work? I ask because with both regulator's
> maximum voltage set to 0.8V, there's no way we can reach the highest
> OPP.
>
No that doesn't work. I can raise the Vgpu max voltage to 0.88V to solve the
issue right here and right now, or we can leave it like that and revisit it
later.
I would at this point go for setting mt6315_7_vbuck1's max-microvolt to
880000, as this is the maximum recommended voltage for the GPU as per the
MT8192 datasheet, it would also make sense as we would be still describing
the hardware in a correct manner.
What do you think?
Angelo
> ChenYu
>
>
>> +};
>> +
>> &mt6359_vufs_ldo_reg {
>> regulator-always-on;
>> };
>> @@ -1411,6 +1418,8 @@ mt6315_7_vbuck1: vbuck1 {
>> regulator-max-microvolt = <800000>;
>> regulator-enable-ramp-delay = <256>;
>> regulator-allowed-modes = <0 1 2>;
>> + regulator-coupled-with = <&mt6359_vsram_others_ldo_reg>;
>> + regulator-coupled-max-spread = <10000>;
>> };
>> };
>> };
>> --
>> 2.39.2
>>
--
AngeloGioacchino Del Regno
Software Engineer
Collabora Ltd.
Platinum Building, St John's Innovation Park, Cambridge CB4 0DS, UK
Registered in England & Wales, no. 5513718
On 02/03/2023 11:11, Chen-Yu Tsai wrote:
> On Thu, Mar 2, 2023 at 6:10 PM AngeloGioacchino Del Regno
> <[email protected]> wrote:
>>
>> Il 02/03/23 10:36, Matthias Brugger ha scritto:
>>> Series looks good but from my understanding has a dependency on:
>>> [PATCH v4 00/12] Panfrost: Improve and add MediaTek SoCs support
>>> (https://lore.kernel.org/linux-mediatek/[email protected]/)
>>>
>>> Did I get that right?
>>>
>>
>> Yes you got it right - without the mentioned series, this one will do nothing
>> at all (and will also fail binding checks, as the bindings are introduced in
>> that other series).
>
> Please also let me test them on MT8183 and MT8186 before merging them.
>
Of course, I'll wait for your tested-by tags then.
Thanks for testing!
Matthias
On Thu, Mar 2, 2023 at 6:17 PM AngeloGioacchino Del Regno
<[email protected]> wrote:
>
> Il 02/03/23 11:03, Chen-Yu Tsai ha scritto:
> > On Wed, Mar 1, 2023 at 5:55 PM AngeloGioacchino Del Regno
> > <[email protected]> wrote:
> >>
> >> Add coupling for these regulators, as VSRAM_OTHER is used to power the
> >> GPU SRAM, and they have a strict voltage output relation to satisfy in
> >> order to ensure GPU stable operation.
> >> While at it, also add voltage constraint overrides for the GPU SRAM
> >> regulator "mt6359_vsram_others" so that we stay in a safe range of
> >> 0.75-0.80V.
> >>
> >> Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
> >> ---
> >> arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 9 +++++++++
> >> 1 file changed, 9 insertions(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
> >> index 8570b78c04a4..f858eca219d7 100644
> >> --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
> >> +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
> >> @@ -447,6 +447,13 @@ &mt6359_vrf12_ldo_reg {
> >> regulator-always-on;
> >> };
> >>
> >> +&mt6359_vsram_others_ldo_reg {
> >> + regulator-min-microvolt = <750000>;
> >> + regulator-max-microvolt = <800000>;
> >> + regulator-coupled-with = <&mt6315_7_vbuck1>;
> >> + regulator-coupled-max-spread = <10000>;
> >
> > Looking again at the downstream OPP table, it seems there's no voltage
> > difference requirement. It only needs V_SRAM >= V_GPU. Same applies to
> > MT8195. Looks like only MT8183 and MT8186 need V_SRAM - V_GPU >= 10000.
>
> On MT8195 we don't need any regulator coupling. There, the GPU-SRAM voltage
> is fixed at .. I don't remember, 0.7V? - anyway - MT8195 doesn't need to
> scale the vsram.
Looks like it's fixed at 0.75V. I guess we're Ok on MT8195.
> >
> > Would setting max-spread to 0 work? I ask because with both regulator's
> > maximum voltage set to 0.8V, there's no way we can reach the highest
> > OPP.
> >
>
> No that doesn't work. I can raise the Vgpu max voltage to 0.88V to solve the
> issue right here and right now, or we can leave it like that and revisit it
> later.
>
> I would at this point go for setting mt6315_7_vbuck1's max-microvolt to
> 880000, as this is the maximum recommended voltage for the GPU as per the
> MT8192 datasheet, it would also make sense as we would be still describing
> the hardware in a correct manner.
>
> What do you think?
If it's just to accommodate the coupler stuff, I say just set the maximum
at the lowest possible setting that satisfies the coupler constraint and
granularity of the regulator. The regulator does 6250 uV steps, so I guess
we could set the maximum at 812500 uV, with a comment stating the nominal
voltage of 800000 uV and that the extra 12500 uV is to workaround coupler
limitations.
Does that sound OK?
ChenYu
On Fri, Mar 3, 2023 at 12:09 PM Chen-Yu Tsai <[email protected]> wrote:
>
> On Thu, Mar 2, 2023 at 6:17 PM AngeloGioacchino Del Regno
> <[email protected]> wrote:
> >
> > Il 02/03/23 11:03, Chen-Yu Tsai ha scritto:
> > > On Wed, Mar 1, 2023 at 5:55 PM AngeloGioacchino Del Regno
> > > <[email protected]> wrote:
> > >>
> > >> Add coupling for these regulators, as VSRAM_OTHER is used to power the
> > >> GPU SRAM, and they have a strict voltage output relation to satisfy in
> > >> order to ensure GPU stable operation.
> > >> While at it, also add voltage constraint overrides for the GPU SRAM
> > >> regulator "mt6359_vsram_others" so that we stay in a safe range of
> > >> 0.75-0.80V.
> > >>
> > >> Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
> > >> ---
> > >> arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 9 +++++++++
> > >> 1 file changed, 9 insertions(+)
> > >>
> > >> diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
> > >> index 8570b78c04a4..f858eca219d7 100644
> > >> --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
> > >> +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
> > >> @@ -447,6 +447,13 @@ &mt6359_vrf12_ldo_reg {
> > >> regulator-always-on;
> > >> };
> > >>
> > >> +&mt6359_vsram_others_ldo_reg {
> > >> + regulator-min-microvolt = <750000>;
> > >> + regulator-max-microvolt = <800000>;
> > >> + regulator-coupled-with = <&mt6315_7_vbuck1>;
> > >> + regulator-coupled-max-spread = <10000>;
> > >
> > > Looking again at the downstream OPP table, it seems there's no voltage
> > > difference requirement. It only needs V_SRAM >= V_GPU. Same applies to
> > > MT8195. Looks like only MT8183 and MT8186 need V_SRAM - V_GPU >= 10000.
> >
> > On MT8195 we don't need any regulator coupling. There, the GPU-SRAM voltage
> > is fixed at .. I don't remember, 0.7V? - anyway - MT8195 doesn't need to
> > scale the vsram.
>
> Looks like it's fixed at 0.75V. I guess we're Ok on MT8195.
>
> > >
> > > Would setting max-spread to 0 work? I ask because with both regulator's
> > > maximum voltage set to 0.8V, there's no way we can reach the highest
> > > OPP.
> > >
> >
> > No that doesn't work. I can raise the Vgpu max voltage to 0.88V to solve the
> > issue right here and right now, or we can leave it like that and revisit it
> > later.
> >
> > I would at this point go for setting mt6315_7_vbuck1's max-microvolt to
> > 880000, as this is the maximum recommended voltage for the GPU as per the
> > MT8192 datasheet, it would also make sense as we would be still describing
> > the hardware in a correct manner.
> >
> > What do you think?
>
> If it's just to accommodate the coupler stuff, I say just set the maximum
> at the lowest possible setting that satisfies the coupler constraint and
> granularity of the regulator. The regulator does 6250 uV steps, so I guess
> we could set the maximum at 812500 uV, with a comment stating the nominal
> voltage of 800000 uV and that the extra 12500 uV is to workaround coupler
> limitations.
>
> Does that sound OK?
Even without changing anything, the coupler seems to work OK:
vsram_others 1 1 0 normal 800mV
0mA 750mV 800mV
10006000.syscon:power-controller-domain 1
0mA 0mV 0mV
Vgpu 2 2 0 normal 800mV
0mA 606mV 800mV
13000000.gpu-mali 1
0mA 800mV 800mV
10006000.syscon:power-controller-domain 1
0mA 0mV 0mV
Am I missing something?
ChenYu
On Thu, Mar 2, 2023 at 7:28 PM Matthias Brugger <[email protected]> wrote:
> On 02/03/2023 11:11, Chen-Yu Tsai wrote:
> > On Thu, Mar 2, 2023 at 6:10 PM AngeloGioacchino Del Regno
> > <[email protected]> wrote:
> >>
> >> Il 02/03/23 10:36, Matthias Brugger ha scritto:
> >>> Series looks good but from my understanding has a dependency on:
> >>> [PATCH v4 00/12] Panfrost: Improve and add MediaTek SoCs support
> >>> (https://lore.kernel.org/linux-mediatek/[email protected]/)
> >>>
> >>> Did I get that right?
> >>>
> >>
> >> Yes you got it right - without the mentioned series, this one will do nothing
> >> at all (and will also fail binding checks, as the bindings are introduced in
> >> that other series).
> >
> > Please also let me test them on MT8183 and MT8186 before merging them.
> >
>
> Of course, I'll wait for your tested-by tags then.
> Thanks for testing!
Tested-by: Chen-Yu Tsai <[email protected]>
on MT8183, MT8186, MT8192 and MT8195 Chromebooks.
BTW, Angelo, I see that Panfrost keeps the GPU regulator enabled, but
the power domains, and thus the SRAM regulator, get powered off when
the GPU is not in use. There doesn't seem to be any damaging effects,
but I worry about idle power consumption.
ChenYu
Il 07/03/23 10:24, Chen-Yu Tsai ha scritto:
> On Fri, Mar 3, 2023 at 12:09 PM Chen-Yu Tsai <[email protected]> wrote:
>>
>> On Thu, Mar 2, 2023 at 6:17 PM AngeloGioacchino Del Regno
>> <[email protected]> wrote:
>>>
>>> Il 02/03/23 11:03, Chen-Yu Tsai ha scritto:
>>>> On Wed, Mar 1, 2023 at 5:55 PM AngeloGioacchino Del Regno
>>>> <[email protected]> wrote:
>>>>>
>>>>> Add coupling for these regulators, as VSRAM_OTHER is used to power the
>>>>> GPU SRAM, and they have a strict voltage output relation to satisfy in
>>>>> order to ensure GPU stable operation.
>>>>> While at it, also add voltage constraint overrides for the GPU SRAM
>>>>> regulator "mt6359_vsram_others" so that we stay in a safe range of
>>>>> 0.75-0.80V.
>>>>>
>>>>> Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
>>>>> ---
>>>>> arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 9 +++++++++
>>>>> 1 file changed, 9 insertions(+)
>>>>>
>>>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
>>>>> index 8570b78c04a4..f858eca219d7 100644
>>>>> --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
>>>>> +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
>>>>> @@ -447,6 +447,13 @@ &mt6359_vrf12_ldo_reg {
>>>>> regulator-always-on;
>>>>> };
>>>>>
>>>>> +&mt6359_vsram_others_ldo_reg {
>>>>> + regulator-min-microvolt = <750000>;
>>>>> + regulator-max-microvolt = <800000>;
>>>>> + regulator-coupled-with = <&mt6315_7_vbuck1>;
>>>>> + regulator-coupled-max-spread = <10000>;
>>>>
>>>> Looking again at the downstream OPP table, it seems there's no voltage
>>>> difference requirement. It only needs V_SRAM >= V_GPU. Same applies to
>>>> MT8195. Looks like only MT8183 and MT8186 need V_SRAM - V_GPU >= 10000.
>>>
>>> On MT8195 we don't need any regulator coupling. There, the GPU-SRAM voltage
>>> is fixed at .. I don't remember, 0.7V? - anyway - MT8195 doesn't need to
>>> scale the vsram.
>>
>> Looks like it's fixed at 0.75V. I guess we're Ok on MT8195.
>>
>>>>
>>>> Would setting max-spread to 0 work? I ask because with both regulator's
>>>> maximum voltage set to 0.8V, there's no way we can reach the highest
>>>> OPP.
>>>>
>>>
>>> No that doesn't work. I can raise the Vgpu max voltage to 0.88V to solve the
>>> issue right here and right now, or we can leave it like that and revisit it
>>> later.
>>>
>>> I would at this point go for setting mt6315_7_vbuck1's max-microvolt to
>>> 880000, as this is the maximum recommended voltage for the GPU as per the
>>> MT8192 datasheet, it would also make sense as we would be still describing
>>> the hardware in a correct manner.
>>>
>>> What do you think?
>>
>> If it's just to accommodate the coupler stuff, I say just set the maximum
>> at the lowest possible setting that satisfies the coupler constraint and
>> granularity of the regulator. The regulator does 6250 uV steps, so I guess
>> we could set the maximum at 812500 uV, with a comment stating the nominal
>> voltage of 800000 uV and that the extra 12500 uV is to workaround coupler
>> limitations.
>>
>> Does that sound OK?
>
> Even without changing anything, the coupler seems to work OK:
>
> vsram_others 1 1 0 normal 800mV
> 0mA 750mV 800mV
> 10006000.syscon:power-controller-domain 1
> 0mA 0mV 0mV
> Vgpu 2 2 0 normal 800mV
> 0mA 606mV 800mV
> 13000000.gpu-mali 1
> 0mA 800mV 800mV
> 10006000.syscon:power-controller-domain 1
> 0mA 0mV 0mV
>
> Am I missing something?
>
I don't think you are... I may be getting confused by all of the changesets
that I'm pushing at once.
Hence, is this commit fine as it is?
Regards,
Angelo
Il 07/03/23 10:27, Chen-Yu Tsai ha scritto:
> On Thu, Mar 2, 2023 at 7:28 PM Matthias Brugger <[email protected]> wrote:
>> On 02/03/2023 11:11, Chen-Yu Tsai wrote:
>>> On Thu, Mar 2, 2023 at 6:10 PM AngeloGioacchino Del Regno
>>> <[email protected]> wrote:
>>>>
>>>> Il 02/03/23 10:36, Matthias Brugger ha scritto:
>>>>> Series looks good but from my understanding has a dependency on:
>>>>> [PATCH v4 00/12] Panfrost: Improve and add MediaTek SoCs support
>>>>> (https://lore.kernel.org/linux-mediatek/[email protected]/)
>>>>>
>>>>> Did I get that right?
>>>>>
>>>>
>>>> Yes you got it right - without the mentioned series, this one will do nothing
>>>> at all (and will also fail binding checks, as the bindings are introduced in
>>>> that other series).
>>>
>>> Please also let me test them on MT8183 and MT8186 before merging them.
>>>
>>
>> Of course, I'll wait for your tested-by tags then.
>> Thanks for testing!
>
> Tested-by: Chen-Yu Tsai <[email protected]>
>
> on MT8183, MT8186, MT8192 and MT8195 Chromebooks.
>
> BTW, Angelo, I see that Panfrost keeps the GPU regulator enabled, but
> the power domains, and thus the SRAM regulator, get powered off when
> the GPU is not in use. There doesn't seem to be any damaging effects,
> but I worry about idle power consumption.
>
> ChenYu
Yes I've seen that as well... and it's true there will be some unwanted
small power leakage.
Though, I would propose to do things step by step. Right now, as it is, the
platform is fully stable... so let's get this in so that we estabilish a
known working baseline... what I have in mind is, exactly:
1. Get Panfrost+DVFS working on current platforms; then
2. Resolve the GPU binning situation (eFuses -> opp-supported-hw)
3. Improve the power consumption (all GPU regulators off during suspend)
Thanks for all the valuable testing and support!
Cheers,
Angelo
On Tue, Mar 7, 2023 at 5:30 PM AngeloGioacchino Del Regno
<[email protected]> wrote:
>
> Il 07/03/23 10:24, Chen-Yu Tsai ha scritto:
> > On Fri, Mar 3, 2023 at 12:09 PM Chen-Yu Tsai <[email protected]> wrote:
> >>
> >> On Thu, Mar 2, 2023 at 6:17 PM AngeloGioacchino Del Regno
> >> <[email protected]> wrote:
> >>>
> >>> Il 02/03/23 11:03, Chen-Yu Tsai ha scritto:
> >>>> On Wed, Mar 1, 2023 at 5:55 PM AngeloGioacchino Del Regno
> >>>> <[email protected]> wrote:
> >>>>>
> >>>>> Add coupling for these regulators, as VSRAM_OTHER is used to power the
> >>>>> GPU SRAM, and they have a strict voltage output relation to satisfy in
> >>>>> order to ensure GPU stable operation.
> >>>>> While at it, also add voltage constraint overrides for the GPU SRAM
> >>>>> regulator "mt6359_vsram_others" so that we stay in a safe range of
> >>>>> 0.75-0.80V.
> >>>>>
> >>>>> Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
> >>>>> ---
> >>>>> arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 9 +++++++++
> >>>>> 1 file changed, 9 insertions(+)
> >>>>>
> >>>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
> >>>>> index 8570b78c04a4..f858eca219d7 100644
> >>>>> --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
> >>>>> +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
> >>>>> @@ -447,6 +447,13 @@ &mt6359_vrf12_ldo_reg {
> >>>>> regulator-always-on;
> >>>>> };
> >>>>>
> >>>>> +&mt6359_vsram_others_ldo_reg {
> >>>>> + regulator-min-microvolt = <750000>;
> >>>>> + regulator-max-microvolt = <800000>;
> >>>>> + regulator-coupled-with = <&mt6315_7_vbuck1>;
> >>>>> + regulator-coupled-max-spread = <10000>;
> >>>>
> >>>> Looking again at the downstream OPP table, it seems there's no voltage
> >>>> difference requirement. It only needs V_SRAM >= V_GPU. Same applies to
> >>>> MT8195. Looks like only MT8183 and MT8186 need V_SRAM - V_GPU >= 10000.
> >>>
> >>> On MT8195 we don't need any regulator coupling. There, the GPU-SRAM voltage
> >>> is fixed at .. I don't remember, 0.7V? - anyway - MT8195 doesn't need to
> >>> scale the vsram.
> >>
> >> Looks like it's fixed at 0.75V. I guess we're Ok on MT8195.
> >>
> >>>>
> >>>> Would setting max-spread to 0 work? I ask because with both regulator's
> >>>> maximum voltage set to 0.8V, there's no way we can reach the highest
> >>>> OPP.
> >>>>
> >>>
> >>> No that doesn't work. I can raise the Vgpu max voltage to 0.88V to solve the
> >>> issue right here and right now, or we can leave it like that and revisit it
> >>> later.
> >>>
> >>> I would at this point go for setting mt6315_7_vbuck1's max-microvolt to
> >>> 880000, as this is the maximum recommended voltage for the GPU as per the
> >>> MT8192 datasheet, it would also make sense as we would be still describing
> >>> the hardware in a correct manner.
> >>>
> >>> What do you think?
> >>
> >> If it's just to accommodate the coupler stuff, I say just set the maximum
> >> at the lowest possible setting that satisfies the coupler constraint and
> >> granularity of the regulator. The regulator does 6250 uV steps, so I guess
> >> we could set the maximum at 812500 uV, with a comment stating the nominal
> >> voltage of 800000 uV and that the extra 12500 uV is to workaround coupler
> >> limitations.
> >>
> >> Does that sound OK?
> >
> > Even without changing anything, the coupler seems to work OK:
> >
> > vsram_others 1 1 0 normal 800mV
> > 0mA 750mV 800mV
> > 10006000.syscon:power-controller-domain 1
> > 0mA 0mV 0mV
> > Vgpu 2 2 0 normal 800mV
> > 0mA 606mV 800mV
> > 13000000.gpu-mali 1
> > 0mA 800mV 800mV
> > 10006000.syscon:power-controller-domain 1
> > 0mA 0mV 0mV
> >
> > Am I missing something?
> >
>
> I don't think you are... I may be getting confused by all of the changesets
> that I'm pushing at once.
>
> Hence, is this commit fine as it is?
It works for some reason. Maybe it's a bug in the coupler. Either way I
think it works, even though the numbers might be a bit off. We can revisit
it later.
Reviewed-by: Chen-Yu Tsai <[email protected]>
Il 07/03/23 10:44, Chen-Yu Tsai ha scritto:
> On Tue, Mar 7, 2023 at 5:30 PM AngeloGioacchino Del Regno
> <[email protected]> wrote:
>>
>> Il 07/03/23 10:24, Chen-Yu Tsai ha scritto:
>>> On Fri, Mar 3, 2023 at 12:09 PM Chen-Yu Tsai <[email protected]> wrote:
>>>>
>>>> On Thu, Mar 2, 2023 at 6:17 PM AngeloGioacchino Del Regno
>>>> <[email protected]> wrote:
>>>>>
>>>>> Il 02/03/23 11:03, Chen-Yu Tsai ha scritto:
>>>>>> On Wed, Mar 1, 2023 at 5:55 PM AngeloGioacchino Del Regno
>>>>>> <[email protected]> wrote:
>>>>>>>
>>>>>>> Add coupling for these regulators, as VSRAM_OTHER is used to power the
>>>>>>> GPU SRAM, and they have a strict voltage output relation to satisfy in
>>>>>>> order to ensure GPU stable operation.
>>>>>>> While at it, also add voltage constraint overrides for the GPU SRAM
>>>>>>> regulator "mt6359_vsram_others" so that we stay in a safe range of
>>>>>>> 0.75-0.80V.
>>>>>>>
>>>>>>> Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
>>>>>>> ---
>>>>>>> arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 9 +++++++++
>>>>>>> 1 file changed, 9 insertions(+)
>>>>>>>
>>>>>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
>>>>>>> index 8570b78c04a4..f858eca219d7 100644
>>>>>>> --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
>>>>>>> +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
>>>>>>> @@ -447,6 +447,13 @@ &mt6359_vrf12_ldo_reg {
>>>>>>> regulator-always-on;
>>>>>>> };
>>>>>>>
>>>>>>> +&mt6359_vsram_others_ldo_reg {
>>>>>>> + regulator-min-microvolt = <750000>;
>>>>>>> + regulator-max-microvolt = <800000>;
>>>>>>> + regulator-coupled-with = <&mt6315_7_vbuck1>;
>>>>>>> + regulator-coupled-max-spread = <10000>;
>>>>>>
>>>>>> Looking again at the downstream OPP table, it seems there's no voltage
>>>>>> difference requirement. It only needs V_SRAM >= V_GPU. Same applies to
>>>>>> MT8195. Looks like only MT8183 and MT8186 need V_SRAM - V_GPU >= 10000.
>>>>>
>>>>> On MT8195 we don't need any regulator coupling. There, the GPU-SRAM voltage
>>>>> is fixed at .. I don't remember, 0.7V? - anyway - MT8195 doesn't need to
>>>>> scale the vsram.
>>>>
>>>> Looks like it's fixed at 0.75V. I guess we're Ok on MT8195.
>>>>
>>>>>>
>>>>>> Would setting max-spread to 0 work? I ask because with both regulator's
>>>>>> maximum voltage set to 0.8V, there's no way we can reach the highest
>>>>>> OPP.
>>>>>>
>>>>>
>>>>> No that doesn't work. I can raise the Vgpu max voltage to 0.88V to solve the
>>>>> issue right here and right now, or we can leave it like that and revisit it
>>>>> later.
>>>>>
>>>>> I would at this point go for setting mt6315_7_vbuck1's max-microvolt to
>>>>> 880000, as this is the maximum recommended voltage for the GPU as per the
>>>>> MT8192 datasheet, it would also make sense as we would be still describing
>>>>> the hardware in a correct manner.
>>>>>
>>>>> What do you think?
>>>>
>>>> If it's just to accommodate the coupler stuff, I say just set the maximum
>>>> at the lowest possible setting that satisfies the coupler constraint and
>>>> granularity of the regulator. The regulator does 6250 uV steps, so I guess
>>>> we could set the maximum at 812500 uV, with a comment stating the nominal
>>>> voltage of 800000 uV and that the extra 12500 uV is to workaround coupler
>>>> limitations.
>>>>
>>>> Does that sound OK?
>>>
>>> Even without changing anything, the coupler seems to work OK:
>>>
>>> vsram_others 1 1 0 normal 800mV
>>> 0mA 750mV 800mV
>>> 10006000.syscon:power-controller-domain 1
>>> 0mA 0mV 0mV
>>> Vgpu 2 2 0 normal 800mV
>>> 0mA 606mV 800mV
>>> 13000000.gpu-mali 1
>>> 0mA 800mV 800mV
>>> 10006000.syscon:power-controller-domain 1
>>> 0mA 0mV 0mV
>>>
>>> Am I missing something?
>>>
>>
>> I don't think you are... I may be getting confused by all of the changesets
>> that I'm pushing at once.
>>
>> Hence, is this commit fine as it is?
>
> It works for some reason. Maybe it's a bug in the coupler. Either way I
> think it works, even though the numbers might be a bit off. We can revisit
> it later.
>
> Reviewed-by: Chen-Yu Tsai <[email protected]>
Thanks!
Angelo
Il 07/03/23 10:27, Chen-Yu Tsai ha scritto:
> On Thu, Mar 2, 2023 at 7:28 PM Matthias Brugger <[email protected]> wrote:
>> On 02/03/2023 11:11, Chen-Yu Tsai wrote:
>>> On Thu, Mar 2, 2023 at 6:10 PM AngeloGioacchino Del Regno
>>> <[email protected]> wrote:
>>>>
>>>> Il 02/03/23 10:36, Matthias Brugger ha scritto:
>>>>> Series looks good but from my understanding has a dependency on:
>>>>> [PATCH v4 00/12] Panfrost: Improve and add MediaTek SoCs support
>>>>> (https://lore.kernel.org/linux-mediatek/[email protected]/)
>>>>>
>>>>> Did I get that right?
>>>>>
>>>>
>>>> Yes you got it right - without the mentioned series, this one will do nothing
>>>> at all (and will also fail binding checks, as the bindings are introduced in
>>>> that other series).
>>>
>>> Please also let me test them on MT8183 and MT8186 before merging them.
>>>
>>
>> Of course, I'll wait for your tested-by tags then.
>> Thanks for testing!
>
> Tested-by: Chen-Yu Tsai <[email protected]>
>
> on MT8183, MT8186, MT8192 and MT8195 Chromebooks.
>
Hello Matthias,
The Panfrost driver patches were just queued to drm-misc-next [1], can you please
pick this fully reviewed and fully tested series, so that we get them both to land
at the same time?
[1]: https://patchwork.kernel.org/comment/25265910/
Many thanks!
Angelo
On 01/03/2023 10:55, AngeloGioacchino Del Regno wrote:
> Changes in v4:
> - Added a fix for MT8192 Vgpu voltage constraints
> - Changed constraints for MT8192 VSRAM-GPU to reflect the maximum
> achievable voltage as per the actual vsram-vgpu relation constraint
>
> Changes in v3:
> - Changed MT8186 compatibles for new bindings
> - Added min/max voltage overrides for vgpu/vsram_gpu on
> mt8183-pumpkin and evb as suggested by Chen-Yu
> - Cosmetic fixes for "arm64: dts: mediatek: mt8192: Add GPU nodes"
>
> Changes in v2:
> - Changed MT8186 to use only two power domains for the GPU.
>
> We finally have working GPU DVFS on MediaTek SoCs.
> On Panfrost.
> For real.
> ...and the best part is that it's going upstream.
>
> In order to get GPU DVFS working, it was necessary to satisfy a
> specific constraint (which is different, depending on the SoC)
> between two regulators: GPU VCORE and GPU SRAM.
> This was done through adding the mtk-regulator-coupler driver,
> which transparently manages the voltage relation between these
> two vregs, hence completely eliminating the need to manage these
> regulators in the Panfrost driver; this solves the long standing
> issue with devfreq+opp tables not supporting managing voltages
> for two regulators per opp entry out of the box, due to which
> we never got GPU DVFS on those SoCs, often locking them out to
> a low GPU frequency.
>
> This changes. Right now!
>
> Tested on MT8192, MT8195 Chromebooks.
>
Applied, thanks!
> This series depends on [1].
>
> [1]: https://lore.kernel.org/lkml/[email protected]/
>
> Alyssa Rosenzweig (2):
> arm64: dts: mediatek: mt8192: Add GPU nodes
> arm64: dts: mediatek: mt8192-asurada: Enable GPU
>
> AngeloGioacchino Del Regno (16):
> arm64: dts: mediatek: mt8183-kukui: Couple VGPU and VSRAM_GPU
> regulators
> arm64: dts: mediatek: mt8183-kukui: Override vgpu/vsram_gpu
> constraints
> arm64: dts: mediatek: mt8183: Remove second opp-microvolt entries from
> gpu table
> arm64: dts: mt8183-pumpkin: Couple VGPU and VSRAM_GPU regulators
> arm64: dts: mediatek: mt8183-evb: Couple VGPU and VSRAM_GPU regulators
> arm64: dts: mediatek: mt8183: Use mediatek,mt8183b-mali as GPU
> compatible
> arm64: dts: mediatek: mt8192: Add mfg_ref_sel clock to MFG0 domain
> arm64: dts: mediatek: mt8192-asurada: Assign sram supply to MFG1 pd
> arm64: dts: mediatek: mt8192-asurada: Fix voltage constraint for Vgpu
> arm64: dts: mediatek: mt8192-asurada: Couple VGPU and VSRAM_OTHER
> regulators
> arm64: dts: mediatek: mt8195: Add mfg_core_tmp clock to MFG1 domain
> arm64: dts: mt8195: Add panfrost node for Mali-G57 Valhall Natt GPU
> arm64: dts: mediatek: mt8195-cherry: Enable Mali-G57 GPU
> arm64: dts: mediatek: mt8186: Add GPU node
> arm64: dts: mediatek: mt8183-pumpkin: Override vgpu/vsram_gpu
> constraints
> arm64: dts: mediatek: mt8183-evb: Override vgpu/vsram_gpu constraints
>
> Nícolas F. R. A. Prado (1):
> arm64: dts: mediatek: mt8192-asurada: Add MFG0 domain supply
>
> arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 17 ++-
> .../arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 17 ++-
> .../boot/dts/mediatek/mt8183-pumpkin.dts | 17 ++-
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 34 ++---
> arch/arm64/boot/dts/mediatek/mt8186.dtsi | 17 +++
> .../boot/dts/mediatek/mt8192-asurada.dtsi | 24 +++-
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 116 +++++++++++++++++-
> .../boot/dts/mediatek/mt8195-cherry.dtsi | 5 +
> arch/arm64/boot/dts/mediatek/mt8195.dtsi | 95 +++++++++++++-
> 9 files changed, 315 insertions(+), 27 deletions(-)
>