This series is based on matthias github, for-next.
Changes since v2:
- Remove some unnecessary linebreaks for some nodes
- Use one line for some properties
- Drop "Fix the fallback for mediatek, mt8186-disp-ccorr" patch
(since this is applied in chunkuang.hu/linux.git/log/?h=mediatek-drm-next)
- Separate GCE into another patch
- Drop some patches which are appied in matthias github
Changes since v1:
- Remove the unnecessary trailing number
- Add aliases for ovl* and rdma*
Allen-KH Cheng (7):
arm64: dts: mediatek: mt8186: Add MTU3 nodes
dt-bindings: spmi: spmi-mtk-pmif: Document mediatek,mt8195-spmi as
fallback of mediatek,mt8186-spmi
arm64: dts: mediatek: mt8186: Add SPMI node
arm64: dts: mediatek: mt8186: Add ADSP node
arm64: dts: mediatek: mt8186: Add audio controller node
arm64: dts: mediatek: mt8186: Add GCE node
arm64: dts: mediatek: mt8186: Add display nodes
.../bindings/spmi/mtk,spmi-mtk-pmif.yaml | 11 +-
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 296 ++++++++++++++++++
2 files changed, 304 insertions(+), 3 deletions(-)
--
2.18.0
Add MTU3 nodes for MT8186 SoC.
Signed-off-by: Allen-KH Cheng <[email protected]>
Tested-by: Chen-Yu Tsai <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 68 ++++++++++++++++++++++++
1 file changed, 68 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index a0d3e1f731bd..178421fd8380 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -981,6 +981,40 @@
status = "disabled";
};
+ ssusb0: usb@11201000 {
+ compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3";
+ reg = <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ clocks = <&topckgen CLK_TOP_USB_TOP>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>,
+ <&infracfg_ao CLK_INFRA_AO_ICUSB>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
+ interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>;
+ phys = <&u2port0 PHY_TYPE_USB2>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ usb_host0: usb@11200000 {
+ compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci";
+ reg = <0 0x11200000 0 0x1000>;
+ reg-names = "mac";
+ clocks = <&topckgen CLK_TOP_USB_TOP>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>,
+ <&infracfg_ao CLK_INFRA_AO_ICUSB>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
+ interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,syscon-wakeup = <&pericfg 0x420 2>;
+ wakeup-source;
+ status = "disabled";
+ };
+ };
+
mmc0: mmc@11230000 {
compatible = "mediatek,mt8186-mmc",
"mediatek,mt8183-mmc";
@@ -1012,6 +1046,40 @@
status = "disabled";
};
+ ssusb1: usb@11281000 {
+ compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3";
+ reg = <0 0x11281000 0 0x2dff>, <0 0x11283e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>,
+ <&clk26m>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
+ interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>;
+ phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB_P1>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ usb_host1: usb@11280000 {
+ compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci";
+ reg = <0 0x11280000 0 0x1000>;
+ reg-names = "mac";
+ clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>,
+ <&clk26m>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck","xhci_ck";
+ interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,syscon-wakeup = <&pericfg 0x424 2>;
+ wakeup-source;
+ status = "disabled";
+ };
+ };
+
u3phy0: t-phy@11c80000 {
compatible = "mediatek,mt8186-tphy",
"mediatek,generic-tphy-v2";
--
2.18.0
Add SPMI node for MT8186 SoC.
Signed-off-by: Allen-KH Cheng <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index 178421fd8380..0e42bdbd2cb6 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -602,6 +602,21 @@
clock-names = "spi", "wrap";
};
+ spmi: spmi@10015000 {
+ compatible = "mediatek,mt8186-spmi", "mediatek,mt8195-spmi";
+ reg = <0 0x10015000 0 0x000e00>, <0 0x1001B000 0 0x000100>;
+ reg-names = "pmif", "spmimst";
+ clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
+ <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>,
+ <&topckgen CLK_TOP_SPMI_MST>;
+ clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux";
+ assigned-clocks = <&topckgen CLK_TOP_SPMI_MST>;
+ assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
+ interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>;
+ status = "disabled";
+ };
+
systimer: timer@10017000 {
compatible = "mediatek,mt8186-timer",
"mediatek,mt6765-timer";
--
2.18.0
Add ADSP node for MT8186 SoC.
Signed-off-by: Allen-KH Cheng <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index 0e42bdbd2cb6..337bcf3c1571 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -633,6 +633,22 @@
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>;
};
+ adsp: adsp@10680000 {
+ compatible = "mediatek,mt8186-dsp";
+ reg = <0 0x10680000 0 0x2000>, <0 0x10800000 0 0x100000>,
+ <0 0x1068b000 0 0x100>, <0 0x1068f000 0 0x1000>;
+ reg-names = "cfg", "sram", "sec", "bus";
+ clocks = <&topckgen CLK_TOP_AUDIODSP>, <&topckgen CLK_TOP_ADSP_BUS>;
+ clock-names = "audiodsp", "adsp_bus";
+ assigned-clocks = <&topckgen CLK_TOP_AUDIODSP>,
+ <&topckgen CLK_TOP_ADSP_BUS>;
+ assigned-clock-parents = <&clk26m>, <&topckgen CLK_TOP_MAINPLL_D2_D2>;
+ mbox-names = "rx", "tx";
+ mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_ADSP_TOP>;
+ status = "disabled";
+ };
+
adsp_mailbox0: mailbox@10686000 {
compatible = "mediatek,mt8186-adsp-mbox";
#mbox-cells = <0>;
--
2.18.0
The mt8186-spmi is used as compatible with mt8195-spmi on the MT8186,
document this situation.
Signed-off-by: Allen-KH Cheng <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Matthias Brugger <[email protected]>
---
.../devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml b/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml
index abcbbe13723f..e4f465abcfe9 100644
--- a/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml
+++ b/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml
@@ -18,9 +18,14 @@ allOf:
properties:
compatible:
- enum:
- - mediatek,mt6873-spmi
- - mediatek,mt8195-spmi
+ oneOf:
+ - enum:
+ - mediatek,mt6873-spmi
+ - mediatek,mt8195-spmi
+ - items:
+ - enum:
+ - mediatek,mt8186-spmi
+ - const: mediatek,mt8195-spmi
reg:
maxItems: 2
--
2.18.0
Add audio controller node for MT8186 SoC.
Signed-off-by: Allen-KH Cheng <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 62 ++++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index 337bcf3c1571..f198fd8abc1d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -1046,6 +1046,68 @@
};
};
+ afe: audio-controller@11210000 {
+ compatible = "mediatek,mt8186-sound";
+ reg = <0 0x11210000 0 0x2000>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_AUDIO>,
+ <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_BCLK>,
+ <&topckgen CLK_TOP_AUDIO>,
+ <&topckgen CLK_TOP_AUD_INTBUS>,
+ <&topckgen CLK_TOP_MAINPLL_D2_D4>,
+ <&topckgen CLK_TOP_AUD_1>,
+ <&apmixedsys CLK_APMIXED_APLL1>,
+ <&topckgen CLK_TOP_AUD_2>,
+ <&apmixedsys CLK_APMIXED_APLL2>,
+ <&topckgen CLK_TOP_AUD_ENGEN1>,
+ <&topckgen CLK_TOP_APLL1_D8>,
+ <&topckgen CLK_TOP_AUD_ENGEN2>,
+ <&topckgen CLK_TOP_APLL2_D8>,
+ <&topckgen CLK_TOP_APLL_I2S0_MCK_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S1_MCK_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S2_MCK_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S4_MCK_SEL>,
+ <&topckgen CLK_TOP_APLL_TDMOUT_MCK_SEL>,
+ <&topckgen CLK_TOP_APLL12_CK_DIV0>,
+ <&topckgen CLK_TOP_APLL12_CK_DIV1>,
+ <&topckgen CLK_TOP_APLL12_CK_DIV2>,
+ <&topckgen CLK_TOP_APLL12_CK_DIV4>,
+ <&topckgen CLK_TOP_APLL12_CK_DIV_TDMOUT_M>,
+ <&topckgen CLK_TOP_AUDIO_H>,
+ <&clk26m>;
+ clock-names = "aud_infra_clk",
+ "mtkaif_26m_clk",
+ "top_mux_audio",
+ "top_mux_audio_int",
+ "top_mainpll_d2_d4",
+ "top_mux_aud_1",
+ "top_apll1_ck",
+ "top_mux_aud_2",
+ "top_apll2_ck",
+ "top_mux_aud_eng1",
+ "top_apll1_d8",
+ "top_mux_aud_eng2",
+ "top_apll2_d8",
+ "top_i2s0_m_sel",
+ "top_i2s1_m_sel",
+ "top_i2s2_m_sel",
+ "top_i2s4_m_sel",
+ "top_tdm_m_sel",
+ "top_apll12_div0",
+ "top_apll12_div1",
+ "top_apll12_div2",
+ "top_apll12_div4",
+ "top_apll12_div_tdm",
+ "top_mux_audio_h",
+ "top_clk26m_clk";
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,apmixedsys = <&apmixedsys>;
+ mediatek,infracfg = <&infracfg_ao>;
+ mediatek,topckgen = <&topckgen>;
+ resets = <&watchdog MT8186_TOPRGU_AUDIO_SW_RST>;
+ reset-names = "audiosys";
+ status = "disabled";
+ };
+
mmc0: mmc@11230000 {
compatible = "mediatek,mt8186-mmc",
"mediatek,mt8183-mmc";
--
2.18.0
Add display nodes and the GCE (Global Command Engine) properties
to the display nodes in order to enable the usage of the CMDQ
(Command Queue), which is required for operating the display.
Signed-off-by: Allen-KH Cheng <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 125 +++++++++++++++++++++++
1 file changed, 125 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index b9d5af26771e..909f1a6ae108 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -20,6 +20,13 @@
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ ovl = &ovl;
+ ovl_2l= &ovl_2l;
+ rdma0 = &rdma0;
+ rdma1 = &rdma1;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -1251,6 +1258,20 @@
reg = <0 0x14000000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
+ mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
+ <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
+ };
+
+ mutex: mutex@14001000 {
+ compatible = "mediatek,mt8186-disp-mutex";
+ reg = <0 0x14001000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
+ interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
+ <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
};
smi_common: smi@14002000 {
@@ -1284,6 +1305,49 @@
power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
};
+ ovl: ovl@14005000 {
+ compatible = "mediatek,mt8186-disp-ovl",
+ "mediatek,mt8192-disp-ovl";
+ reg = <0 0x14005000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_DISP_OVL0>;
+ interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&iommu_mm IOMMU_PORT_L0_OVL_RDMA0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
+ };
+
+ ovl_2l: ovl@14006000 {
+ compatible = "mediatek,mt8186-disp-ovl-2l",
+ "mediatek,mt8192-disp-ovl-2l";
+ reg = <0 0x14006000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
+ interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&iommu_mm IOMMU_PORT_L1_OVL_2L_RDMA0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
+ };
+
+ rdma0: rdma@14007000 {
+ compatible = "mediatek,mt8186-disp-rdma",
+ "mediatek,mt8183-disp-rdma";
+ reg = <0 0x14007000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA0>;
+ interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&iommu_mm IOMMU_PORT_L1_DISP_RDMA0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
+ };
+
+ color: color@14009000 {
+ compatible = "mediatek,mt8186-disp-color",
+ "mediatek,mt8173-disp-color";
+ reg = <0 0x14009000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+ interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
+ };
+
dpi: dpi@1400a000 {
compatible = "mediatek,mt8186-dpi";
reg = <0 0x1400a000 0 0x1000>;
@@ -1301,6 +1365,56 @@
};
};
+ ccorr: ccorr@1400b000 {
+ compatible = "mediatek,mt8186-disp-ccorr",
+ "mediatek,mt8192-disp-ccorr";
+ reg = <0 0x1400b000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+ interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
+ };
+
+ aal: aal@1400c000 {
+ compatible = "mediatek,mt8186-disp-aal",
+ "mediatek,mt8183-disp-aal";
+ reg = <0 0x1400c000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_DISP_AAL0>;
+ interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
+ };
+
+ gamma: gamma@1400d000 {
+ compatible = "mediatek,mt8186-disp-gamma",
+ "mediatek,mt8183-disp-gamma";
+ reg = <0 0x1400d000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
+ interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
+ };
+
+ postmask: postmask@1400e000 {
+ compatible = "mediatek,mt8186-disp-postmask",
+ "mediatek,mt8192-disp-postmask";
+ reg = <0 0x1400e000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
+ interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
+ };
+
+ dither: dither@1400f000 {
+ compatible = "mediatek,mt8186-disp-dither",
+ "mediatek,mt8183-disp-dither";
+ reg = <0 0x1400f000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_DISP_DITHER0>;
+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
+ };
+
dsi0: dsi@14013000 {
compatible = "mediatek,mt8186-dsi";
reg = <0 0x14013000 0 0x1000>;
@@ -1334,6 +1448,17 @@
#iommu-cells = <1>;
};
+ rdma1: rdma@1401f000 {
+ compatible = "mediatek,mt8186-disp-rdma",
+ "mediatek,mt8183-disp-rdma";
+ reg = <0 0x1401f000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA1>;
+ interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&iommu_mm IOMMU_PORT_L1_DISP_RDMA1>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xf000 0x1000>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
+ };
+
wpesys: clock-controller@14020000 {
compatible = "mediatek,mt8186-wpesys";
reg = <0 0x14020000 0 0x1000>;
--
2.18.0
Add the Global Command Engine (GCE) node for MT8186 SoC
Signed-off-by: Allen-KH Cheng <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index f198fd8abc1d..b9d5af26771e 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -5,6 +5,7 @@
*/
/dts-v1/;
#include <dt-bindings/clock/mt8186-clk.h>
+#include <dt-bindings/gce/mt8186-gce.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/memory/mt8186-memory-port.h>
@@ -625,6 +626,15 @@
clocks = <&clk13m>;
};
+ gce: mailbox@1022c000 {
+ compatible = "mediatek,mt8186-gce";
+ reg = <0 0X1022c000 0 0x4000>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_GCE>;
+ clock-names = "gce";
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>;
+ #mbox-cells = <2>;
+ };
+
scp: scp@10500000 {
compatible = "mediatek,mt8186-scp";
reg = <0 0x10500000 0 0x40000>,
--
2.18.0
Il 03/03/23 04:17, Allen-KH Cheng ha scritto:
> Add MTU3 nodes for MT8186 SoC.
>
> Signed-off-by: Allen-KH Cheng <[email protected]>
> Tested-by: Chen-Yu Tsai <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Il 03/03/23 04:17, Allen-KH Cheng ha scritto:
> Add SPMI node for MT8186 SoC.
>
> Signed-off-by: Allen-KH Cheng <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Il 03/03/23 04:17, Allen-KH Cheng ha scritto:
> Add ADSP node for MT8186 SoC.
>
> Signed-off-by: Allen-KH Cheng <[email protected]>
> ---
> arch/arm64/boot/dts/mediatek/mt8186.dtsi | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> index 0e42bdbd2cb6..337bcf3c1571 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> @@ -633,6 +633,22 @@
> interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>;
> };
>
> + adsp: adsp@10680000 {
> + compatible = "mediatek,mt8186-dsp";
> + reg = <0 0x10680000 0 0x2000>, <0 0x10800000 0 0x100000>,
> + <0 0x1068b000 0 0x100>, <0 0x1068f000 0 0x1000>;
> + reg-names = "cfg", "sram", "sec", "bus";
> + clocks = <&topckgen CLK_TOP_AUDIODSP>, <&topckgen CLK_TOP_ADSP_BUS>;
Was missing <&topckgen CLK_TOP_AUDIO_H> intentional here?
AFAIK, that's required for the ADSP.
Regards,
Angelo
Il 03/03/23 04:17, Allen-KH Cheng ha scritto:
> Add the Global Command Engine (GCE) node for MT8186 SoC
>
> Signed-off-by: Allen-KH Cheng <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Il 03/03/23 04:17, Allen-KH Cheng ha scritto:
> Add display nodes and the GCE (Global Command Engine) properties
> to the display nodes in order to enable the usage of the CMDQ
> (Command Queue), which is required for operating the display.
>
> Signed-off-by: Allen-KH Cheng <[email protected]>
> ---
> arch/arm64/boot/dts/mediatek/mt8186.dtsi | 125 +++++++++++++++++++++++
> 1 file changed, 125 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> index b9d5af26771e..909f1a6ae108 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> @@ -20,6 +20,13 @@
> #address-cells = <2>;
> #size-cells = <2>;
>
> + aliases {
> + ovl = &ovl;
Are you sure that this alias shouldn't be `ovl0 = &ovl` instead?
> + ovl_2l= &ovl_2l;
And this `ovl_2l0 = &ovl_2l` ?
Everything else looks good.
Regards,
Angelo
Hi Angelo,
On Fri, 2023-03-03 at 12:35 +0100, AngeloGioacchino Del Regno wrote:
> Il 03/03/23 04:17, Allen-KH Cheng ha scritto:
> > Add display nodes and the GCE (Global Command Engine) properties
> > to the display nodes in order to enable the usage of the CMDQ
> > (Command Queue), which is required for operating the display.
> >
> > Signed-off-by: Allen-KH Cheng <[email protected]>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8186.dtsi | 125
> > +++++++++++++++++++++++
> > 1 file changed, 125 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> > index b9d5af26771e..909f1a6ae108 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> > @@ -20,6 +20,13 @@
> > #address-cells = <2>;
> > #size-cells = <2>;
> >
> > + aliases {
> > + ovl = &ovl;
>
> Are you sure that this alias shouldn't be `ovl0 = &ovl` instead?
>
> > + ovl_2l= &ovl_2l;
>
> And this `ovl_2l0 = &ovl_2l` ?
>
> Everything else looks good.
>
> Regards,
> Angelo
>
Hmm, I think there is a small error here.
I either put index in aliases or don't write aliases since the
number of ovl and ovl_2l is one.
I will add 0 and upstae in next version.
Thanks,
Allen
Note:
in mtk_ddp_comp_get_id:
int id = of_alias_get_id(node, mtk_ddp_comp_stem[comp_type]);
(id < 0 || id == mtk_ddp_matches[i].alias_id)) return i;
Hi Angelo,
On Fri, 2023-03-03 at 12:31 +0100, AngeloGioacchino Del Regno wrote:
> Il 03/03/23 04:17, Allen-KH Cheng ha scritto:
> > Add ADSP node for MT8186 SoC.
> >
> > Signed-off-by: Allen-KH Cheng <[email protected]>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8186.dtsi | 16 ++++++++++++++++
> > 1 file changed, 16 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> > index 0e42bdbd2cb6..337bcf3c1571 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> > @@ -633,6 +633,22 @@
> > interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > };
> >
> > + adsp: adsp@10680000 {
> > + compatible = "mediatek,mt8186-dsp";
> > + reg = <0 0x10680000 0 0x2000>, <0 0x10800000 0
> > 0x100000>,
> > + <0 0x1068b000 0 0x100>, <0 0x1068f000 0
> > 0x1000>;
> > + reg-names = "cfg", "sram", "sec", "bus";
> > + clocks = <&topckgen CLK_TOP_AUDIODSP>,
> > <&topckgen CLK_TOP_ADSP_BUS>;
>
> Was missing <&topckgen CLK_TOP_AUDIO_H> intentional here?
>
> AFAIK, that's required for the ADSP.
>
> Regards,
> Angelo
This may be dependent on the design of the chipset.
CLK_TOP_AUDIO_H will be used by the afe (audio-controller) node. This
is not used for DSP in the MT8186 architecture.
Thanks,
Allen