Hello,
This series adds support to configure the CPSW MAC's PHY in SGMII mode.
Also, SGMII mode is enabled for TI's J7200 and J721E SoCs.
Siddharth Vadapalli (3):
phy: ti: phy-gmii-sel: Add support for SGMII mode
phy: ti: gmii-sel: Enable SGMII mode for J7200
phy: ti: gmii-sel: Enable SGMII mode for J721E
drivers/phy/ti/phy-gmii-sel.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
--
2.25.1
TI's J7200 SoC supports SGMII mode with the CPSW5G instance of the CPSW
Ethernet Switch. Thus, enable it by adding SGMII mode to the list of the
corresponding extra_modes member.
Signed-off-by: Siddharth Vadapalli <[email protected]>
---
drivers/phy/ti/phy-gmii-sel.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c
index 351173aeb0a6..b0335a8abc18 100644
--- a/drivers/phy/ti/phy-gmii-sel.c
+++ b/drivers/phy/ti/phy-gmii-sel.c
@@ -219,7 +219,7 @@ static const
struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw5g_soc_j7200 = {
.use_of_data = true,
.regfields = phy_gmii_sel_fields_am654,
- .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII),
+ .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII),
.num_ports = 4,
.num_qsgmii_main_ports = 1,
};
--
2.25.1
Hello,
Please ignore this series. There are a few changes required. I will update and
post the v2 series.
Regards,
Siddharth.
On 09/03/23 11:52, Siddharth Vadapalli wrote:
> Hello,
>
> This series adds support to configure the CPSW MAC's PHY in SGMII mode.
> Also, SGMII mode is enabled for TI's J7200 and J721E SoCs.
>
> Siddharth Vadapalli (3):
> phy: ti: phy-gmii-sel: Add support for SGMII mode
> phy: ti: gmii-sel: Enable SGMII mode for J7200
> phy: ti: gmii-sel: Enable SGMII mode for J721E
>
> drivers/phy/ti/phy-gmii-sel.c | 10 ++++++++--
> 1 file changed, 8 insertions(+), 2 deletions(-)
>