Hello,
This series adds support to configure the CPSW MAC's PHY in SGMII mode.
Also, SGMII mode is enabled for TI's J7200 and J721E SoCs.
Changes from v1:
1. Add "break" statement within "case PHY_INTERFACE_MODE_SGMII".
2. Add newline before "default" case.
3. Update commit message of patch 1/3 to follow the existing convention.
v1:
https://lore.kernel.org/r/[email protected]/
Siddharth Vadapalli (3):
phy: ti: gmii-sel: Add support for SGMII mode
phy: ti: gmii-sel: Enable SGMII mode for J7200
phy: ti: gmii-sel: Enable SGMII mode for J721E
drivers/phy/ti/phy-gmii-sel.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
--
2.25.1
Add support to configure the CPSW MAC's PHY in SGMII mode if the SoC
supports it. The extra_modes member of the phy_gmii_sel_soc_data struct
corresponding to the SoC is used to determine whether or not the SoC
supports SGMII mode.
Signed-off-by: Siddharth Vadapalli <[email protected]>
---
drivers/phy/ti/phy-gmii-sel.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c
index 8c667819c39a..5e16d8dd5bee 100644
--- a/drivers/phy/ti/phy-gmii-sel.c
+++ b/drivers/phy/ti/phy-gmii-sel.c
@@ -23,6 +23,7 @@
#define AM33XX_GMII_SEL_MODE_RGMII 2
/* J72xx SoC specific definitions for the CONTROL port */
+#define J72XX_GMII_SEL_MODE_SGMII 3
#define J72XX_GMII_SEL_MODE_QSGMII 4
#define J72XX_GMII_SEL_MODE_QSGMII_SUB 6
@@ -106,6 +107,13 @@ static int phy_gmii_sel_mode(struct phy *phy, enum phy_mode mode, int submode)
gmii_sel_mode = J72XX_GMII_SEL_MODE_QSGMII_SUB;
break;
+ case PHY_INTERFACE_MODE_SGMII:
+ if (!(soc_data->extra_modes & BIT(PHY_INTERFACE_MODE_SGMII)))
+ goto unsupported;
+ else
+ gmii_sel_mode = J72XX_GMII_SEL_MODE_SGMII;
+ break;
+
default:
goto unsupported;
}
--
2.25.1
TI's J7200 SoC supports SGMII mode with the CPSW5G instance of the CPSW
Ethernet Switch. Thus, enable it by adding SGMII mode to the list of the
corresponding extra_modes member.
Signed-off-by: Siddharth Vadapalli <[email protected]>
---
drivers/phy/ti/phy-gmii-sel.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c
index 5e16d8dd5bee..f3da6b020247 100644
--- a/drivers/phy/ti/phy-gmii-sel.c
+++ b/drivers/phy/ti/phy-gmii-sel.c
@@ -221,7 +221,7 @@ static const
struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw5g_soc_j7200 = {
.use_of_data = true,
.regfields = phy_gmii_sel_fields_am654,
- .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII),
+ .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII),
.num_ports = 4,
.num_qsgmii_main_ports = 1,
};
--
2.25.1
TI's J721E SoC supports SGMII mode with the CPSW9G instance of the CPSW
Ethernet Switch. Thus, enable it by adding SGMII mode to the list of the
corresponding extra_modes member.
Signed-off-by: Siddharth Vadapalli <[email protected]>
---
drivers/phy/ti/phy-gmii-sel.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c
index f3da6b020247..c87118cb2af9 100644
--- a/drivers/phy/ti/phy-gmii-sel.c
+++ b/drivers/phy/ti/phy-gmii-sel.c
@@ -230,7 +230,7 @@ static const
struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j721e = {
.use_of_data = true,
.regfields = phy_gmii_sel_fields_am654,
- .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII),
+ .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII),
.num_ports = 8,
.num_qsgmii_main_ports = 2,
};
--
2.25.1
Hello,
This series applies cleanly as of next-20230404. Please merge this series
followed by the series at:
https://lore.kernel.org/r/[email protected]/
in case of no concerns.
Regards,
Siddharth.
On 09/03/23 12:05, Siddharth Vadapalli wrote:
> Hello,
>
> This series adds support to configure the CPSW MAC's PHY in SGMII mode.
> Also, SGMII mode is enabled for TI's J7200 and J721E SoCs.
>
> Changes from v1:
> 1. Add "break" statement within "case PHY_INTERFACE_MODE_SGMII".
> 2. Add newline before "default" case.
> 3. Update commit message of patch 1/3 to follow the existing convention.
>
> v1:
> https://lore.kernel.org/r/[email protected]/
>
> Siddharth Vadapalli (3):
> phy: ti: gmii-sel: Add support for SGMII mode
> phy: ti: gmii-sel: Enable SGMII mode for J7200
> phy: ti: gmii-sel: Enable SGMII mode for J721E
>
> drivers/phy/ti/phy-gmii-sel.c | 12 ++++++++++--
> 1 file changed, 10 insertions(+), 2 deletions(-)
>
On 09/03/2023 08:35, Siddharth Vadapalli wrote:
> Hello,
>
> This series adds support to configure the CPSW MAC's PHY in SGMII mode.
> Also, SGMII mode is enabled for TI's J7200 and J721E SoCs.
>
> Changes from v1:
> 1. Add "break" statement within "case PHY_INTERFACE_MODE_SGMII".
> 2. Add newline before "default" case.
> 3. Update commit message of patch 1/3 to follow the existing convention.
>
> v1:
> https://lore.kernel.org/r/[email protected]/
>
> Siddharth Vadapalli (3):
> phy: ti: gmii-sel: Add support for SGMII mode
> phy: ti: gmii-sel: Enable SGMII mode for J7200
> phy: ti: gmii-sel: Enable SGMII mode for J721E
>
> drivers/phy/ti/phy-gmii-sel.c | 12 ++++++++++--
> 1 file changed, 10 insertions(+), 2 deletions(-)
>
For the series:
Reviewed-by: Roger Quadros <[email protected]>
On 09-03-23, 12:05, Siddharth Vadapalli wrote:
> Hello,
>
> This series adds support to configure the CPSW MAC's PHY in SGMII mode.
> Also, SGMII mode is enabled for TI's J7200 and J721E SoCs.
Applied, thanks
--
~Vinod