This series introduces support for A690 in the DRM/MSM driver and
enables it for the two SC8280XP laptops.
Bjorn Andersson (3):
drm/msm/adreno: Add Adreno A690 support
arm64: dts: qcom: sc8280xp: Add GPU related nodes
arm64: dts: qcom: sc8280xp: Enable GPU related nodes
arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 26 +++
.../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 26 +++
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 171 ++++++++++++++++++
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 120 +++++++++++-
drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 34 ++++
drivers/gpu/drm/msm/adreno/adreno_device.c | 14 ++
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 10 +-
7 files changed, 396 insertions(+), 5 deletions(-)
--
2.39.1
From: Bjorn Andersson <[email protected]>
Add Adreno SMMU, GPU clock controller, GMU and GPU nodes for the
SC8280XP.
Signed-off-by: Bjorn Andersson <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
---
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 171 +++++++++++++++++++++++++
1 file changed, 171 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index fcd393444f47..94e8d0da9d7b 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
+#include <dt-bindings/clock/qcom,gpucc-sc8280xp.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sc8280xp.h>
@@ -2275,6 +2276,176 @@ tcsr: syscon@1fc0000 {
reg = <0x0 0x01fc0000 0x0 0x30000>;
};
+ gpu: gpu@3d00000 {
+ compatible = "qcom,adreno-690.0", "qcom,adreno";
+ reg = <0 0x03d00000 0 0x40000>,
+ <0 0x03d9e000 0 0x1000>,
+ <0 0x03d61000 0 0x800>;
+ reg-names = "kgsl_3d0_reg_memory",
+ "cx_mem",
+ "cx_dbgc";
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&adreno_smmu 0 0xc00>, <&adreno_smmu 1 0xc00>;
+ operating-points-v2 = <&gpu_opp_table>;
+ qcom,gmu = <&gmu>;
+ interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "gfx-mem";
+ #cooling-cells = <2>;
+
+ status = "disabled";
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ opp-peak-kBps = <451000>;
+ };
+
+ opp-410000000 {
+ opp-hz = /bits/ 64 <410000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ opp-peak-kBps = <1555000>;
+ };
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ opp-peak-kBps = <1555000>;
+ };
+
+ opp-547000000 {
+ opp-hz = /bits/ 64 <547000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+ opp-peak-kBps = <1555000>;
+ };
+
+ opp-606000000 {
+ opp-hz = /bits/ 64 <606000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ opp-peak-kBps = <2736000>;
+ };
+
+ opp-640000000 {
+ opp-hz = /bits/ 64 <640000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ opp-peak-kBps = <2736000>;
+ };
+
+ opp-690000000 {
+ opp-hz = /bits/ 64 <690000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+ opp-peak-kBps = <2736000>;
+ };
+ };
+ };
+
+ gmu: gmu@3d6a000 {
+ compatible="qcom,adreno-gmu-690.0", "qcom,adreno-gmu";
+ reg = <0 0x03d6a000 0 0x34000>,
+ <0 0x03de0000 0 0x10000>,
+ <0 0x0b290000 0 0x10000>,
+ <0 0x0b490000 0 0x10000>;
+ reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
+ interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hfi", "gmu";
+ clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_CXO_CLK>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gpucc GPU_CC_AHB_CLK>,
+ <&gpucc GPU_CC_HUB_CX_INT_CLK>,
+ <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
+ <&aoss_qmp>;
+ clock-names = "gmu",
+ "cxo",
+ "axi",
+ "memnoc",
+ "ahb",
+ "hub",
+ "smmu_vote",
+ "apb_pclk";
+ power-domains = <&gpucc GPU_CC_CX_GDSC>,
+ <&gpucc GPU_CC_GX_GDSC>;
+ power-domain-names = "cx",
+ "gx";
+ iommus = <&adreno_smmu 5 0xc00>;
+ operating-points-v2 = <&gmu_opp_table>;
+
+ status = "disabled";
+
+ gmu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+ };
+ };
+ };
+
+ gpucc: clock-controller@3d90000 {
+ compatible = "qcom,sc8280xp-gpucc";
+ reg = <0 0x03d90000 0 0x9000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+ <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+ clock-names = "bi_tcxo",
+ "gcc_gpu_gpll0_clk_src",
+ "gcc_gpu_gpll0_div_clk_src";
+
+ power-domains = <&rpmhpd SC8280XP_GFX>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+
+ status = "disabled";
+ };
+
+ adreno_smmu: iommu@3da0000 {
+ compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu", "arm,mmu-500";
+ reg = <0 0x03da0000 0 0x20000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <2>;
+ interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
+ <&gpucc GPU_CC_AHB_CLK>,
+ <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
+ <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_HUB_CX_INT_CLK>,
+ <&gpucc GPU_CC_HUB_AON_CLK>,
+ <&aoss_qmp>;
+ clock-names = "gcc_gpu_memnoc_gfx_clk",
+ "gcc_gpu_snoc_dvm_gfx_clk",
+ "gpu_cc_ahb_clk",
+ "gpu_cc_hlos1_vote_gpu_smmu_clk",
+ "gpu_cc_cx_gmu_clk",
+ "gpu_cc_hub_cx_int_clk",
+ "gpu_cc_hub_aon_clk",
+ "apb_pclk";
+
+ power-domains = <&gpucc GPU_CC_CX_GDSC>;
+
+ status = "disabled";
+ };
+
usb_0_hsphy: phy@88e5000 {
compatible = "qcom,sc8280xp-usb-hs-phy",
"qcom,usb-snps-hs-5nm-phy";
--
2.39.1
From: Bjorn Andersson <[email protected]>
Introduce support for the Adreno A690, found in Qualcomm SC8280XP.
Signed-off-by: Bjorn Andersson <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 120 ++++++++++++++++++++-
drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 34 ++++++
drivers/gpu/drm/msm/adreno/adreno_device.c | 14 +++
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 10 +-
4 files changed, 173 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index aae60cbd9164..81dfcc5073ad 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -588,6 +588,63 @@ const struct adreno_reglist a660_hwcg[] = {
{},
};
+const struct adreno_reglist a690_hwcg[] = {
+ {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
+ {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
+ {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
+ {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
+ {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
+ {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
+ {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
+ {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
+ {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
+ {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
+ {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
+ {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
+ {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
+ {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
+ {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
+ {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
+ {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
+ {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
+ {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
+ {REG_A6XX_RBBM_CLOCK_CNTL, 0x8AA8AA82},
+ {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
+ {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
+ {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
+ {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
+ {REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, 0x20200},
+ {REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, 0x10111},
+ {REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, 0x5555},
+ {}
+};
+
static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
{
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
@@ -747,6 +804,45 @@ static const u32 a660_protect[] = {
A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */
};
+/* These are for a690 */
+static const u32 a690_protect[] = {
+ A6XX_PROTECT_RDONLY(0x00000, 0x004ff),
+ A6XX_PROTECT_RDONLY(0x00501, 0x00001),
+ A6XX_PROTECT_RDONLY(0x0050b, 0x002f4),
+ A6XX_PROTECT_NORDWR(0x0050e, 0x00000),
+ A6XX_PROTECT_NORDWR(0x00510, 0x00000),
+ A6XX_PROTECT_NORDWR(0x00534, 0x00000),
+ A6XX_PROTECT_NORDWR(0x00800, 0x00082),
+ A6XX_PROTECT_NORDWR(0x008a0, 0x00008),
+ A6XX_PROTECT_NORDWR(0x008ab, 0x00024),
+ A6XX_PROTECT_RDONLY(0x008d0, 0x000bc),
+ A6XX_PROTECT_NORDWR(0x00900, 0x0004d),
+ A6XX_PROTECT_NORDWR(0x0098d, 0x00272),
+ A6XX_PROTECT_NORDWR(0x00e00, 0x00001),
+ A6XX_PROTECT_NORDWR(0x00e03, 0x0000c),
+ A6XX_PROTECT_NORDWR(0x03c00, 0x000c3),
+ A6XX_PROTECT_RDONLY(0x03cc4, 0x01fff),
+ A6XX_PROTECT_NORDWR(0x08630, 0x001cf),
+ A6XX_PROTECT_NORDWR(0x08e00, 0x00000),
+ A6XX_PROTECT_NORDWR(0x08e08, 0x00008),
+ A6XX_PROTECT_NORDWR(0x08e50, 0x0001f),
+ A6XX_PROTECT_NORDWR(0x08e80, 0x0027f),
+ A6XX_PROTECT_NORDWR(0x09624, 0x001db),
+ A6XX_PROTECT_NORDWR(0x09e60, 0x00011),
+ A6XX_PROTECT_NORDWR(0x09e78, 0x00187),
+ A6XX_PROTECT_NORDWR(0x0a630, 0x001cf),
+ A6XX_PROTECT_NORDWR(0x0ae02, 0x00000),
+ A6XX_PROTECT_NORDWR(0x0ae50, 0x0012f),
+ A6XX_PROTECT_NORDWR(0x0b604, 0x00000),
+ A6XX_PROTECT_NORDWR(0x0b608, 0x00006),
+ A6XX_PROTECT_NORDWR(0x0be02, 0x00001),
+ A6XX_PROTECT_NORDWR(0x0be20, 0x0015f),
+ A6XX_PROTECT_NORDWR(0x0d000, 0x005ff),
+ A6XX_PROTECT_NORDWR(0x0f000, 0x00bff),
+ A6XX_PROTECT_RDONLY(0x0fc00, 0x01fff),
+ A6XX_PROTECT_NORDWR(0x11c00, 0x00000), /*note: infiite range */
+};
+
static void a6xx_set_cp_protect(struct msm_gpu *gpu)
{
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
@@ -758,6 +854,11 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu)
count = ARRAY_SIZE(a650_protect);
count_max = 48;
BUILD_BUG_ON(ARRAY_SIZE(a650_protect) > 48);
+ } else if (adreno_is_a690(adreno_gpu)) {
+ regs = a690_protect;
+ count = ARRAY_SIZE(a690_protect);
+ count_max = 48;
+ BUILD_BUG_ON(ARRAY_SIZE(a690_protect) > 48);
} else if (adreno_is_a660_family(adreno_gpu)) {
regs = a660_protect;
count = ARRAY_SIZE(a660_protect);
@@ -806,6 +907,13 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
uavflagprd_inv = 2;
}
+ if (adreno_is_a690(adreno_gpu)) {
+ lower_bit = 2;
+ amsbc = 1;
+ rgb565_predicator = 1;
+ uavflagprd_inv = 2;
+ }
+
if (adreno_is_7c3(adreno_gpu)) {
lower_bit = 1;
amsbc = 1;
@@ -1065,13 +1173,18 @@ static int hw_init(struct msm_gpu *gpu)
if (adreno_is_a660_family(adreno_gpu))
gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020);
+ if (adreno_is_a690(adreno_gpu)) {
+ gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x0);
+ gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020);
+ }
+
/* Setting the mem pool size */
gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128);
/* Setting the primFifo thresholds default values,
* and vccCacheSkipDis=1 bit (0x200) for A640 and newer
*/
- if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu))
+ if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu) || adreno_is_a690(adreno_gpu))
gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200);
else if (adreno_is_a640_family(adreno_gpu) || adreno_is_7c3(adreno_gpu))
gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200);
@@ -1579,7 +1692,7 @@ static void a6xx_llc_activate(struct a6xx_gpu *a6xx_gpu)
/* On A660, the SCID programming for UCHE traffic is done in
* A6XX_GBIF_SCACHE_CNTL0[14:10]
*/
- if (adreno_is_a660_family(adreno_gpu))
+ if (adreno_is_a660_family(adreno_gpu) || adreno_is_a690(adreno_gpu))
gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL0, (0x1f << 10) |
(1 << 8), (gpu_scid << 10) | (1 << 8));
}
@@ -2006,7 +2119,8 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
info = adreno_info(config->rev);
if (info && (info->revn == 650 || info->revn == 660 ||
- adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), info->rev)))
+ info->revn == 690 ||
+ adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), info->rev)))
adreno_gpu->base.hw_apriv = true;
a6xx_llc_slices_init(pdev, a6xx_gpu);
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
index 2cc83e049613..4d6d68a25931 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
@@ -4,6 +4,7 @@
#include <linux/completion.h>
#include <linux/circ_buf.h>
#include <linux/list.h>
+#include <soc/qcom/cmd-db.h>
#include "a6xx_gmu.h"
#include "a6xx_gmu.xml.h"
@@ -414,6 +415,37 @@ static void a650_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
msg->cnoc_cmds_data[1][0] = 0x60000001;
}
+static void a690_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
+{
+ /*
+ * Send a single "off" entry just to get things running
+ * TODO: bus scaling
+ */
+ msg->bw_level_num = 1;
+
+ msg->ddr_cmds_num = 3;
+ msg->ddr_wait_bitmask = 0x01;
+
+ msg->ddr_cmds_addrs[0] = cmd_db_read_addr("SH0");
+ msg->ddr_cmds_addrs[1] = cmd_db_read_addr("MC0");
+ msg->ddr_cmds_addrs[2] = cmd_db_read_addr("ACV");
+
+ msg->ddr_cmds_data[0][0] = 0x40000000;
+ msg->ddr_cmds_data[0][1] = 0x40000000;
+ msg->ddr_cmds_data[0][2] = 0x40000000;
+
+ /*
+ * These are the CX (CNOC) votes - these are used by the GMU but the
+ * votes are known and fixed for the target
+ */
+ msg->cnoc_cmds_num = 1;
+ msg->cnoc_wait_bitmask = 0x01;
+
+ msg->cnoc_cmds_addrs[0] = cmd_db_read_addr("CN0");
+ msg->cnoc_cmds_data[0][0] = 0x40000000;
+ msg->cnoc_cmds_data[1][0] = 0x60000001;
+}
+
static void a660_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
{
/*
@@ -531,6 +563,8 @@ static int a6xx_hfi_send_bw_table(struct a6xx_gmu *gmu)
adreno_7c3_build_bw_table(&msg);
else if (adreno_is_a660(adreno_gpu))
a660_build_bw_table(&msg);
+ else if (adreno_is_a690(adreno_gpu))
+ a690_build_bw_table(&msg);
else
a6xx_build_bw_table(&msg);
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
index ca38b837dedb..437515e46e5a 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -355,6 +355,20 @@ static const struct adreno_info gpulist[] = {
.init = a6xx_gpu_init,
.zapfw = "a640_zap.mdt",
.hwcg = a640_hwcg,
+ }, {
+ .rev = ADRENO_REV(6, 9, 0, ANY_ID),
+ .revn = 690,
+ .name = "A690",
+ .fw = {
+ [ADRENO_FW_SQE] = "a660_sqe.fw",
+ [ADRENO_FW_GMU] = "a690_gmu.bin",
+ },
+ .gmem = SZ_4M,
+ .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .init = a6xx_gpu_init,
+ .zapfw = "a690_zap.mdt",
+ .hwcg = a690_hwcg,
+ .address_space_size = SZ_16G,
},
};
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index b4f9b1343d63..da29bd392388 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -55,7 +55,7 @@ struct adreno_reglist {
u32 value;
};
-extern const struct adreno_reglist a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[], a660_hwcg[];
+extern const struct adreno_reglist a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[], a660_hwcg[], a690_hwcg[];
struct adreno_info {
struct adreno_rev rev;
@@ -272,6 +272,11 @@ static inline int adreno_is_a660(struct adreno_gpu *gpu)
return gpu->revn == 660;
}
+static inline int adreno_is_a690(struct adreno_gpu *gpu)
+{
+ return gpu->revn == 690;
+};
+
/* check for a615, a616, a618, a619 or any derivatives */
static inline int adreno_is_a615_family(struct adreno_gpu *gpu)
{
@@ -286,7 +291,8 @@ static inline int adreno_is_a660_family(struct adreno_gpu *gpu)
/* check for a650, a660, or any derivatives */
static inline int adreno_is_a650_family(struct adreno_gpu *gpu)
{
- return gpu->revn == 650 || gpu->revn == 620 || adreno_is_a660_family(gpu);
+ return gpu->revn == 650 || gpu->revn == 620 || gpu->revn == 690 ||
+ adreno_is_a660_family(gpu);
}
u64 adreno_private_address_space_size(struct msm_gpu *gpu);
--
2.39.1
From: Bjorn Andersson <[email protected]>
Add memory reservation for the zap-shader and enable the Adreno SMMU,
GPU clock controller, GMU and the GPU nodes for the SC8280XP CRD and the
Lenovo ThinkPad X13s.
Signed-off-by: Bjorn Andersson <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
---
arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 26 +++++++++++++++++++
.../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 26 +++++++++++++++++++
2 files changed, 52 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
index 35b63c3962f0..1d1ad43040ac 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
@@ -203,6 +203,11 @@ vreg_wwan: regulator-wwan {
};
reserved-memory {
+ gpu_mem: gpu-mem@8bf00000 {
+ reg = <0 0x8bf00000 0 0x2000>;
+ no-map;
+ };
+
linux,cma {
compatible = "shared-dma-pool";
size = <0x0 0x8000000>;
@@ -252,6 +257,10 @@ usb1_sbu_mux: endpoint {
};
};
+&adreno_smmu {
+ status = "okay";
+};
+
&apps_rsc {
pmc8280-1-rpmh-regulators {
compatible = "qcom,pm8350-rpmh-regulators";
@@ -369,6 +378,23 @@ &dispcc0 {
status = "okay";
};
+&gmu {
+ status = "okay";
+};
+
+&gpu {
+ status = "okay";
+
+ zap-shader {
+ memory-region = <&gpu_mem>;
+ firmware-name = "qcom/sc8280xp/qcdxkmsuc8280.mbn";
+ };
+};
+
+&gpucc {
+ status = "okay";
+};
+
&mdss0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
index 4ef15edd6c0f..7967e951a8ee 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
@@ -256,6 +256,11 @@ vreg_wwan: regulator-wwan {
};
reserved-memory {
+ gpu_mem: gpu-mem@8bf00000 {
+ reg = <0 0x8bf00000 0 0x2000>;
+ no-map;
+ };
+
linux,cma {
compatible = "shared-dma-pool";
size = <0x0 0x8000000>;
@@ -351,6 +356,10 @@ usb1_sbu_mux: endpoint {
};
};
+&adreno_smmu {
+ status = "okay";
+};
+
&apps_rsc {
pmc8280-1-rpmh-regulators {
compatible = "qcom,pm8350-rpmh-regulators";
@@ -484,6 +493,23 @@ &dispcc0 {
status = "okay";
};
+&gmu {
+ status = "okay";
+};
+
+&gpu {
+ status = "okay";
+
+ zap-shader {
+ memory-region = <&gpu_mem>;
+ firmware-name = "qcom/sc8280xp/LENOVO/21BX/qcdxkmsuc8280.mbn";
+ };
+};
+
+&gpucc {
+ status = "okay";
+};
+
&mdss0 {
status = "okay";
};
--
2.39.1
On 8.02.2023 04:40, Bjorn Andersson wrote:
> From: Bjorn Andersson <[email protected]>
>
> Add Adreno SMMU, GPU clock controller, GMU and GPU nodes for the
> SC8280XP.
>
> Signed-off-by: Bjorn Andersson <[email protected]>
> Signed-off-by: Bjorn Andersson <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 171 +++++++++++++++++++++++++
> 1 file changed, 171 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index fcd393444f47..94e8d0da9d7b 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -6,6 +6,7 @@
>
> #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
> #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
> +#include <dt-bindings/clock/qcom,gpucc-sc8280xp.h>
> #include <dt-bindings/clock/qcom,rpmh.h>
> #include <dt-bindings/interconnect/qcom,osm-l3.h>
> #include <dt-bindings/interconnect/qcom,sc8280xp.h>
> @@ -2275,6 +2276,176 @@ tcsr: syscon@1fc0000 {
> reg = <0x0 0x01fc0000 0x0 0x30000>;
> };
>
> + gpu: gpu@3d00000 {
> + compatible = "qcom,adreno-690.0", "qcom,adreno";
Did Qualcomm really pull off a chip this big with
patchlevel=0/first try? Nice.
> + reg = <0 0x03d00000 0 0x40000>,
> + <0 0x03d9e000 0 0x1000>,
> + <0 0x03d61000 0 0x800>;
> + reg-names = "kgsl_3d0_reg_memory",
> + "cx_mem",
> + "cx_dbgc";
> + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
> + iommus = <&adreno_smmu 0 0xc00>, <&adreno_smmu 1 0xc00>;
> + operating-points-v2 = <&gpu_opp_table>;
> + qcom,gmu = <&gmu>;
> + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "gfx-mem";
> + #cooling-cells = <2>;
> +
> + status = "disabled";
> +
> + gpu_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-270000000 {
> + opp-hz = /bits/ 64 <270000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> + opp-peak-kBps = <451000>;
> + };
> +
> + opp-410000000 {
> + opp-hz = /bits/ 64 <410000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
> + opp-peak-kBps = <1555000>;
> + };
> +
> + opp-500000000 {
> + opp-hz = /bits/ 64 <500000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> + opp-peak-kBps = <1555000>;
> + };
> +
> + opp-547000000 {
> + opp-hz = /bits/ 64 <547000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
> + opp-peak-kBps = <1555000>;
> + };
> +
> + opp-606000000 {
> + opp-hz = /bits/ 64 <606000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
> + opp-peak-kBps = <2736000>;
> + };
> +
> + opp-640000000 {
> + opp-hz = /bits/ 64 <640000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
> + opp-peak-kBps = <2736000>;
> + };
> +
> + opp-690000000 {
> + opp-hz = /bits/ 64 <690000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
> + opp-peak-kBps = <2736000>;
> + };
> + };
> + };
> +
> + gmu: gmu@3d6a000 {
> + compatible="qcom,adreno-gmu-690.0", "qcom,adreno-gmu";
This needs a binding update.
> + reg = <0 0x03d6a000 0 0x34000>,
> + <0 0x03de0000 0 0x10000>,
> + <0 0x0b290000 0 0x10000>,
> + <0 0x0b490000 0 0x10000>;
> + reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
I think this should be a vertical list with so many entries.
> + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hfi", "gmu";
> + clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
> + <&gpucc GPU_CC_CXO_CLK>,
> + <&gcc GCC_DDRSS_GPU_AXI_CLK>,
> + <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
> + <&gpucc GPU_CC_AHB_CLK>,
> + <&gpucc GPU_CC_HUB_CX_INT_CLK>,
> + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
> + <&aoss_qmp>;
> + clock-names = "gmu",
> + "cxo",
> + "axi",
> + "memnoc",
> + "ahb",
> + "hub",
> + "smmu_vote",
> + "apb_pclk";
> + power-domains = <&gpucc GPU_CC_CX_GDSC>,
> + <&gpucc GPU_CC_GX_GDSC>;
> + power-domain-names = "cx",
> + "gx";
> + iommus = <&adreno_smmu 5 0xc00>;
> + operating-points-v2 = <&gmu_opp_table>;
> +
> + status = "disabled";
> +
> + gmu_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-200000000 {
> + opp-hz = /bits/ 64 <200000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
> + };
> + };
> + };
> +
> + gpucc: clock-controller@3d90000 {
> + compatible = "qcom,sc8280xp-gpucc";
> + reg = <0 0x03d90000 0 0x9000>;
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_GPU_GPLL0_CLK_SRC>,
> + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
> + clock-names = "bi_tcxo",
> + "gcc_gpu_gpll0_clk_src",
> + "gcc_gpu_gpll0_div_clk_src";
> +
> + power-domains = <&rpmhpd SC8280XP_GFX>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> +
> + status = "disabled";
Is there any benefit in not enabling this by default?
> + };
> +
> + adreno_smmu: iommu@3da0000 {
> + compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu", "arm,mmu-500";
This needs a binding update.
> + reg = <0 0x03da0000 0 0x20000>;
> + #iommu-cells = <2>;
> + #global-interrupts = <2>;
> + interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>;
> +
> + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
> + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
> + <&gpucc GPU_CC_AHB_CLK>,
> + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
> + <&gpucc GPU_CC_CX_GMU_CLK>,
> + <&gpucc GPU_CC_HUB_CX_INT_CLK>,
> + <&gpucc GPU_CC_HUB_AON_CLK>,
> + <&aoss_qmp>;
> + clock-names = "gcc_gpu_memnoc_gfx_clk",
> + "gcc_gpu_snoc_dvm_gfx_clk",
> + "gpu_cc_ahb_clk",
> + "gpu_cc_hlos1_vote_gpu_smmu_clk",
> + "gpu_cc_cx_gmu_clk",
> + "gpu_cc_hub_cx_int_clk",
> + "gpu_cc_hub_aon_clk",
> + "apb_pclk";
You'll need to update the smmu bindings; I think this may
be overkill for the SMMU.. usually you need 3-4 clks at
max (snoc_dvm, memnoc, vote_smmu and some other thing).
> +
> + power-domains = <&gpucc GPU_CC_CX_GDSC>;
> +
> + status = "disabled";
Not sure if there's any benefit in disabling this.
Konrad
> + };
> +
> usb_0_hsphy: phy@88e5000 {
> compatible = "qcom,sc8280xp-usb-hs-phy",
> "qcom,usb-snps-hs-5nm-phy";
On 08/02/2023 05:40, Bjorn Andersson wrote:
> From: Bjorn Andersson <[email protected]>
>
> Introduce support for the Adreno A690, found in Qualcomm SC8280XP.
>
> Signed-off-by: Bjorn Andersson <[email protected]>
> Signed-off-by: Bjorn Andersson <[email protected]>
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 120 ++++++++++++++++++++-
> drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 34 ++++++
> drivers/gpu/drm/msm/adreno/adreno_device.c | 14 +++
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 10 +-
> 4 files changed, 173 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index aae60cbd9164..81dfcc5073ad 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -588,6 +588,63 @@ const struct adreno_reglist a660_hwcg[] = {
> {},
> };
>
> +const struct adreno_reglist a690_hwcg[] = {
> + {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
> + {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
> + {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
> + {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
> + {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
> + {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
> + {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
> + {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
> + {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
> + {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
> + {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
> + {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
> + {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
> + {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
> + {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
> + {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
> + {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
> + {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
> + {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
> + {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
> + {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
> + {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
> + {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
> + {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
> + {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
> + {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
> + {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
> + {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
> + {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
> + {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
> + {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
> + {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
> + {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
> + {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
> + {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
> + {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
> + {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
> + {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
> + {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
> + {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
> + {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
> + {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
> + {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
> + {REG_A6XX_RBBM_CLOCK_CNTL, 0x8AA8AA82},
> + {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
> + {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
> + {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
> + {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
> + {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
> + {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
> + {REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, 0x20200},
> + {REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, 0x10111},
> + {REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, 0x5555},
> + {}
> +};
> +
> static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
> {
> struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
> @@ -747,6 +804,45 @@ static const u32 a660_protect[] = {
> A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */
> };
>
> +/* These are for a690 */
> +static const u32 a690_protect[] = {
> + A6XX_PROTECT_RDONLY(0x00000, 0x004ff),
> + A6XX_PROTECT_RDONLY(0x00501, 0x00001),
Judging from msm-5.4 this should be , 0x0005
> + A6XX_PROTECT_RDONLY(0x0050b, 0x002f4),
> + A6XX_PROTECT_NORDWR(0x0050e, 0x00000),
> + A6XX_PROTECT_NORDWR(0x00510, 0x00000),
> + A6XX_PROTECT_NORDWR(0x00534, 0x00000),
> + A6XX_PROTECT_NORDWR(0x00800, 0x00082),
> + A6XX_PROTECT_NORDWR(0x008a0, 0x00008),
> + A6XX_PROTECT_NORDWR(0x008ab, 0x00024),
> + A6XX_PROTECT_RDONLY(0x008d0, 0x000bc),
> + A6XX_PROTECT_NORDWR(0x00900, 0x0004d),
> + A6XX_PROTECT_NORDWR(0x0098d, 0x00272),
> + A6XX_PROTECT_NORDWR(0x00e00, 0x00001),
> + A6XX_PROTECT_NORDWR(0x00e03, 0x0000c),
> + A6XX_PROTECT_NORDWR(0x03c00, 0x000c3),
> + A6XX_PROTECT_RDONLY(0x03cc4, 0x01fff),
> + A6XX_PROTECT_NORDWR(0x08630, 0x001cf),
> + A6XX_PROTECT_NORDWR(0x08e00, 0x00000),
> + A6XX_PROTECT_NORDWR(0x08e08, 0x00008),
> + A6XX_PROTECT_NORDWR(0x08e50, 0x0001f),
> + A6XX_PROTECT_NORDWR(0x08e80, 0x0027f),
> + A6XX_PROTECT_NORDWR(0x09624, 0x001db),
> + A6XX_PROTECT_NORDWR(0x09e60, 0x00011),
> + A6XX_PROTECT_NORDWR(0x09e78, 0x00187),
> + A6XX_PROTECT_NORDWR(0x0a630, 0x001cf),
> + A6XX_PROTECT_NORDWR(0x0ae02, 0x00000),
> + A6XX_PROTECT_NORDWR(0x0ae50, 0x0012f),
> + A6XX_PROTECT_NORDWR(0x0b604, 0x00000),
> + A6XX_PROTECT_NORDWR(0x0b608, 0x00006),
> + A6XX_PROTECT_NORDWR(0x0be02, 0x00001),
> + A6XX_PROTECT_NORDWR(0x0be20, 0x0015f),
> + A6XX_PROTECT_NORDWR(0x0d000, 0x005ff),
> + A6XX_PROTECT_NORDWR(0x0f000, 0x00bff),
> + A6XX_PROTECT_RDONLY(0x0fc00, 0x01fff),
> + A6XX_PROTECT_NORDWR(0x11c00, 0x00000), /*note: infiite range */
> +};
> +
> static void a6xx_set_cp_protect(struct msm_gpu *gpu)
> {
> struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
> @@ -758,6 +854,11 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu)
> count = ARRAY_SIZE(a650_protect);
> count_max = 48;
> BUILD_BUG_ON(ARRAY_SIZE(a650_protect) > 48);
> + } else if (adreno_is_a690(adreno_gpu)) {
> + regs = a690_protect;
> + count = ARRAY_SIZE(a690_protect);
> + count_max = 48;
> + BUILD_BUG_ON(ARRAY_SIZE(a690_protect) > 48);
> } else if (adreno_is_a660_family(adreno_gpu)) {
> regs = a660_protect;
> count = ARRAY_SIZE(a660_protect);
> @@ -806,6 +907,13 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
> uavflagprd_inv = 2;
> }
>
> + if (adreno_is_a690(adreno_gpu)) {
> + lower_bit = 2;
> + amsbc = 1;
> + rgb565_predicator = 1;
> + uavflagprd_inv = 2;
> + }
> +
> if (adreno_is_7c3(adreno_gpu)) {
> lower_bit = 1;
> amsbc = 1;
> @@ -1065,13 +1173,18 @@ static int hw_init(struct msm_gpu *gpu)
> if (adreno_is_a660_family(adreno_gpu))
> gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020);
>
> + if (adreno_is_a690(adreno_gpu)) {
> + gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x0);
I might sound like a purist here, but a660 has this down, after setting
cp_protect
> + gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020);
> + }
> +
> /* Setting the mem pool size */
> gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128);
>
> /* Setting the primFifo thresholds default values,
> * and vccCacheSkipDis=1 bit (0x200) for A640 and newer
> */
> - if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu))
> + if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu) || adreno_is_a690(adreno_gpu))
> gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200);
> else if (adreno_is_a640_family(adreno_gpu) || adreno_is_7c3(adreno_gpu))
> gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200);
> @@ -1579,7 +1692,7 @@ static void a6xx_llc_activate(struct a6xx_gpu *a6xx_gpu)
> /* On A660, the SCID programming for UCHE traffic is done in
> * A6XX_GBIF_SCACHE_CNTL0[14:10]
> */
> - if (adreno_is_a660_family(adreno_gpu))
> + if (adreno_is_a660_family(adreno_gpu) || adreno_is_a690(adreno_gpu))
> gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL0, (0x1f << 10) |
> (1 << 8), (gpu_scid << 10) | (1 << 8));
> }
> @@ -2006,7 +2119,8 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
> info = adreno_info(config->rev);
>
> if (info && (info->revn == 650 || info->revn == 660 ||
> - adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), info->rev)))
> + info->revn == 690 ||
> + adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), info->rev)))
> adreno_gpu->base.hw_apriv = true;
>
> a6xx_llc_slices_init(pdev, a6xx_gpu);
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
> index 2cc83e049613..4d6d68a25931 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
> @@ -4,6 +4,7 @@
> #include <linux/completion.h>
> #include <linux/circ_buf.h>
> #include <linux/list.h>
> +#include <soc/qcom/cmd-db.h>
>
> #include "a6xx_gmu.h"
> #include "a6xx_gmu.xml.h"
> @@ -414,6 +415,37 @@ static void a650_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
> msg->cnoc_cmds_data[1][0] = 0x60000001;
> }
>
> +static void a690_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
> +{
> + /*
> + * Send a single "off" entry just to get things running
> + * TODO: bus scaling
> + */
> + msg->bw_level_num = 1;
> +
> + msg->ddr_cmds_num = 3;
> + msg->ddr_wait_bitmask = 0x01;
> +
> + msg->ddr_cmds_addrs[0] = cmd_db_read_addr("SH0");
> + msg->ddr_cmds_addrs[1] = cmd_db_read_addr("MC0");
> + msg->ddr_cmds_addrs[2] = cmd_db_read_addr("ACV");
As we are calling into cmd db. we should make sure that cmd_db_ready()
in adreno_bind().
> +
> + msg->ddr_cmds_data[0][0] = 0x40000000;
> + msg->ddr_cmds_data[0][1] = 0x40000000;
> + msg->ddr_cmds_data[0][2] = 0x40000000;
> +
> + /*
> + * These are the CX (CNOC) votes - these are used by the GMU but the
> + * votes are known and fixed for the target
> + */
> + msg->cnoc_cmds_num = 1;
> + msg->cnoc_wait_bitmask = 0x01;
> +
> + msg->cnoc_cmds_addrs[0] = cmd_db_read_addr("CN0");
> + msg->cnoc_cmds_data[0][0] = 0x40000000;
> + msg->cnoc_cmds_data[1][0] = 0x60000001;
> +}
> +
> static void a660_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
> {
> /*
> @@ -531,6 +563,8 @@ static int a6xx_hfi_send_bw_table(struct a6xx_gmu *gmu)
> adreno_7c3_build_bw_table(&msg);
> else if (adreno_is_a660(adreno_gpu))
> a660_build_bw_table(&msg);
> + else if (adreno_is_a690(adreno_gpu))
> + a690_build_bw_table(&msg);
> else
> a6xx_build_bw_table(&msg);
>
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
> index ca38b837dedb..437515e46e5a 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> @@ -355,6 +355,20 @@ static const struct adreno_info gpulist[] = {
> .init = a6xx_gpu_init,
> .zapfw = "a640_zap.mdt",
> .hwcg = a640_hwcg,
> + }, {
> + .rev = ADRENO_REV(6, 9, 0, ANY_ID),
> + .revn = 690,
> + .name = "A690",
> + .fw = {
> + [ADRENO_FW_SQE] = "a660_sqe.fw",
If it uses a660 sqe, should it also belong to a660 family? Or is it
significantly different?
> + [ADRENO_FW_GMU] = "a690_gmu.bin",
> + },
> + .gmem = SZ_4M,
> + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> + .init = a6xx_gpu_init,
> + .zapfw = "a690_zap.mdt",
> + .hwcg = a690_hwcg,
> + .address_space_size = SZ_16G,
> },
> };
>
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index b4f9b1343d63..da29bd392388 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -55,7 +55,7 @@ struct adreno_reglist {
> u32 value;
> };
>
> -extern const struct adreno_reglist a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[], a660_hwcg[];
> +extern const struct adreno_reglist a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[], a660_hwcg[], a690_hwcg[];
>
> struct adreno_info {
> struct adreno_rev rev;
> @@ -272,6 +272,11 @@ static inline int adreno_is_a660(struct adreno_gpu *gpu)
> return gpu->revn == 660;
> }
>
> +static inline int adreno_is_a690(struct adreno_gpu *gpu)
> +{
> + return gpu->revn == 690;
> +};
> +
> /* check for a615, a616, a618, a619 or any derivatives */
> static inline int adreno_is_a615_family(struct adreno_gpu *gpu)
> {
> @@ -286,7 +291,8 @@ static inline int adreno_is_a660_family(struct adreno_gpu *gpu)
> /* check for a650, a660, or any derivatives */
> static inline int adreno_is_a650_family(struct adreno_gpu *gpu)
> {
> - return gpu->revn == 650 || gpu->revn == 620 || adreno_is_a660_family(gpu);
> + return gpu->revn == 650 || gpu->revn == 620 || gpu->revn == 690 ||
> + adreno_is_a660_family(gpu);
> }
>
> u64 adreno_private_address_space_size(struct msm_gpu *gpu);
--
With best wishes
Dmitry
On Tue, Feb 7, 2023 at 7:41 PM Bjorn Andersson
<[email protected]> wrote:
>
> From: Bjorn Andersson <[email protected]>
>
> Introduce support for the Adreno A690, found in Qualcomm SC8280XP.
>
> Signed-off-by: Bjorn Andersson <[email protected]>
> Signed-off-by: Bjorn Andersson <[email protected]>
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 120 ++++++++++++++++++++-
> drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 34 ++++++
> drivers/gpu/drm/msm/adreno/adreno_device.c | 14 +++
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 10 +-
> 4 files changed, 173 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index aae60cbd9164..81dfcc5073ad 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -588,6 +588,63 @@ const struct adreno_reglist a660_hwcg[] = {
> {},
> };
>
> +const struct adreno_reglist a690_hwcg[] = {
> + {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
> + {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
> + {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
> + {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
> + {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
> + {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
> + {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
> + {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
> + {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
> + {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
> + {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
> + {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
> + {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
> + {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
> + {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
> + {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
> + {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
> + {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
> + {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
> + {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
> + {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
> + {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
> + {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
> + {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
> + {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
> + {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
> + {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
> + {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
> + {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
> + {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
> + {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
> + {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
> + {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
> + {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
> + {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
> + {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
> + {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
> + {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
> + {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
> + {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
> + {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
> + {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
> + {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
> + {REG_A6XX_RBBM_CLOCK_CNTL, 0x8AA8AA82},
> + {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
> + {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
> + {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
> + {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
> + {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
> + {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
> + {REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, 0x20200},
> + {REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, 0x10111},
> + {REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, 0x5555},
> + {}
> +};
> +
> static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
> {
> struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
> @@ -747,6 +804,45 @@ static const u32 a660_protect[] = {
> A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */
> };
>
> +/* These are for a690 */
> +static const u32 a690_protect[] = {
> + A6XX_PROTECT_RDONLY(0x00000, 0x004ff),
> + A6XX_PROTECT_RDONLY(0x00501, 0x00001),
> + A6XX_PROTECT_RDONLY(0x0050b, 0x002f4),
> + A6XX_PROTECT_NORDWR(0x0050e, 0x00000),
> + A6XX_PROTECT_NORDWR(0x00510, 0x00000),
> + A6XX_PROTECT_NORDWR(0x00534, 0x00000),
> + A6XX_PROTECT_NORDWR(0x00800, 0x00082),
> + A6XX_PROTECT_NORDWR(0x008a0, 0x00008),
> + A6XX_PROTECT_NORDWR(0x008ab, 0x00024),
> + A6XX_PROTECT_RDONLY(0x008d0, 0x000bc),
There is a slight difference from downstream here, upstream userspace
needs access to CP_PERFCTR_CP_SEL so this range starts at 0x008de. I
*think* that is the only major difference in CP_PROTECT settings.
BR,
-R
> + A6XX_PROTECT_NORDWR(0x00900, 0x0004d),
> + A6XX_PROTECT_NORDWR(0x0098d, 0x00272),
> + A6XX_PROTECT_NORDWR(0x00e00, 0x00001),
> + A6XX_PROTECT_NORDWR(0x00e03, 0x0000c),
> + A6XX_PROTECT_NORDWR(0x03c00, 0x000c3),
> + A6XX_PROTECT_RDONLY(0x03cc4, 0x01fff),
> + A6XX_PROTECT_NORDWR(0x08630, 0x001cf),
> + A6XX_PROTECT_NORDWR(0x08e00, 0x00000),
> + A6XX_PROTECT_NORDWR(0x08e08, 0x00008),
> + A6XX_PROTECT_NORDWR(0x08e50, 0x0001f),
> + A6XX_PROTECT_NORDWR(0x08e80, 0x0027f),
> + A6XX_PROTECT_NORDWR(0x09624, 0x001db),
> + A6XX_PROTECT_NORDWR(0x09e60, 0x00011),
> + A6XX_PROTECT_NORDWR(0x09e78, 0x00187),
> + A6XX_PROTECT_NORDWR(0x0a630, 0x001cf),
> + A6XX_PROTECT_NORDWR(0x0ae02, 0x00000),
> + A6XX_PROTECT_NORDWR(0x0ae50, 0x0012f),
> + A6XX_PROTECT_NORDWR(0x0b604, 0x00000),
> + A6XX_PROTECT_NORDWR(0x0b608, 0x00006),
> + A6XX_PROTECT_NORDWR(0x0be02, 0x00001),
> + A6XX_PROTECT_NORDWR(0x0be20, 0x0015f),
> + A6XX_PROTECT_NORDWR(0x0d000, 0x005ff),
> + A6XX_PROTECT_NORDWR(0x0f000, 0x00bff),
> + A6XX_PROTECT_RDONLY(0x0fc00, 0x01fff),
> + A6XX_PROTECT_NORDWR(0x11c00, 0x00000), /*note: infiite range */
> +};
> +
> static void a6xx_set_cp_protect(struct msm_gpu *gpu)
> {
> struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
> @@ -758,6 +854,11 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu)
> count = ARRAY_SIZE(a650_protect);
> count_max = 48;
> BUILD_BUG_ON(ARRAY_SIZE(a650_protect) > 48);
> + } else if (adreno_is_a690(adreno_gpu)) {
> + regs = a690_protect;
> + count = ARRAY_SIZE(a690_protect);
> + count_max = 48;
> + BUILD_BUG_ON(ARRAY_SIZE(a690_protect) > 48);
> } else if (adreno_is_a660_family(adreno_gpu)) {
> regs = a660_protect;
> count = ARRAY_SIZE(a660_protect);
> @@ -806,6 +907,13 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
> uavflagprd_inv = 2;
> }
>
> + if (adreno_is_a690(adreno_gpu)) {
> + lower_bit = 2;
> + amsbc = 1;
> + rgb565_predicator = 1;
> + uavflagprd_inv = 2;
> + }
> +
> if (adreno_is_7c3(adreno_gpu)) {
> lower_bit = 1;
> amsbc = 1;
> @@ -1065,13 +1173,18 @@ static int hw_init(struct msm_gpu *gpu)
> if (adreno_is_a660_family(adreno_gpu))
> gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020);
>
> + if (adreno_is_a690(adreno_gpu)) {
> + gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x0);
> + gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020);
> + }
> +
> /* Setting the mem pool size */
> gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128);
>
> /* Setting the primFifo thresholds default values,
> * and vccCacheSkipDis=1 bit (0x200) for A640 and newer
> */
> - if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu))
> + if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu) || adreno_is_a690(adreno_gpu))
> gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200);
> else if (adreno_is_a640_family(adreno_gpu) || adreno_is_7c3(adreno_gpu))
> gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200);
> @@ -1579,7 +1692,7 @@ static void a6xx_llc_activate(struct a6xx_gpu *a6xx_gpu)
> /* On A660, the SCID programming for UCHE traffic is done in
> * A6XX_GBIF_SCACHE_CNTL0[14:10]
> */
> - if (adreno_is_a660_family(adreno_gpu))
> + if (adreno_is_a660_family(adreno_gpu) || adreno_is_a690(adreno_gpu))
> gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL0, (0x1f << 10) |
> (1 << 8), (gpu_scid << 10) | (1 << 8));
> }
> @@ -2006,7 +2119,8 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
> info = adreno_info(config->rev);
>
> if (info && (info->revn == 650 || info->revn == 660 ||
> - adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), info->rev)))
> + info->revn == 690 ||
> + adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), info->rev)))
> adreno_gpu->base.hw_apriv = true;
>
> a6xx_llc_slices_init(pdev, a6xx_gpu);
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
> index 2cc83e049613..4d6d68a25931 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
> @@ -4,6 +4,7 @@
> #include <linux/completion.h>
> #include <linux/circ_buf.h>
> #include <linux/list.h>
> +#include <soc/qcom/cmd-db.h>
>
> #include "a6xx_gmu.h"
> #include "a6xx_gmu.xml.h"
> @@ -414,6 +415,37 @@ static void a650_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
> msg->cnoc_cmds_data[1][0] = 0x60000001;
> }
>
> +static void a690_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
> +{
> + /*
> + * Send a single "off" entry just to get things running
> + * TODO: bus scaling
> + */
> + msg->bw_level_num = 1;
> +
> + msg->ddr_cmds_num = 3;
> + msg->ddr_wait_bitmask = 0x01;
> +
> + msg->ddr_cmds_addrs[0] = cmd_db_read_addr("SH0");
> + msg->ddr_cmds_addrs[1] = cmd_db_read_addr("MC0");
> + msg->ddr_cmds_addrs[2] = cmd_db_read_addr("ACV");
> +
> + msg->ddr_cmds_data[0][0] = 0x40000000;
> + msg->ddr_cmds_data[0][1] = 0x40000000;
> + msg->ddr_cmds_data[0][2] = 0x40000000;
> +
> + /*
> + * These are the CX (CNOC) votes - these are used by the GMU but the
> + * votes are known and fixed for the target
> + */
> + msg->cnoc_cmds_num = 1;
> + msg->cnoc_wait_bitmask = 0x01;
> +
> + msg->cnoc_cmds_addrs[0] = cmd_db_read_addr("CN0");
> + msg->cnoc_cmds_data[0][0] = 0x40000000;
> + msg->cnoc_cmds_data[1][0] = 0x60000001;
> +}
> +
> static void a660_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
> {
> /*
> @@ -531,6 +563,8 @@ static int a6xx_hfi_send_bw_table(struct a6xx_gmu *gmu)
> adreno_7c3_build_bw_table(&msg);
> else if (adreno_is_a660(adreno_gpu))
> a660_build_bw_table(&msg);
> + else if (adreno_is_a690(adreno_gpu))
> + a690_build_bw_table(&msg);
> else
> a6xx_build_bw_table(&msg);
>
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
> index ca38b837dedb..437515e46e5a 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> @@ -355,6 +355,20 @@ static const struct adreno_info gpulist[] = {
> .init = a6xx_gpu_init,
> .zapfw = "a640_zap.mdt",
> .hwcg = a640_hwcg,
> + }, {
> + .rev = ADRENO_REV(6, 9, 0, ANY_ID),
> + .revn = 690,
> + .name = "A690",
> + .fw = {
> + [ADRENO_FW_SQE] = "a660_sqe.fw",
> + [ADRENO_FW_GMU] = "a690_gmu.bin",
> + },
> + .gmem = SZ_4M,
> + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> + .init = a6xx_gpu_init,
> + .zapfw = "a690_zap.mdt",
> + .hwcg = a690_hwcg,
> + .address_space_size = SZ_16G,
> },
> };
>
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index b4f9b1343d63..da29bd392388 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -55,7 +55,7 @@ struct adreno_reglist {
> u32 value;
> };
>
> -extern const struct adreno_reglist a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[], a660_hwcg[];
> +extern const struct adreno_reglist a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[], a660_hwcg[], a690_hwcg[];
>
> struct adreno_info {
> struct adreno_rev rev;
> @@ -272,6 +272,11 @@ static inline int adreno_is_a660(struct adreno_gpu *gpu)
> return gpu->revn == 660;
> }
>
> +static inline int adreno_is_a690(struct adreno_gpu *gpu)
> +{
> + return gpu->revn == 690;
> +};
> +
> /* check for a615, a616, a618, a619 or any derivatives */
> static inline int adreno_is_a615_family(struct adreno_gpu *gpu)
> {
> @@ -286,7 +291,8 @@ static inline int adreno_is_a660_family(struct adreno_gpu *gpu)
> /* check for a650, a660, or any derivatives */
> static inline int adreno_is_a650_family(struct adreno_gpu *gpu)
> {
> - return gpu->revn == 650 || gpu->revn == 620 || adreno_is_a660_family(gpu);
> + return gpu->revn == 650 || gpu->revn == 620 || gpu->revn == 690 ||
> + adreno_is_a660_family(gpu);
> }
>
> u64 adreno_private_address_space_size(struct msm_gpu *gpu);
> --
> 2.39.1
>
On Tue, 7 Feb 2023 19:40:50 -0800
Bjorn Andersson <[email protected]> wrote:
> From: Bjorn Andersson <[email protected]>
>
> Introduce support for the Adreno A690, found in Qualcomm SC8280XP.
>
> Signed-off-by: Bjorn Andersson <[email protected]>
> Signed-off-by: Bjorn Andersson <[email protected]>
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 120 ++++++++++++++++++++-
> drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 34 ++++++
> drivers/gpu/drm/msm/adreno/adreno_device.c | 14 +++
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 10 +-
> 4 files changed, 173 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index aae60cbd9164..81dfcc5073ad 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -588,6 +588,63 @@ const struct adreno_reglist a660_hwcg[] = {
> {},
> };
>
> +const struct adreno_reglist a690_hwcg[] = {
> + {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
> + {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
> + {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
> + {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
> + {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
> + {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
> + {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
> + {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
> + {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
> + {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
> + {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
> + {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
> + {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
> + {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
> + {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
> + {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
> + {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
> + {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
> + {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
> + {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
> + {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
> + {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
> + {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
> + {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
> + {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
> + {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
> + {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
> + {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
> + {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
> + {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
> + {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
> + {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
> + {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
> + {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
> + {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
> + {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
> + {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
> + {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
> + {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
> + {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
> + {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
> + {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
> + {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
> + {REG_A6XX_RBBM_CLOCK_CNTL, 0x8AA8AA82},
> + {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
> + {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
> + {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
> + {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
> + {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
> + {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
> + {REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, 0x20200},
> + {REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, 0x10111},
> + {REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, 0x5555},
> + {}
> +};
> +
> static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
> {
> struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
> @@ -747,6 +804,45 @@ static const u32 a660_protect[] = {
> A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */
> };
>
> +/* These are for a690 */
> +static const u32 a690_protect[] = {
> + A6XX_PROTECT_RDONLY(0x00000, 0x004ff),
> + A6XX_PROTECT_RDONLY(0x00501, 0x00001),
> + A6XX_PROTECT_RDONLY(0x0050b, 0x002f4),
> + A6XX_PROTECT_NORDWR(0x0050e, 0x00000),
> + A6XX_PROTECT_NORDWR(0x00510, 0x00000),
> + A6XX_PROTECT_NORDWR(0x00534, 0x00000),
> + A6XX_PROTECT_NORDWR(0x00800, 0x00082),
> + A6XX_PROTECT_NORDWR(0x008a0, 0x00008),
> + A6XX_PROTECT_NORDWR(0x008ab, 0x00024),
> + A6XX_PROTECT_RDONLY(0x008d0, 0x000bc),
> + A6XX_PROTECT_NORDWR(0x00900, 0x0004d),
> + A6XX_PROTECT_NORDWR(0x0098d, 0x00272),
> + A6XX_PROTECT_NORDWR(0x00e00, 0x00001),
> + A6XX_PROTECT_NORDWR(0x00e03, 0x0000c),
> + A6XX_PROTECT_NORDWR(0x03c00, 0x000c3),
> + A6XX_PROTECT_RDONLY(0x03cc4, 0x01fff),
> + A6XX_PROTECT_NORDWR(0x08630, 0x001cf),
> + A6XX_PROTECT_NORDWR(0x08e00, 0x00000),
> + A6XX_PROTECT_NORDWR(0x08e08, 0x00008),
> + A6XX_PROTECT_NORDWR(0x08e50, 0x0001f),
> + A6XX_PROTECT_NORDWR(0x08e80, 0x0027f),
> + A6XX_PROTECT_NORDWR(0x09624, 0x001db),
> + A6XX_PROTECT_NORDWR(0x09e60, 0x00011),
> + A6XX_PROTECT_NORDWR(0x09e78, 0x00187),
> + A6XX_PROTECT_NORDWR(0x0a630, 0x001cf),
> + A6XX_PROTECT_NORDWR(0x0ae02, 0x00000),
> + A6XX_PROTECT_NORDWR(0x0ae50, 0x0012f),
> + A6XX_PROTECT_NORDWR(0x0b604, 0x00000),
> + A6XX_PROTECT_NORDWR(0x0b608, 0x00006),
> + A6XX_PROTECT_NORDWR(0x0be02, 0x00001),
> + A6XX_PROTECT_NORDWR(0x0be20, 0x0015f),
> + A6XX_PROTECT_NORDWR(0x0d000, 0x005ff),
> + A6XX_PROTECT_NORDWR(0x0f000, 0x00bff),
> + A6XX_PROTECT_RDONLY(0x0fc00, 0x01fff),
> + A6XX_PROTECT_NORDWR(0x11c00, 0x00000), /*note: infiite range */
> +};
> +
> static void a6xx_set_cp_protect(struct msm_gpu *gpu)
> {
> struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
> @@ -758,6 +854,11 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu)
> count = ARRAY_SIZE(a650_protect);
> count_max = 48;
> BUILD_BUG_ON(ARRAY_SIZE(a650_protect) > 48);
> + } else if (adreno_is_a690(adreno_gpu)) {
> + regs = a690_protect;
> + count = ARRAY_SIZE(a690_protect);
> + count_max = 48;
> + BUILD_BUG_ON(ARRAY_SIZE(a690_protect) > 48);
> } else if (adreno_is_a660_family(adreno_gpu)) {
> regs = a660_protect;
> count = ARRAY_SIZE(a660_protect);
> @@ -806,6 +907,13 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
> uavflagprd_inv = 2;
> }
>
> + if (adreno_is_a690(adreno_gpu)) {
> + lower_bit = 2;
> + amsbc = 1;
> + rgb565_predicator = 1;
> + uavflagprd_inv = 2;
> + }
> +
> if (adreno_is_7c3(adreno_gpu)) {
> lower_bit = 1;
> amsbc = 1;
> @@ -1065,13 +1173,18 @@ static int hw_init(struct msm_gpu *gpu)
> if (adreno_is_a660_family(adreno_gpu))
> gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020);
>
> + if (adreno_is_a690(adreno_gpu)) {
> + gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x0);
> + gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020);
> + }
> +
> /* Setting the mem pool size */
> gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128);
>
> /* Setting the primFifo thresholds default values,
> * and vccCacheSkipDis=1 bit (0x200) for A640 and newer
> */
> - if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu))
> + if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu) || adreno_is_a690(adreno_gpu))
> gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200);
> else if (adreno_is_a640_family(adreno_gpu) || adreno_is_7c3(adreno_gpu))
> gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200);
> @@ -1579,7 +1692,7 @@ static void a6xx_llc_activate(struct a6xx_gpu *a6xx_gpu)
> /* On A660, the SCID programming for UCHE traffic is done in
> * A6XX_GBIF_SCACHE_CNTL0[14:10]
> */
> - if (adreno_is_a660_family(adreno_gpu))
> + if (adreno_is_a660_family(adreno_gpu) || adreno_is_a690(adreno_gpu))
> gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL0, (0x1f << 10) |
> (1 << 8), (gpu_scid << 10) | (1 << 8));
> }
> @@ -2006,7 +2119,8 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
> info = adreno_info(config->rev);
>
> if (info && (info->revn == 650 || info->revn == 660 ||
> - adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), info->rev)))
> + info->revn == 690 ||
> + adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), info->rev)))
> adreno_gpu->base.hw_apriv = true;
>
> a6xx_llc_slices_init(pdev, a6xx_gpu);
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
> index 2cc83e049613..4d6d68a25931 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
> @@ -4,6 +4,7 @@
> #include <linux/completion.h>
> #include <linux/circ_buf.h>
> #include <linux/list.h>
> +#include <soc/qcom/cmd-db.h>
>
> #include "a6xx_gmu.h"
> #include "a6xx_gmu.xml.h"
> @@ -414,6 +415,37 @@ static void a650_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
> msg->cnoc_cmds_data[1][0] = 0x60000001;
> }
>
> +static void a690_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
> +{
> + /*
> + * Send a single "off" entry just to get things running
> + * TODO: bus scaling
> + */
> + msg->bw_level_num = 1;
> +
> + msg->ddr_cmds_num = 3;
> + msg->ddr_wait_bitmask = 0x01;
> +
> + msg->ddr_cmds_addrs[0] = cmd_db_read_addr("SH0");
> + msg->ddr_cmds_addrs[1] = cmd_db_read_addr("MC0");
> + msg->ddr_cmds_addrs[2] = cmd_db_read_addr("ACV");
> +
> + msg->ddr_cmds_data[0][0] = 0x40000000;
> + msg->ddr_cmds_data[0][1] = 0x40000000;
> + msg->ddr_cmds_data[0][2] = 0x40000000;
> +
> + /*
> + * These are the CX (CNOC) votes - these are used by the GMU but the
> + * votes are known and fixed for the target
> + */
> + msg->cnoc_cmds_num = 1;
> + msg->cnoc_wait_bitmask = 0x01;
> +
> + msg->cnoc_cmds_addrs[0] = cmd_db_read_addr("CN0");
> + msg->cnoc_cmds_data[0][0] = 0x40000000;
> + msg->cnoc_cmds_data[1][0] = 0x60000001;
> +}
> +
> static void a660_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
> {
> /*
> @@ -531,6 +563,8 @@ static int a6xx_hfi_send_bw_table(struct a6xx_gmu *gmu)
> adreno_7c3_build_bw_table(&msg);
> else if (adreno_is_a660(adreno_gpu))
> a660_build_bw_table(&msg);
> + else if (adreno_is_a690(adreno_gpu))
> + a690_build_bw_table(&msg);
> else
> a6xx_build_bw_table(&msg);
>
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
> index ca38b837dedb..437515e46e5a 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> @@ -355,6 +355,20 @@ static const struct adreno_info gpulist[] = {
> .init = a6xx_gpu_init,
> .zapfw = "a640_zap.mdt",
> .hwcg = a640_hwcg,
> + }, {
> + .rev = ADRENO_REV(6, 9, 0, ANY_ID),
> + .revn = 690,
> + .name = "A690",
> + .fw = {
> + [ADRENO_FW_SQE] = "a660_sqe.fw",
> + [ADRENO_FW_GMU] = "a690_gmu.bin",
> + },
> + .gmem = SZ_4M,
> + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> + .init = a6xx_gpu_init,
> + .zapfw = "a690_zap.mdt",
> + .hwcg = a690_hwcg,
> + .address_space_size = SZ_16G,
> },
> };
This needs
MODULE_FIRMWARE("qcom/a660_sqe.fw");
MODULE_FIRMWARE("qcom/a690_gmu.bin");
MODULE_FIRMWARE("qcom/a690_zap.mbn");
...Juerg
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index b4f9b1343d63..da29bd392388 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -55,7 +55,7 @@ struct adreno_reglist {
> u32 value;
> };
>
> -extern const struct adreno_reglist a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[], a660_hwcg[];
> +extern const struct adreno_reglist a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[], a660_hwcg[], a690_hwcg[];
>
> struct adreno_info {
> struct adreno_rev rev;
> @@ -272,6 +272,11 @@ static inline int adreno_is_a660(struct adreno_gpu *gpu)
> return gpu->revn == 660;
> }
>
> +static inline int adreno_is_a690(struct adreno_gpu *gpu)
> +{
> + return gpu->revn == 690;
> +};
> +
> /* check for a615, a616, a618, a619 or any derivatives */
> static inline int adreno_is_a615_family(struct adreno_gpu *gpu)
> {
> @@ -286,7 +291,8 @@ static inline int adreno_is_a660_family(struct adreno_gpu *gpu)
> /* check for a650, a660, or any derivatives */
> static inline int adreno_is_a650_family(struct adreno_gpu *gpu)
> {
> - return gpu->revn == 650 || gpu->revn == 620 || adreno_is_a660_family(gpu);
> + return gpu->revn == 650 || gpu->revn == 620 || gpu->revn == 690 ||
> + adreno_is_a660_family(gpu);
> }
>
> u64 adreno_private_address_space_size(struct msm_gpu *gpu);
> > diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > index ca38b837dedb..437515e46e5a 100644
> > --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> > +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > @@ -355,6 +355,20 @@ static const struct adreno_info gpulist[] = {
> > .init = a6xx_gpu_init,
> > .zapfw = "a640_zap.mdt",
> > .hwcg = a640_hwcg,
> > + }, {
> > + .rev = ADRENO_REV(6, 9, 0, ANY_ID),
> > + .revn = 690,
> > + .name = "A690",
> > + .fw = {
> > + [ADRENO_FW_SQE] = "a660_sqe.fw",
> > + [ADRENO_FW_GMU] = "a690_gmu.bin",
> > + },
> > + .gmem = SZ_4M,
> > + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > + .init = a6xx_gpu_init,
> > + .zapfw = "a690_zap.mdt",
> > + .hwcg = a690_hwcg,
> > + .address_space_size = SZ_16G,
> > },
> > };
>
> This needs
>
> MODULE_FIRMWARE("qcom/a660_sqe.fw");
> MODULE_FIRMWARE("qcom/a690_gmu.bin");
> MODULE_FIRMWARE("qcom/a690_zap.mbn");
Eek. That should be
MODULE_FIRMWARE("qcom/a690_zap.mdt");
>
> ...Juerg
>
>
> > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > index b4f9b1343d63..da29bd392388 100644
> > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > @@ -55,7 +55,7 @@ struct adreno_reglist {
> > u32 value;
> > };
> >
> > -extern const struct adreno_reglist a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[], a660_hwcg[];
> > +extern const struct adreno_reglist a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[], a660_hwcg[], a690_hwcg[];
> >
> > struct adreno_info {
> > struct adreno_rev rev;
> > @@ -272,6 +272,11 @@ static inline int adreno_is_a660(struct adreno_gpu *gpu)
> > return gpu->revn == 660;
> > }
> >
> > +static inline int adreno_is_a690(struct adreno_gpu *gpu)
> > +{
> > + return gpu->revn == 690;
> > +};
> > +
> > /* check for a615, a616, a618, a619 or any derivatives */
> > static inline int adreno_is_a615_family(struct adreno_gpu *gpu)
> > {
> > @@ -286,7 +291,8 @@ static inline int adreno_is_a660_family(struct adreno_gpu *gpu)
> > /* check for a650, a660, or any derivatives */
> > static inline int adreno_is_a650_family(struct adreno_gpu *gpu)
> > {
> > - return gpu->revn == 650 || gpu->revn == 620 || adreno_is_a660_family(gpu);
> > + return gpu->revn == 650 || gpu->revn == 620 || gpu->revn == 690 ||
> > + adreno_is_a660_family(gpu);
> > }
> >
> > u64 adreno_private_address_space_size(struct msm_gpu *gpu);
>
On Tue, 7 Feb 2023 19:40:49 -0800, Bjorn Andersson wrote:
> This series introduces support for A690 in the DRM/MSM driver and
> enables it for the two SC8280XP laptops.
>
> Bjorn Andersson (3):
> drm/msm/adreno: Add Adreno A690 support
> arm64: dts: qcom: sc8280xp: Add GPU related nodes
> arm64: dts: qcom: sc8280xp: Enable GPU related nodes
>
> [...]
Applied, thanks!
[1/3] drm/msm/adreno: Add Adreno A690 support
(no commit info)
[2/3] arm64: dts: qcom: sc8280xp: Add GPU related nodes
commit: eec51ab2fd6f447a993c502364704d0cb5bc8cae
[3/3] arm64: dts: qcom: sc8280xp: Enable GPU related nodes
commit: 598a06afca5a2ab4850ce9ff8146ec728cca570c
Best regards,
--
Bjorn Andersson <[email protected]>