Adding of additional support to Cadence PCIe controller (i.e. pci-j721e.c)
for up to 4x lanes, and reworking of driver to define maximum lanes per
board configuration.
Changes from v1:
* Reworked 'PCI: j721e: Add PCIe 4x lane selection support' to not cause
regressions on 1-2x lane platforms
Changes from v2:
* Correct dev_warn format string from %d to %u since lane count is a
unsigned integer
* Update CC list
Changes from v3:
* Use the max_lanes setting per chip for the mask size required since
bootloader could have set num_lanes to a higher value that the
device tree which would leave in an undefined state
* Reorder patches do the previous change to not break bisect
* Remove line breaking for dev_warn to allow better grepping and since
no strict 80 columns anymore
Changes from v4:
* Correct invalid settings for j7200 PCIe RC + EP
* Add j784s4 configuration for selection of 4x lanes
Changes from v5:
* Dropped 'PCI: j721e: Add warnings on num-lanes misconfiguration' patch
from series
* Reworded 'PCI: j721e: Add per platform maximum lane settings' commit
message
* Added yaml documentation and schema checks for ti,j721e-pci-* lane
checking
Changes from v6:
* Fix wordwrapping in commit messages from ~65 columns to correct 75
columns
* Re-ran get_maintainers.pl to add missing maintainers in CC
Changes from v7:
* Addressed review comments in ti,j721e-pci-ep.yaml and
ti,j721e-pci-host.yaml from v6
* Added warn message if num-lanes property value is invalid.
* Addressed build issue reported in
https://lore.kernel.org/all/[email protected]/
Changes from v8:
* Use "const: 1" in ti,j721e-pci-ep.yaml and ti,j721e-pci-host.yaml
when num-lanes min and max values are equal.
Changes from v9:
* Rebase on next-20230315
Changes from v10:
* Rebase on next-20230317
Matt Ranostay (5):
dt-bindings: PCI: ti,j721e-pci-*: add checks for num-lanes
PCI: j721e: Add per platform maximum lane settings
PCI: j721e: Add PCIe 4x lane selection support
dt-bindings: PCI: ti,j721e-pci-*: add j784s4-pci-* compatible strings
PCI: j721e: add j784s4 PCIe configuration
.../bindings/pci/ti,j721e-pci-ep.yaml | 39 ++++++++++++++--
.../bindings/pci/ti,j721e-pci-host.yaml | 39 ++++++++++++++--
drivers/pci/controller/cadence/pci-j721e.c | 45 ++++++++++++++++---
3 files changed, 112 insertions(+), 11 deletions(-)
--
2.25.1
From: Matt Ranostay <[email protected]>
Add num-lanes schema checks based on compatible string on available lanes
for that platform.
Signed-off-by: Matt Ranostay <[email protected]>
Signed-off-by: Achal Verma <[email protected]>
---
.../bindings/pci/ti,j721e-pci-ep.yaml | 27 ++++++++++++++++---
.../bindings/pci/ti,j721e-pci-host.yaml | 27 ++++++++++++++++---
2 files changed, 48 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
index 10e6eabdff53..32e0c70ed801 100644
--- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
@@ -10,9 +10,6 @@ title: TI J721E PCI EP (PCIe Wrapper)
maintainers:
- Kishon Vijay Abraham I <[email protected]>
-allOf:
- - $ref: "cdns-pcie-ep.yaml#"
-
properties:
compatible:
oneOf:
@@ -65,6 +62,30 @@ properties:
items:
- const: link_state
+allOf:
+ - $ref: cdns-pcie-ep.yaml#
+ - if:
+ properties:
+ compatible:
+ enum:
+ - ti,am64-pcie-ep
+ then:
+ properties:
+ num-lanes:
+ const: 1
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ - ti,j7200-pcie-ep
+ - ti,j721e-pcie-ep
+ then:
+ properties:
+ num-lanes:
+ minimum: 1
+ maximum: 2
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
index 3d7aee97353a..2547088304e5 100644
--- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
+++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
@@ -10,9 +10,6 @@ title: TI J721E PCI Host (PCIe Wrapper)
maintainers:
- Kishon Vijay Abraham I <[email protected]>
-allOf:
- - $ref: "cdns-pcie-host.yaml#"
-
properties:
compatible:
oneOf:
@@ -94,6 +91,30 @@ properties:
interrupts:
maxItems: 1
+allOf:
+ - $ref: cdns-pcie-host.yaml#
+ - if:
+ properties:
+ compatible:
+ enum:
+ - ti,am64-pcie-host
+ then:
+ properties:
+ num-lanes:
+ const: 1
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ - ti,j7200-pcie-host
+ - ti,j721e-pcie-host
+ then:
+ properties:
+ num-lanes:
+ minimum: 1
+ maximum: 2
+
required:
- compatible
- reg
--
2.25.1
From: Matt Ranostay <[email protected]>
Various platforms have different maximum amount of lanes that can be
selected. Add max_lanes to struct j721e_pcie to allow for detection of this
which is needed to calculate the needed bitmask size for the possible lane
count.
Signed-off-by: Matt Ranostay <[email protected]>
Signed-off-by: Vignesh Raghavendra <[email protected]>
Signed-off-by: Achal Verma <[email protected]>
---
drivers/pci/controller/cadence/pci-j721e.c | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index cc83a8925ce0..f4dc2c5abedb 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -47,8 +47,6 @@ enum link_status {
#define GENERATION_SEL_MASK GENMASK(1, 0)
-#define MAX_LANES 2
-
struct j721e_pcie {
struct cdns_pcie *cdns_pcie;
struct clk *refclk;
@@ -71,6 +69,7 @@ struct j721e_pcie_data {
unsigned int quirk_disable_flr:1;
u32 linkdown_irq_regfield;
unsigned int byte_access_allowed:1;
+ unsigned int max_lanes;
};
static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset)
@@ -290,11 +289,13 @@ static const struct j721e_pcie_data j721e_pcie_rc_data = {
.quirk_retrain_flag = true,
.byte_access_allowed = false,
.linkdown_irq_regfield = LINK_DOWN,
+ .max_lanes = 2,
};
static const struct j721e_pcie_data j721e_pcie_ep_data = {
.mode = PCI_MODE_EP,
.linkdown_irq_regfield = LINK_DOWN,
+ .max_lanes = 2,
};
static const struct j721e_pcie_data j7200_pcie_rc_data = {
@@ -302,23 +303,27 @@ static const struct j721e_pcie_data j7200_pcie_rc_data = {
.quirk_detect_quiet_flag = true,
.linkdown_irq_regfield = J7200_LINK_DOWN,
.byte_access_allowed = true,
+ .max_lanes = 2,
};
static const struct j721e_pcie_data j7200_pcie_ep_data = {
.mode = PCI_MODE_EP,
.quirk_detect_quiet_flag = true,
.quirk_disable_flr = true,
+ .max_lanes = 2,
};
static const struct j721e_pcie_data am64_pcie_rc_data = {
.mode = PCI_MODE_RC,
.linkdown_irq_regfield = J7200_LINK_DOWN,
.byte_access_allowed = true,
+ .max_lanes = 1,
};
static const struct j721e_pcie_data am64_pcie_ep_data = {
.mode = PCI_MODE_EP,
.linkdown_irq_regfield = J7200_LINK_DOWN,
+ .max_lanes = 1,
};
static const struct of_device_id of_j721e_pcie_match[] = {
@@ -432,8 +437,10 @@ static int j721e_pcie_probe(struct platform_device *pdev)
pcie->user_cfg_base = base;
ret = of_property_read_u32(node, "num-lanes", &num_lanes);
- if (ret || num_lanes > MAX_LANES)
+ if (ret || num_lanes > data->max_lanes) {
+ dev_warn(dev, "num-lanes property not provided or invalid, setting num-lanes to 1\n");
num_lanes = 1;
+ }
pcie->num_lanes = num_lanes;
if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)))
--
2.25.1
From: Matt Ranostay <[email protected]>
Add definition for j784s4-pci-ep + j784s4-pci-host devices along with
schema checks for num-lanes.
Signed-off-by: Matt Ranostay <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Achal Verma <[email protected]>
---
.../devicetree/bindings/pci/ti,j721e-pci-ep.yaml | 12 ++++++++++++
.../devicetree/bindings/pci/ti,j721e-pci-host.yaml | 12 ++++++++++++
2 files changed, 24 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
index 32e0c70ed801..d2fbf1f7aa54 100644
--- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
@@ -14,6 +14,7 @@ properties:
compatible:
oneOf:
- const: ti,j721e-pcie-ep
+ - const: ti,j784s4-pcie-ep
- description: PCIe EP controller in AM64
items:
- const: ti,am64-pcie-ep
@@ -86,6 +87,17 @@ allOf:
minimum: 1
maximum: 2
+ - if:
+ properties:
+ compatible:
+ enum:
+ - ti,j784s4-pcie-ep
+ then:
+ properties:
+ num-lanes:
+ minimum: 1
+ maximum: 4
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
index 2547088304e5..e41d6f403493 100644
--- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
+++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
@@ -14,6 +14,7 @@ properties:
compatible:
oneOf:
- const: ti,j721e-pcie-host
+ - const: ti,j784s4-pcie-host
- description: PCIe controller in AM64
items:
- const: ti,am64-pcie-host
@@ -115,6 +116,17 @@ allOf:
minimum: 1
maximum: 2
+ - if:
+ properties:
+ compatible:
+ enum:
+ - ti,j784s4-pcie-host
+ then:
+ properties:
+ num-lanes:
+ minimum: 1
+ maximum: 4
+
required:
- compatible
- reg
--
2.25.1
From: Matt Ranostay <[email protected]>
Add PCIe configuration for j784s4 platform which has 4x lane support.
Tested-by: Achal Verma <[email protected]>
Signed-off-by: Matt Ranostay <[email protected]>
Reviewed-by: Roger Quadros <[email protected]>
Signed-off-by: Achal Verma <[email protected]>
---
drivers/pci/controller/cadence/pci-j721e.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index 58dcac9021e4..cce7b391f931 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -330,6 +330,20 @@ static const struct j721e_pcie_data am64_pcie_ep_data = {
.max_lanes = 1,
};
+static const struct j721e_pcie_data j784s4_pcie_rc_data = {
+ .mode = PCI_MODE_RC,
+ .quirk_retrain_flag = true,
+ .byte_access_allowed = false,
+ .linkdown_irq_regfield = LINK_DOWN,
+ .max_lanes = 4,
+};
+
+static const struct j721e_pcie_data j784s4_pcie_ep_data = {
+ .mode = PCI_MODE_EP,
+ .linkdown_irq_regfield = LINK_DOWN,
+ .max_lanes = 4,
+};
+
static const struct of_device_id of_j721e_pcie_match[] = {
{
.compatible = "ti,j721e-pcie-host",
@@ -355,6 +369,14 @@ static const struct of_device_id of_j721e_pcie_match[] = {
.compatible = "ti,am64-pcie-ep",
.data = &am64_pcie_ep_data,
},
+ {
+ .compatible = "ti,j784s4-pcie-host",
+ .data = &j784s4_pcie_rc_data,
+ },
+ {
+ .compatible = "ti,j784s4-pcie-ep",
+ .data = &j784s4_pcie_ep_data,
+ },
{},
};
--
2.25.1
From: Matt Ranostay <[email protected]>
Add support for setting of two-bit field that allows selection of 4x lane
PCIe which was previously limited to only 2x lanes.
Signed-off-by: Matt Ranostay <[email protected]>
Reviewed-by: Vignesh Raghavendra <[email protected]>
Reviewed-by: Roger Quadros <[email protected]>
Signed-off-by: Achal Verma <[email protected]>
---
drivers/pci/controller/cadence/pci-j721e.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index f4dc2c5abedb..58dcac9021e4 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -42,7 +42,6 @@ enum link_status {
};
#define J721E_MODE_RC BIT(7)
-#define LANE_COUNT_MASK BIT(8)
#define LANE_COUNT(n) ((n) << 8)
#define GENERATION_SEL_MASK GENMASK(1, 0)
@@ -52,6 +51,7 @@ struct j721e_pcie {
struct clk *refclk;
u32 mode;
u32 num_lanes;
+ u32 max_lanes;
void __iomem *user_cfg_base;
void __iomem *intd_cfg_base;
u32 linkdown_irq_regfield;
@@ -205,11 +205,15 @@ static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie,
{
struct device *dev = pcie->cdns_pcie->dev;
u32 lanes = pcie->num_lanes;
+ u32 mask = BIT(8);
u32 val = 0;
int ret;
+ if (pcie->max_lanes == 4)
+ mask = GENMASK(9, 8);
+
val = LANE_COUNT(lanes - 1);
- ret = regmap_update_bits(syscon, offset, LANE_COUNT_MASK, val);
+ ret = regmap_update_bits(syscon, offset, mask, val);
if (ret)
dev_err(dev, "failed to set link count\n");
@@ -441,7 +445,9 @@ static int j721e_pcie_probe(struct platform_device *pdev)
dev_warn(dev, "num-lanes property not provided or invalid, setting num-lanes to 1\n");
num_lanes = 1;
}
+
pcie->num_lanes = num_lanes;
+ pcie->max_lanes = data->max_lanes;
if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)))
return -EINVAL;
--
2.25.1
On 17/03/2023 08:51, Achal Verma wrote:
> From: Matt Ranostay <[email protected]>
>
> Add num-lanes schema checks based on compatible string on available lanes
> for that platform.
>
> Signed-off-by: Matt Ranostay <[email protected]>
> Signed-off-by: Achal Verma <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof