2023-03-23 12:32:33

by Thomas Richter

Subject: [PATCH] perf list: Remove UTF-8 characters from json file

commit 7f76b3113068 ("perf list: Add IBM z16 event description for s390")
contains the verbal description for z16 extended counter set.
However some entries of the public description contain
UTF-8 characters which brakes the build on some distros.

Fix this and remove the UTF-8 characters.

Fixes: 7f76b3113068 ("perf list: Add IBM z16 event description for s390")
Reported-by: Arnaldo Carvalho de Melo <[email protected]>
Signed-off-by: Thomas Richter <[email protected]>
---
tools/perf/pmu-events/arch/s390/cf_z16/extended.json | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/tools/perf/pmu-events/arch/s390/cf_z16/extended.json b/tools/perf/pmu-events/arch/s390/cf_z16/extended.json
index c306190fc06f..c2b10ec1c6e0 100644
--- a/tools/perf/pmu-events/arch/s390/cf_z16/extended.json
+++ b/tools/perf/pmu-events/arch/s390/cf_z16/extended.json
@@ -95,28 +95,28 @@
"EventCode": "145",
"EventName": "DCW_REQ",
"BriefDescription": "Directory Write Level 1 Data Cache from Cache",
- "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache."
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache."
},
{
"Unit": "CPU-M-CF",
"EventCode": "146",
"EventName": "DCW_REQ_IV",
"BriefDescription": "Directory Write Level 1 Data Cache from Cache with Intervention",
- "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache with intervention."
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache with intervention."
},
{
"Unit": "CPU-M-CF",
"EventCode": "147",
"EventName": "DCW_REQ_CHIP_HIT",
"BriefDescription": "Directory Write Level 1 Data Cache from Cache with Chip HP Hit",
- "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache after using chip level horizontal persistence, Chip-HP hit."
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache after using chip level horizontal persistence, Chip-HP hit."
},
{
"Unit": "CPU-M-CF",
"EventCode": "148",
"EventName": "DCW_REQ_DRAWER_HIT",
"BriefDescription": "Directory Write Level 1 Data Cache from Cache with Drawer HP Hit",
- "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit."
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit."
},
{
"Unit": "CPU-M-CF",
@@ -284,7 +284,7 @@
"EventCode": "172",
"EventName": "ICW_REQ_DRAWER_HIT",
"BriefDescription": "Directory Write Level 1 Instruction Cache from Cache with Drawer HP Hit",
- "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestor’s Level-2 cache using drawer level horizontal persistence, Drawer-HP hit."
+ "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestors Level-2 cache using drawer level horizontal persistence, Drawer-HP hit."
},
{
"Unit": "CPU-M-CF",
--
2.17.1

2023-03-23 13:37:33

by Arnaldo Carvalho de Melo

Subject: Re: [PATCH] perf list: Remove UTF-8 characters from json file

Em Thu, Mar 23, 2023 at 01:25:32PM +0100, Thomas Richter escreveu:
> commit 7f76b3113068 ("perf list: Add IBM z16 event description for s390")
> contains the verbal description for z16 extended counter set.
> However some entries of the public description contain
> UTF-8 characters which brakes the build on some distros.
>
> Fix this and remove the UTF-8 characters.

Thanks, tested and applied. Now its some power9 file failing...

- Arnaldo


> Fixes: 7f76b3113068 ("perf list: Add IBM z16 event description for s390")
> Reported-by: Arnaldo Carvalho de Melo <[email protected]>
> Signed-off-by: Thomas Richter <[email protected]>
> ---
> tools/perf/pmu-events/arch/s390/cf_z16/extended.json | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/tools/perf/pmu-events/arch/s390/cf_z16/extended.json b/tools/perf/pmu-events/arch/s390/cf_z16/extended.json
> index c306190fc06f..c2b10ec1c6e0 100644
> --- a/tools/perf/pmu-events/arch/s390/cf_z16/extended.json
> +++ b/tools/perf/pmu-events/arch/s390/cf_z16/extended.json
> @@ -95,28 +95,28 @@
> "EventCode": "145",
> "EventName": "DCW_REQ",
> "BriefDescription": "Directory Write Level 1 Data Cache from Cache",
> - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache."
> + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache."
> },
> {
> "Unit": "CPU-M-CF",
> "EventCode": "146",
> "EventName": "DCW_REQ_IV",
> "BriefDescription": "Directory Write Level 1 Data Cache from Cache with Intervention",
> - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache with intervention."
> + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache with intervention."
> },
> {
> "Unit": "CPU-M-CF",
> "EventCode": "147",
> "EventName": "DCW_REQ_CHIP_HIT",
> "BriefDescription": "Directory Write Level 1 Data Cache from Cache with Chip HP Hit",
> - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache after using chip level horizontal persistence, Chip-HP hit."
> + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache after using chip level horizontal persistence, Chip-HP hit."
> },
> {
> "Unit": "CPU-M-CF",
> "EventCode": "148",
> "EventName": "DCW_REQ_DRAWER_HIT",
> "BriefDescription": "Directory Write Level 1 Data Cache from Cache with Drawer HP Hit",
> - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit."
> + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit."
> },
> {
> "Unit": "CPU-M-CF",
> @@ -284,7 +284,7 @@
> "EventCode": "172",
> "EventName": "ICW_REQ_DRAWER_HIT",
> "BriefDescription": "Directory Write Level 1 Instruction Cache from Cache with Drawer HP Hit",
> - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestor’s Level-2 cache using drawer level horizontal persistence, Drawer-HP hit."
> + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestors Level-2 cache using drawer level horizontal persistence, Drawer-HP hit."
> },
> {
> "Unit": "CPU-M-CF",
> --
> 2.17.1
>

--

- Arnaldo